Datasheet CXP87248A, CXP87240A Datasheet (Sony)

CXP87240A/87248A

CMOS 8-bit Single Chip Microcomputer

Description

The CXP87240A/87248A is a CMOS 8-bit micro­computer which consists of A/D converter, serial
interface, timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuit, PWM generator, PWM for tuner, VISS/VASS
circuit, 32kHz timer/event counter, remote control
receiving circuit, general purpose prescaler, HSYNC
counter, VCR vertical sync separation circuit and the
measuring circuit which measure signals of capstan
FG and drum FG/PG and other servo systems, as
well as basic configurations like 8-bit CPU, ROM,
RAM and I/O port. They are integrated into a single
chip.

Also CXP87240A/87248A provides sleep/stop
function which enables to lower power consumption
and ultra-low speed instruction mode in 32kHz
operation.

100 pin QFP (PIastic) 100 pin LQFP (PIastic)

Structure

Silicon gate CMOS IC

Features

• A wide instruction set (213 instructions) which cover various types of data

— 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction

• Minimum instruction cycle During operation 333ns/12MHz (3.0 to 5.5V)

During operation 250ns/16MHz (4.5 to 5.5V)
During operation 122µs/32kHz

• Incorporated ROM capacity 40Kbytes (CXP87240A), 48Kbytes (CXP87248A)

• Incorporated RAM capacity 1376bytes

• Peripheral functions

— A/D converter 8-bit, 12-channel, successive approximation system

(Conversion time 20.0µs/16MHz)

— Serial interface Incorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel

Incorporated 8-bit and 8-stage FIFO
(1 to 8 bytes auto transfer) 1-channel

— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer,

32kHz timer/counter

— High precision timing pattern generator PPG 19-pin 32-stage programmable

RTG 5-pin 2-channel

— PWM/DA gate output PWM 12-bit, 2-channel (Repetitive frequency 62kHz/16MHz)

DA gate pulse output 13-bit, 4-channel
— Servo input control Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit Incorporated 26-bit and 8-stage FIFO
— PWM output 14-bit, 1-channel
— VISS/VASS circuit Pulse duty auto detection circuit
— Remote control receiving circuit 8-bit pulse measuring counter, 6-stage FIFO
— General purpose prescaler 7-bit (SYNC1 input frequency divided, FRC capture possible)
— HSYNC counter 12-bit event counter (counts the SYNC1 input.)

• Interruption 22 factors, 15 vectors, multi-interruption possible

• Standby mode SLEEP/STOP

• Package 100-pin plastic QFP/LQFP

• Piggyback/evaluation chip CXP87200A 100-pin ceramic QFP/LQFP

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E94833-ST

CXP87240A/87248A

Vss

DD

V
MP

RST
XTAL

EXTAL
TX

TEX

PE1/INT2
PI4/INT1/NMI

PE0/INT0

AVss

PA0 to PA7

PB0 to PB7

8

PORT A8PORT B8PORT C

CLOCK

GENERATOR/

SYSTEM CONTROL

SPC700

CPU CORE

NMI

2

RAM

PC0 to PC7

PD0 to PD7

PE0/CKOUT

8

PORT D

RAM

1376 BYTES

ROM

40K/48K BYTES

INTERRUPT CONTROLLER

2

FIFO

PE0 to PE1

PE2 to PE7

2

6

PORT E

2

2

2

PF4 to PF7

PF0 to PF3

4

PG0 to PG7

PH0 to PH7

4

PORT F8PORT G8PORT H7PORT I

32kHz

PRESCALER/

TIME BASE TIMER

TIMER/COUNTER

FIFO

FRC

CAPTURE UNIT

3

FIFO

PI1 to PI7

REALTIME

2

PJ0 to PJ7
8

PORT J

1

CH

PULSE

CH0

GENERATOR

RAM

PATTERN

GENERATOR

PROGRAMMABLE

4

2

PC7/RTO7

5

19

to

PC3/RTO3

PC2/PPO18

to

PA0/PPO0

AV

REF

AV

DD

AN0 to AN3

Block Diagram

A/D CONVERTER

SERIAL

12

SI0

CS0

PF0/AN4

PF7/AN11

to

SERIAL

INTERFACE UNIT

SCK0

PI7/SI1

PI6/SO1

(CH1)

PI5/SCK1

(CH0)

INTERFACE UNIT

SO0

8 BIT TIMER 1

8 BIT TIMER/COUNTER 0

PE1/EC

VSYNC SEPARATOR

PG5/SYNC1

PG4/SYNC0

PI3/TO/DDO

PG7/EXI1

PG6/EXI0

– 2 –

CONTROL

SERVO INPUT

CTL

DRUM

CAPSTAN

PG1/DFG

PG0/CFG

PG2/DPG

PG3/PBCTL

VISS/VASS

REMOCON INPUT

PI1/RMC

14 BIT PWM GENERATOR

PI2/PWM

HSYNC COUNTER

12 BIT PWM GENERATOR CH1

12 BIT PWM GENERATOR CH0

PE6/DAB0

PE4/DAA0

PE3/PWM1

PE2/PWM0

PROGRAMMABLE PRESCALER

PE7/DAB1

PE5/DAA1

PI3/ADJ

PE1/HCOUT

Pin Configuration 1 (Top View) 100-pin QFP package

PA7/PPO7

PA6/PPO6

PA5/PPO5

PA4/PPO4

PA3/PPO3

PA2/PPO2

PA1/PPO1

PA0/PPO0

PB7/PPO15

PB6/PPO14

NC

CXP87240A/87248A

SS

DD

V

TX

V

TEX

PI2/PWM

PI1/RMC

PI5/SCK1

PI4/INT1/NMI

PI3/TO/DDO/ADJ

PB5/PPO13
PB4/PPO12
PB3/PPO11
PB2/PPO10

PB1/PPO9

PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3

PC2/PPO18
PC1/PPO17
PC0/PPO16

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1

PJ0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0

100

99

98

1

2
3
4
5
6
7
8
9

10

11
12
13
14
15
16
17

18
19

20

21

22

23

24
25

26

27

28
29
30

32

31

33

95

93

94

96

97

35

36

34

92

37

38

39

91

40

90

41 42

89

88

87

43

44

84

86

85

46

45

47

81

82

83

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56

55

54
53
52
51

49

48

50

PI6/SO1
PI7/SI1
PE0/INT0/CKOUT
PE1/EC/INT2/HCOUT
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7

DD

AV
AVREF
AVSS
PF4/AN8

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

MP

RST

SS

V

XTAL

CS0

EXTAL

SI0

SO0

SCK0

Note) 1. NC (Pin 90) is always connected to VDD.

2. Vss (Pins 41 and 88) are both connected to GND.

– 3 –

PF6/AN10

PF7/AN11

PF5/AN9

Pin Configuration 2 (Top View) 100-pin LQFP package

NC

PA7/PPO7

PA6/PPO6

PA5/PPO5

PA4/PPO4

PA3/PPO3

PA2/PPO2

PA1/PPO1

PA0/PPO0

PB7/PPO15

PB6/PPO14

PB5/PPO13

PB4/PPO12

CXP87240A/87248A

SS

DD

V

TX

V

TEX

PI2/PWM

PI1/RMC

PI5/SCK1

PI4/INT1/NMI

PI3/TO/DDO/ADJ

PI7/SI1

PI6/SO1

PE0/INT0/CKOUT

PB3/PPO11
PB2/PPO10

PB1/PPO9
PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4

PC3/RTO3
PC2/PPO18
PC1/PPO17
PC0/PPO16

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1

PJ0
PD7
PD6
PD5
PD4
PD3

100

99

98
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19

20
21
22

23

24
25

27

28

26

95

93

94

96

97

30

31

29

92

32

33

34

89

88

91

90

35

36

87

37

38

39

84

86

85

40

41

42

81

82

83

43

80

78

79

46

45

44

47

76

77

75
74

73

72

71
70
69

68
67

66
65

64

63

62

61

60
59
58

57
56
55
54
53
52

51

49

48

50

PE1/EC/INT2/HCOUT
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7

DD

AV
AVREF

SS

MP

PD2

PD1

PD0

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

RST

V

XTAL

EXTAL

Note) 1. NC (Pin 88) is always connected to VDD.

2. Vss (Pins 39 and 86) are both connected to GND.

– 4 –

CS0

SI0

SO0

SCK0

PF6/AN10

PF7/AN11

PF4/AN8

PF5/AN9

SS

AV

Pin Description

Symbol I/O Description

(Port A)

PA0/PPO0

to

PA7/PPO7

Output/
Real time
output

8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

(Port B)

PB0/PPO8

to

PB7/PPO15

Output/
Real time
output

8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

PC0/PPO16

to

PC2/PPO18

I/O/
Real time
output

(Port C)
8-bit I/O port, enables to
specify I/O by bit unit.
Data is gated with PPO or

PC3/RTO3

to

PC7/RTO7

I/O/
Real time
output

RTO contents by OR-gate
and they are output.
(8 pins)

CXP87240A/87248A

Programmable pattern generator (PPG)
output.
Functions as high precision real time
pulse output port.
(19 pins)
PB0 and PB2 can be 3-state controlled
with PPG.

Real time pulse generator (RTG) output.
Functions as high precision real time
pulse output port. (5 pins)

PD0 to PD7

PE0/INT0/
CKOUT

PE1/EC/INT2/
HCOUT

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
AN0 to AN3
PF0/AN4

to

PF3/AN7
PF4/AN8

to

PF7/AN11

I/O

Input/Input/Output

Input/Input/Input/
Output

Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Input

Input/Input

Output/Input

(Port D)
8-bit I/O port. Enable to specify I/O by 4-bit unit.
Enables to drive 12mA sink current.
(8 pins)

I

nput pin to request external interruption.

Active when falling edge.

PC3 can be 3-state controlled with RTG.

(Port E)
8-bit port.
Lower 2 bits
are input

External event
input pin for
timer/counter.

System clock frequency division output.

Input pin to request
external interruption.
Active when falling edge.

Coincidence signal
output pin for
HSYNC counter.

pins and
upper 6 bits
are output

PWM output pins.
(2 pins)

pins.
(8 pins)

DA gate pulse output pins.
(4 pins)

Analog input pins to A/D converter. (12 pins)

(Port F)
Lower 4 bits are input port and upper 4 bits are output port.
Lower 4 bits also serve as standby release input pin.
(8 pins)

SCK0
SO0
SI0
CS0

I/O
Ouput
Input
Input

Serial clock (CH0) I/O pin.
Serial data (CH0) output pin.
Serial data (CH0) input pin.
Serial chip select (CH0) input pin.

– 5 –

Symbol I/O Description

CXP87240A/87248A

PG0/CFG
PG1/DFG
PG2/DPG

PG3/PBCTL
PG4/SYNC0

PG5/SYNC1
PG6/EXI0
PG7/EXI1

PH0 to PH7

PI1/RMC
PI2/PWM
PI3/TO/

DDO/ADJ
PI4/INT1/

NMI
PI5/SCK1

Input/Input
Input/Input
Input/Input

Input/Input
Input/Input

Input/Input
Input/Input
Input/Input

Output

I/O/Input
I/O/Output
I/O/Output/

Output/Output
I/O/Input/Input
I/O/I/O

Capstan FG input pin.
Drum FG input pin.
Drum PG input pin.

(Port G)
8-bit input port.

Playback CTL pulse input pin.
External event input pin of timer/counter.

(8 pins)

Composite sync signal input pin.

External input pin to FRC capture unit.

(Port H)
8-bit output port ; Medium withstand voltage (12V) and high current
(12mA), N-ch open drain output.
(8 pins)

Remote control receiving circuit input pin.
14-bit PWM output pin.

(Port I)
7-bit I/O port.
I/O port can be
specified by bit
unit.
(7 pins)

Timer/counter, CTL duty detection, 32kHz oscillation
adjustment output pin.

Input pin to request external interruption and
non-maskable interruption. Active when falling edge.

Serial clock (CH1) I/O pin.
PI6/SO1
PI7/SI1

PJ0 to PJ7

EXTAL
XTAL
TEX
TX

RST
MP
AVDD
AVREF
AVss
VDD
Vss

I/O/Output
I/O/Input

I/O

Input
Output
Input
Output

Input
Input

Input

Serial data (CH1) output pin.

Serial data (CH1) input pin.

(Port J)
8-bit I/O port. Function as standby release input can be specified by bit
unit. I/O can be specified by bit unit.

Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input the external clock to EXTAL pin and input
opposite phase clock to XTAL pin.

Connecting pin of crystal oscillator for 32kHz timer clock. When used
as event counter, input to TEX pin and leave TX pin open. (Feedback
resistor is not removed.)

System reset pin of active "L" level.
Microprocessor mode input pin. Always connect to GND.
Positive power supply pin of A/D converter.
Reference voltage input pin of A/D converter.
GND pin of A/D converter.
Positive power supply pin.
GND pin. Connect both Vss pins to GND.

– 6 –

AAA

AAA

A

AAA

Input/Output Circuit Formats for Pins

CXP87240A/87248A

Pin

PA0 /PPO0

to

PA7/PPO7
PB4/PPO12

to

PB7/PPO15

12 pins

PB0 /PPO8
PB2/PPO10

Port A
Port B

Data bus

PPO data

Port A or Port B

RD

PPO8 or PPO10

Circuit format

Output becomes active from Hi-Z
by data writing to port register.

When reset

Hi-Z

Hi-Z

2 pins

PB1/PPO9
PB3/PPO11

2 pins

PB0 or PB2 data

RD

Data bus

Output becomes active from Hi-Z
by data writing to port register.

PPO9 or PPO11

PPG control
status register bit 0
3-state control
selection

AA

PPO9 or PPO11

PB1 or PB3 data

Data bus

RD

Hi-Z

Output becomes active from Hi-Z
by data writing to port register.

– 7 –

CXP87240A/87248A

AAA

AAA

A

AAA

AAA

AAA

PC0/PPO16

to

PC2/PPO18
PC5/RTO5

to

PC7/RTO7

6 pins

Port C

Data bus

Data bus

PPO, RTO data

Port C data

Port C direction

RD (Port C)

RD (Port C direction)

RTO3

PC3 data

Circuit format

(Every bit)

When resetPin

Input
protection
circuit

IP

Hi-Z

PC3/RTO3

1 pins

PC4/RTO4

PC3 direction

Data bus

RD

Data bus

RD

RTG interruption
control register
bit7

AAA

3-state control selection

PC4 data

PC4 direction

Data bus

RD

Data bus

Hi-Z

RTO4

RTO4

Hi-Z

RTO data is OR-gate data of ch0 and ch1.

RD

1 pins

– 8 –

CXP87240A/87248A

PD0

to

PD7

8 pins

Port D

Data bus

Port E

Port E/PWM
selection register
bit 0, 1

Port D data

Port D direction

RD (Port D)

Circuit format

(Every 4 bits)

PD0 to 3
PD4 to 7

IP

High
current
12mA

When resetPin

Hi-Z

PE0/INT0/
CKOUT

1 pin

PE1/EC/INT2/
HCOUT

Data bus

Port E

From HSYNC
counter

RD

Hi-z control

HCOUT

Data bus

PS1
PS2
PS3

Interruption circuit

RD (Port E)

MPX

IP

Input
protection
circuit

Input
protection

IP

circuit

Hi-Z

Hi-Z

1 pin

To interruption circuit/
event counter

– 9 –

CXP87240A/87248A

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1

4 pins

PE6/DAB0
PE7/DAB1

Port E

Data bus

Port E

DA gate output
or PWM output

Hi-Z control

Port/DA output
select

DA gate output

Hi-Z control

Port/DA output
select

Port E data

RD (Port E)

Port E data

Circuit format

MPX

MPX

When resetPin

Hi-Z

H level

2 pins

AN0

to

AN3

4 pins

PF0/AN4

to

PF3/AN7

4 pins

Data bus

Port F

RD (Port E)

Input multiplexer

IP

Input multiplexer

IP

RD (Port F)

Data bus

A/D converter

A/D converter

Hi-Z

Hi-Z

– 10 –

CXP87240A/87248A

PF4/AN8

to

PF7/AN11

4 pins

PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1

8 pins

Circuit format

Port F

Port F data

Data bus

RD
(Port F)

Port/AD select

Port G

Schmitt input

IP

RD (Port G)

Note) For PG4/SYNC0, PG5/SYNC1, CMOS schmitt input and TTL schmitt
input can be selected with the mask option.

Servo input

Data bus

IP

Input multiplexer

A/D
converter

When resetPin

Hi-Z

Hi-Z

PH0

to

PH7

8 pins

PI2/PWM
PI3/TO/
DDO/ADJ

2 pins

Port H

Port H data

Data bus

RD (Port H)

Port I

Port I function
select

PI2: From 14-bit PWM
PI3: From timer/counter,
CTL duty detection circuit,
32kHz timer

Port I data

Port I direction

Data
bus

RD (Port I)

Medium withstand
voltage 12V

Hi-Z

High current
12mA

MPX

Hi-Z

IP

– 11 –

CXP87240A/87248A

A

A

PI1/RMC
PI4/INT1/NMI
PI7/SI1

3 pins

PI5/SCK1
PI6/SO1

2 pins

Port I

Data bus

PI1: To remote control circuit
PI4: To interruption circuit
PI7: To serial CH1

Port I

Port I function
select

From serial CH1

Port I data

Port I direction

Data

bus

RD (Port I)

Port I data

Port I direction

RD (Port I)

Circuit format

MPX

MPX

A

To serial CH1

IP

Schmitt input

Note)
PI5 is schmitt input
PI6 is inverter input

When resetPin

Hi-Z

Hi-Z

IP

PJ0

to

PJ7

8 pins

CS0

SI0

2 pins

SO0

Port J

Port J data

Port J direction

Data bus

Standby release

Data bus

SO0 from SIO

RD
(Port J)

RD

Edge detection

Schmitt input

IP

To SIO

IP

Hi-Z

Hi-Z

Hi-Z

1 pin

SO0 output enable

– 12 –

CXP87240A/87248A

SCK0

1 pin

EXTAL
XTAL

2 pins

TEX
TX

2 pins

TEX

TX

Internal serial clock
from SIO

SCK0 output enable

EXTAL

XTAL

Circuit format

External serial clock to SIO

IP

IP

Schmitt input

32kHz
timer counter

IP

• Shows the circuit
composition during
oscillation.

• Feedback resistor is
removed during stop.

• Shows the circuit
composition during
oscillation.

• Feedback resistor is
removed during 32kHz
oscillation circuit stop
by software.
At this time TEX pin
outputs "L" level and TX
pin outputs "H" level.

When resetPin

Hi-Z

Oscillation

Oscillation

RST

1 pin

MP

1 pin

Mask option

Pull-up resistor

Schmitt input

OP

IP

IP

CPU mode

L level

Hi-Z

– 13 –

CXP87240A/87248A

Absolute Maximum Ratings (Vss=0V)

Item Symbol Rating Unit Remarks

–0.3 to +7.0

AVss to +7.0

–0.3 to +0.3
–0.3 to +7.0
–0.3 to +7.0

–0.3 to +15.0

–5

–50

15

∗1

∗2
∗2

Supply voltage

Input voltage
Output voltage
Medium withstand output voltage
High level output current
High level total output current

VDD
AVDD
AVSS
VIN
VOUT
VOUTP
IOH
∑IOH

IOL

Low level output current

20

130

–20 to +75

–55 to +150

Low level total output current
Operating temperature
Storage temperature

IOLC
∑IOL
Topr
Tstg

600

Allowable power dissipation

∗1

AVDD and VDD should be set to a same voltage.

∗2

VIN and VOUT should not exceed VDD + 0.3V.

∗3

The high current operation transistors are the N-CH transistors of the PD and PH ports.

PD

380

V
V
V
V
V

V
mA
mA

mA
mA

mA

°C
°C

mW

PH pin

Total of output pins
Other than high current output

pins: per pin
High current port pin∗3: per pin
Total of output pins

QFP package type
LQFP package type

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.

– 14 –

CXP87240A/87248A

Recommended Operating Conditions (Vss = 0V)

Item Symbol Min. Max. Unit Remarks

Supply voltage

Analog power supply

High level
input voltage

Low level
input voltage

VDD

AVDD
VIH

VIHS

VIHTS

VIHEX

VIL
VILS

VILTS

VILEX

3.0

2.7

2.7

2.5

3.0

0.7VDD

0.8VDD

2.2
VDD – 0.4
VDD – 0.2

0
0

0
–0.3
–0.3

5.5

5.5

5.5

5.5

5.5
VDD
VDD

5.5

5.5

VDD + 0.3
VDD + 0.2

0.3VDD

0.2VDD

0.2VDD

0.8

0.4

0.2

Guaranteed range during high speed mode
(1/2 dividing clock) operation

Guaranteed range during low speed mode.
(1/16 dividing clock) operation

V

Guaranteed operation range by TEX clock
Guaranteed data hold operation range

during STOP

∗1

V

∗2

V
V

CMOS schmitt input∗3and PE0/INT0 pin

V

CMOS schmitt input

V

TTL schmitt input

V

EXTAL pin

V

EXTAL pin
∗2, ∗8

V

∗2, ∗9

V
V

CMOS schmitt input∗3and PE0/INT0 pin

V

TTL schmitt input

V

EXTAL pin

V

EXTAL pin

∗5, ∗8
∗5, ∗9

∗5, ∗8
∗5, ∗9

∗7

∗4

TEX pin
TEX pin

∗4

TEX pin
TEX pin

∗6, ∗8
∗6, ∗9

∗6, ∗8
∗6, ∗9

Operating temperature

∗1

AVDD and VDD should be set to a same voltage.

∗2

Normal input port (each pin of PC, PD, PF0 to PF3, PG, PI and PJ), MP pin.

∗3

Each pin of SCK0, RST, PE1/EC/INT2, PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1.

∗4

Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option)

∗5

It specifies only when the external clock is input.

∗6

It specifies only when the external event count clock is input.

∗7

Each pin of CS0, SI0, and PG (For PG4 and PG5, when CMOS schmitt input is selected with mask option.)

∗8

When the range of supply voltage (VDD) is within 4.5 to 5.5V.

∗9

When the range of supply voltage (VDD) is within 3.0 to 3.6V.

Topr

–20

+75

°C

– 15 –

Electrical Characteristics
DC Characteristics

Supply Voltage (VDD) 4.5 to 5.5V

CXP87240A/87248A

(Ta = –20 to +75°C, Vss = 0V)

Item Symbol Pins Conditions Min.

High level
output voltage

Low level
output voltage

VOH

VOL

IIHE

PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (VOL only)
PI1 to PI7
PJ, SO0, SCK0

PD, PH

VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V

EXTAL

Input current

IILE
IIHT

VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIH = 5.5V

TEX

IILT
IILR

RST

∗1

VDD = 5.5V,
VIL = 0.4V

PA to PG,

I/O leakage
current

IIZ

PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST

VDD=5.5V,
VI=0, 5.5V

∗1

Open drain
output leakage
current (N-CH

ILOH

PH

VDD = 5.5V
VOH = 12V

Tr OFF in state)

4.0

3.5

0.5

–0.5

0.1
–0.1
–1.5

Typ.

Max. Unit

V
V

0.4

0.6

1.5
40

–40

10

–10

–400

±10

50

V
V

V
µA
µA
µA
µA
µA

µA

µA

IDD1

VDD = 5V ± 0.5V

∗3

28

45

SLEEP mode

16MHz crystal oscillation (C1 = C2 = 15pF)

IDDS1

1.7

8

VDD = 5V ± 0.5V

32kHz crystal oscillation (C1 = C2 = 47pF)

Supply
current

∗2

IDD2

VDD

VDD = 3V ± 0.3V

40

100

SLEEP mode

IDDS2

10

30

VDD = 3V ± 0.3V

STOP mode

IDDS3

(EXTAL and TEX pins oscillation stop)

10

VDD = 5V ± 0.5V

Other than VDD,
Vss, AV

Input capacity

∗1

RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current

CIN

DD

AVss

Clock 1MHz

, and

0V other than the measured pins

10

20

when non-resistor is selected.

∗2

When entire output pins are open.

∗3

When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).

mA

mA

µA

µA

µA

pF

– 16 –

CXP87240A/87248A

Supply Voltage (VDD) 3.0 to 3.6V (Ta = –20 to +75°C, Vss = 0V)

Item Symbol Pins Conditions Min.

High level
output voltage

Low level
output voltage

VOH

VOL

IIHE

PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (VOL only)
PI1 to PI7
PJ, SO0, SCK0

PD, PH

VDD = 3.0V, IOH = –0.15mA
VDD = 3.0V, IOH = –0.5mA
VDD = 3.0V, IOL = 1.2mA
VDD = 3.0V, IOL = 1.6mA
VDD = 3.0V, IOL = 5mA
VDD = 3.6V, VIH = 3.6V

EXTAL

VDD = 3.6V, VIL = 0.3V
VDD = 3.6V, VIH = 3.6V

Input current

IILE
IIHT

TEX

IILT
IILR

RST

∗1

VDD = 3.6V,
VIL = 0.3V

PA to PG,

I/O leakage
current

Open drain
output leakage
current

IIZ

ILOH

PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST

PH

VDD = 3.6V,
VI = 0, 3.6V

∗1

VDD = 3.6V,
VOH = 12V

2.7

2.3

0.3

–0.3

0.1
–0.1
–0.9

Typ.

Max. Unit

V
V

0.3

0.5

1.0
20

–20

10

–10

–200

±10

50

V
V

V
µA
µA
µA
µA
µA

µA

µA

IDD1

VDD = 3.3V ± 0.3V

∗3

13

25

SLEEP mode

12MHz crystal oscillation (C1 = C2 = 15pF)

Supply
current

∗2

IDDS1

VDD

VDD = 3.3V ± 0.3V

0.8

2.5

STOP mode

IDDS3

(EXTAL and TEX pins oscillation stop)

10

VDD = 3.3V ± 0.3V

Input
capacity

∗1

RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current

CIN

Other than VDD,
Vss, AV

DD, and AVss

Clock 1MHz
0V other than the measured pins

10

20

when non-resistor is selected.

∗2

When entire output pins are open.

∗3

When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).

mA

mA

µA

pF

– 17 –

CXP87240A/87248A

A

A

A

AC Characteristics
(1) Clock timing (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)

Item Symbol Pins Conditions Unit

System clock frequency

System clock input
pulse width

System clock input rise
and fall times

Event count clock input
pulse width

Event count clock input rise
and fall times

System clock frequency
Event count clock input

pulse width
Event count clock input rise

and fall times

∗

tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2

bits (CPU clock selection).

fC

tXL,
tXH

tCR,
tCF

tEH,
tEL

tER,
tEF

fC

tTL,
tTH

tTR,
tTF

XTAL
EXTAL

XTAL
EXTAL

XTAL
EXTAL

EC

EC
TEX

TX
TEX

TEX

Fig. 1,
Fig. 2

Fig. 1,
Fig. 2 (External clock drive)

Fig. 1, Fig. 2
(external clock drive)

Fig. 3

Fig. 3
Fig. 2 VDD = 2.7 to 5.5V

(32kHz clock spplied condition)
Fig. 3

Fig. 3

VDD = 4.5 to 5.5V

VDD = 4.5 to 5.5V

Min.

1
1

28

37.5

tsys× 4

32.768

10

Max.

16

MHz

12

200

∗

20

20

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

ns

ns

ns

ms

kHz

µs

ms

Fig. 1. Clock timing

EXTAL

Fig. 2. Clock applied condition

Crystal oscillation
Ceramic oscillation

EXTAL

AA

C

1 C2

Fig. 3. Event count clock timing

TEX
EC

XTAL

1/fc

XH tXLtCF tCR

t

32kHz clock applied condition

External clock

EXTAL

AA

74HC04

XTAL

crystal oscillation

TEX

AA

C

1

TX

0.8VDD

0.2VDD

DD – 0.4V

V

0.4V

C2

t

EH tELtEF tER

tTH tTLtTF tTR

– 18 –

CXP87240A/87248A

(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item

CS ↓→SCK
delay time

CS ↑→SCK
floating delay time

CS ↓→SO
delay time

CS ↓→SO
floating delay time

CS
high level width

SCK
cycle time

SCK
high and low level widths

SI input setup time
(against SCK ↑)

SI input hold time
(against SCK ↑)

SCK ↓→SO delay time

Symbol Pins Min.

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK0

SCK0

SO0

SO0

CS0

SCK0

SCK0

SI0

SI0

SO0

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode

Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode

tsys+200

2tsys + 200

8000/fc

tsys + 100

8000/fc – 100
–tsys + 100

200

2tsys + 100

100

Max. UnitConditions

tsys + 200

tsys + 200

tsys + 200

tsys + 200

2tsys + 200

100

ns

ns

ns

ns

ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns

Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.

– 19 –

CXP87240A/87248A

(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)

Item

CS ↓→SCK
delay time

CS ↑→SCK
floating delay time

CS ↓→SO
delay time

CS ↓→SO
floating delay time

CS
high level width

SCK
cycle time

SCK
high and low level widths

SI input setup time
(against SCK ↑)

SI input hold time
(against SCK ↑)

SCK ↓→SO delay time

Symbol Pins Min.

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK0

SCK0

SO0

SO0

CS0

SCK0

SCK0

SI0

SI0

SO0

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode
Input mode

Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode

tsys + 200

2tsys + 200

8000/fc

tsys + 100

8000/fc – 150
–tsys + 100

200

2tsys + 100

100

Max. UnitConditions

tsys + 250

tsys + 200

tsys + 250

tsys + 200

2tsys + 250

125

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF.

– 20 –

Fig. 4. Serial transfer timing (CH0)

CXP87240A/87248A

tWHCS

CS0

SCK0

DD

0.2V

tKCY

tDCSK tDCSKF

tKL tKH

0.8VDD

0.2VDD

tKSI

SIK

t

0.8VDD

0.8VDD

SI0

SO0

0.8VDD

Input data

0.2VDD

DCSO tKSO tDCSOF

t

Output data

0.8V

0.2VDD

DD

– 21 –

CXP87240A/87248A

Serial transfer (CH1) (SIO mode) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pins Min. Max. UnitConditions

SCK1 cycle time

SCK1 high and low
level widths

SI1 input setup time
(against SCK1 ↑)

SI1 input hold time
(against SCK1 ↑)

SCK1 ↓→SO1 delay time

Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK1

SCK1

SI1

SI1

SO1

Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode

2tsys + 200

16000/fc

tsys+100

8000/fc – 50

100
200

tsys + 200

100

tsys + 200

100

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.

Serial transfer (CH1) (SIO mode) (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)

Item Symbol Pins Min. Max. UnitConditions

SCK1 cycle time

SCK1 high and low
level widths

SI1 input setup time
(against SCK1 ↑)

SI1 input hold time
(against SCK1 ↑)

SCK1 ↓→SO1 delay time

Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK1

SCK1

SI1

SI1

SO1

Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode

2tsys + 200

16000/fc

tsys + 100

8000/fc – 150

100
200

tsys + 200

100

tsys + 250

125

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF.

– 22 –

Fig. 5. Serial transfer CH1 timing (SIO mode)

tKL tKH

t

CXP87240A/87248A

KCY

SCK1

SI1

SO1

tKSO

tSIK tKSI

Input data

0.8VDD

0.2VDD

Output data

0.8VDD

DD

0.2V

0.8VDD

0.2VDD

– 23 –

CXP87240A/87248A

Serial transfer (CH1) (Special mode) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pins Conditions Min. Typ. Max. Unit
SO1 cycle time
SI1 data setup time

SI1 data hold time

tLCY
tLSU

tLHD

SO1
SI1

SI1
SI1

Note 1)

104 µs

2
2

µs
µs

Note 1) tLCY specifies only serial mode register (CH1) (SIOM1: Address 01FAH) lower 2 bits (SO1 clock

selection) has been set at 104µs.

Note 2) The load of SO1 pin is 50pF + 1TTL.

Serial transfer (CH1) (Special mode) (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)

Item Symbol Pins Conditions Min. Typ. Max. Unit
SO1 cycle time
SI1 data setup time

SI1 data hold time

tLCY
tLSU

tLHD

SO1
SI1

SI1
SI1

Note 1)

104 µs

2
2

µs
µs

Note 1) tLCY specifies only serial mode register (CH1) (SIOM1: Address 01FAH) lower 2 bits (SO1 clock

selection) has been set at 104µs.

Note 2) The load of SO1 pin is 50pF.

Fig. 6. Serial transfer CH1 timing (Special mode)

tLCY

SO1

SI1

Start bit Output data bit

tLCY/2

LCY

t

tLSU tLHD

input

data bit

0.5VDD

0.8VDD

0.2VDD

– 24 –

CXP87240A/87248A

(3) General purpose prescaler (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)

Item Symbol Pins Conditions Min. Typ. Max. Unit
External clock input frequency
External clock input pulse width
External clock input

rise and fall times

fPCK

tWH, tWL
tR,

tF

Fig. 7. General purpose prescaler timing

tWH

SYNC1

0.5VDD

0.2VDD

1/fPCK

SYNC1
SYNC1

SYNC1

tF

tWL

0.8VDD

tR

33

12

200

MHz

ns
ns

– 25 –

CXP87240A/87248A

(4) HSYNC counter (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)

Item Symbol Pins Conditions Min. Typ. Max. unit
External clock input frequency
External clock input pulse width

External clock input rise/fall time

HCOUT output delay time
(against SYNC1 ↑)

HCOUT output rise/fall time

fHCK

tWH, tWL
tR

tF
tHLH
tHHL
tTLH
tTHL

SYNC1
SYNC1

SYNC1

HCOUT

HCOUT

External clock input
SYNC1 tR = tF = 6ns

External clock input
SYNC1 tR = tF = 6ns

33

tsys + 130

tsys + 90

100

30

12

200

tsys + 220
tsys + 150

280

70

MHz

ns
ns
ns

ns
ns
ns

Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)

Note 2) The load of HCOUT pin is 50pF.

Fig. 8. HSYNC counter timing

1/fHCK

SYNC1

tWH

0.5VDD

0.2VDD

tF

0.8VDD

tWL

tR

HCOUT

tHLH

0.5VDD

0.2VDD

tTLH

tHHL

0.8VDD

tTHL

– 26 –

CXP87240A/87248A

(5) A/D converter characteristics

Item Symbol Pins Conditions Min. Typ. Max. Unit

Resolution
Linearity error
Absolute error
Conversion time
Sampling time
Reference input voltage
Analog input voltage

tCONV
tSAMP

VREF
VIAN
IREF

AVREF current

IREFS

(Ta = –20 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V)

Item Symbol Pins Conditions Min. Typ. Max. Unit

Resolution
Linearity error
Absolute error
Conversion time
Sampling time

tCONV
tSAMP

(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V)

8

Ta = 25°C

±1±2LSB

VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V

∗

∗

AVDD

0

0.6

1.0

10 µA

AV

REF

AN0 to AN11

AVREF

VDD = AVDD = 4.5 to 5.5V

Operating mode
SLEEP mode

STOP mode

160/fADC

12/fADC

AVDD – 0.5

32kHz operating mode

8

Ta = 25°C
VDD = AVDD = AVREF =

5.0V
160/fADC

12/fADC

∗

∗

±1±2LSB

Bits

LSB

µs
µs

V
V

mA

Bits

LSB

µs

µs
Reference input voltage
Analog input voltage

VREF
VIAN

AVREF

AN0 to AN11

IREF

AVREF current

AVREF

IREFS

Fig. 9. Definitions of A/D converter terms

FFH
FEH

Digital conversion value

01H
00H

Linearity error

Analog input

VDD = AVDD = 3.0 to 3.6V

AVDD – 0.3

0

Operating mode
SLEEP mode

STOP mode
32kHz operating mode

∗

The value of fADC is as follows by selecting ADC
operation clock (MSC: Address 01FFH bit 0).
When PS2 is selected, fADC = fc/2
When PS1 is selected, fADC = fc

V

FTVZT

0.4

AVDD

0.7

10 µA

V
V

mA

– 27 –

(6) Interruption, reset input (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)

Item Symbol Pins Conditions Min. Max. Unit

INT0

External interruption
high and low level widths

tIH
tIL

INT1
INT2
NMI
PJ0 to PJ7

1

µs

CXP87240A/87248A

Reset input low level width

Fig. 10. Interruption input timing

INT0
INT1
INT2
NMI
PJ0 to PJ7
(During standby release input)
(Falling edge)

Fig. 11. Reset input timing

RST

tRSL

RST

0.2VDD

32/fc

tIH tIL

0.8VDD

tRSL

µs

0.2VDD

(7) Others

Item

CFG input
high and low level widths

DFG input
high and low level widths

DPG minimum pulse width
DPG minimum

removal time
PBCTL input

high and low level widths
EXI input

high and low level widths

Note) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

Symbol Pins Min.

tCFH
tCFL

tDFH
tDFL

tDPW
trem
tCTH

tCTL
tEIH

tEIL

CFG

DFG
DPG
DPG

PBCTL
EXI0

EXI1

Conditions

tsys = 2000/fc

tsys = 2000/fc

(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)

Max. Unit

tFRC × 24 + 200

tFRC × 16 + 200

tFRC × 8 + 200

tFRC × 16 + 200

tFRC × 8+200 + tsys

tFRC × 8+200 + tsys

ns

ns

ns
ns

ns

ns

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
tFRC = 1000/fc [ns]

– 28 –

Fig. 12. Other timings

CXP87240A/87248A

tCFH tCFL

CFG

DFG

DPG

0.8VDD

0.8VDD

tDFH tDFL

tDPW

trem

0.2VDD

0.2VDD

trem

0.8VDD

PBCTL

EXI0
EXI1

tCTH tCTL

0.8VDD

0.2VDD

tEIH tEIL

0.8VDD

0.2VDD

– 29 –

Supplement

A

A

Fig. 13. Recommended oscillation circuit

CXP87240A/87248A

Manufacturer

RIVER
ELETEC
CO., LTD.

KINSEKI LTD.

(i)

EXTAL

AAA

1 C2

C

Model

HC-49/U03

HC-49/U (-S)

XTAL

Rd

fc (MHz)

8.00

10.00

12.00

16.00

8.00

10.00

12.00

(ii)

C1

C1 (pF) C2 (pF)

10

5

16 (12)
16 (12)

12

10

5

16 (12)
16 (12)

12

TEX

AAA

TX

Rd (Ω)

0

0

Rd

C2

Circuit

example

(i)

(i)

16.00

P3

Mask option table

Item

Reset pin pull-up resistor
Input circuit format

∗

In PG4/SYNC0 pin and PG5/SYNC1 pin, the input circuit format can be selected to every pin.
However, TTL shmitt can not be selected when the supply voltage (VDD) ranges 3.0V to 5.5V.

∗

Non-existent

C-MOS schmitt

32.768kHz

Content

12
30

Existent

TTL schmitt

12

18

470K

(ii)

– 30 –

Characteristics Curve

CXP87240A/87248A

(fc = 16MHz, Ta = 25°C, Typical)

10.0

5.0

1.0

0.5

– Supply current [mA]

DD

I

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

IDD vs. VDD

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

SLEEP mode

32kHz mode
(instruction)

32kHz
SLEEP mode

(fc = 12MHz, Ta = 25°C, Typical)

10.0

5.0

1.0

0.5

– Supply current [mA]

DD

I

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

IDD vs. VDD

1/2 dividing mode
1/4 dividing mode

1/16 dividing mode

SLEEP mode

3456

VDD – Supply voltage [V]

(VDD = 5.0V, Ta = 25°C, Typical)

30

20

– Supply current [mA]

DD

I

10

0

1

fc – System clock [MHz]

IDD vs. fc

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

SLEEP mode

5101516

3456

VDD – Supply voltage [V]

(VDD = 3.3V, Ta = 25°C, Typical)

30

20

– Supply current [mA]

DD

I

10

0

1

fc – System clock [MHz]

IDD vs. fc

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

SLEEP mode

5101516

– 31 –

Package Outline Unit: mm

100PIN QFP (PLASTIC)

23.9 ± 0.4
+ 0.4

20.0 – 0.1

+ 0.4

17.9 ± 0.4

14.0 – 0.01

+ 0.1

0.15 – 0.05

15.8 ± 0.4

CXP87240A/87248A

A

SONY CODE
EIAJ CODE

JEDEC CODE

76

0.65

75

0° to 15°

±0.12

0.15

(16.3)

DETAIL A

QFP-100P-L01
∗QFP100-P-1420-A

0.8 ± 0.2

100PIN LQFP (PLASTIC)

16.0 ± 0.2

∗ 14.0 ± 0.1

M

PACKAGE STRUCTURE

PACKAGE MATERIAL
LEAD TREATMENT

LEAD MATERIAL
PACKAGE WEIGHT

51

50

+ 0.35

2.75 – 0.15

EPOXY RESIN
SOLDER PLATING

COPPER / 42 ALLOY

1.4g

100

0.5 ± 0.08

SONY CODE

EIAJ CODE

JEDEC CODE

(15.0)

A

26

1

+ 0.08

0.18 – 0.03

(0.22)

25

+ 0.2

1.5 – 0.1

+ 0.05

0.127 – 0.02

0.5 ± 0.2

0.1

0.1 ± 0.1

NOTE: Dimension “∗” does not include mold protrusion.

0° to 10°

0.5 ± 0.2

DETAIL A

LQFP-100P-L01

∗QFP100-P-1414-A

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY/PHENOL RESIN
SOLDER PLATING
42 ALLOY

– 32 –