Page 1
Description
The CXP87132/87140 is a CMOS 8-bit microcomputer
which consists of A/D converter, serial interface (2ch
independently), timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuit (PPG 2ch independently, RTG 2ch independently),
PWM generator, general purpose prescaler, PWM for
tuner, VCR vertical sync separation circuit and the
measuring circuit which measure signals of capstan
FG and drum FG/PG and other servo systems, as
well as basic configurations like 8-bit CPU, ROM,
RAM and I/O port. They are integrated into a single
chip.
Also the CXP87132/87140 provides power on reset
function, sleep/stop function which enables to lower
power consumption.
Features
• A wide instruction set (213 instructions) which covers various types of data
— 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction
• Minimum instruction cycle During operation 333ns/12MHz (3.0 to 5.5V)
During operation 250ns/16MHz (4.5 to 5.5V)
• Incorporated ROM capacity 32K bytes (CXP87132)
40K bytes (CXP87140)
• Incorporated RAM capacity 1312 bytes
• Peripheral functions
— A/D converter 8-bit, 12-channel, successive approximation system
(Conversion time: 20µs/16MHz)
— Serial I/O Incorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel
Incorporated 8-bit and 8-stage FIFO
(1 to 8 bytes auto transfer) 1-channel
— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer
— High precision timing pattern generator PPG 19 pins 32-stage programmable
PPG 10 pins 21-stage programmable
RTG 5 pins 2-channel
— PWM/DA gate output PWM 12-bit, 2-channel (Repetitive frequency 62.5kHz/16MHz)
DA gate pulse 12-bit, 4-channel
— Servo input control Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit Incorporated 26-bit and 8-stage FIFO
— PWM output 14-bit, 1-channel
— General purpose prescaler 10-bit (System clock asynchronous)
— Pulse cycle measuring circuit
• Interruption 18 factors, 14 vectors, multi-interruption possible
• Standby mode Sleep/stop
• Package 100-pin plastic QFP/LQFP
• Piggyback/evaluation chip CXP87100 100-pin ceramic QFP/LQFP
CMOS 8-bit Single Chip Microcomputer
– 1 –
E93631A7Z-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXP87132/87140
100 pin QFP (PIastic) 100 pin LQFP (PIastic)
Structure
Silicon gate CMOS IC
Page 2
– 2 –
CXP87132/87140
A/D CONVERTER
SERIAL
INTERFACE UNIT
(CH0)
BUFFER
RAM
INTERRUPT CONTROLLER
SPC700
CPU CORE
ROM
32K/40K BYTES
PRESCALER/
TIME BASE TIMER
RAM
1312 BYTES
CLOCK
GENERATOR/
SYSTEM CONTROL
12
AN0 to AN3
SI0
CS0
PI7/SI1
SCK0
AV
DD
PE1/INT2
EXTAL
XTAL
V
DD
Vss
PORT C
8
PC0 to PC7
PORT D
8
PD0 to PD7
PORT I
PI1 to PI7
RST
PORT J
8
PJ0 to PJ7
PORT G
8
PG0 to PG7
PORT H
8
PH0 to PH7
PORT A
8
PA0 to PA7
PORT E
2
6
PE0 to PE1
PE2 to PE7
REALTIME
PULSE
GENERATOR
2
PF0/AN4
to
PF7/AN11
2
PE0/INT0
FRC
CAPTURE
UNIT
FIFO
RAM
CH0
CH1
19
5
2
PORT B
8
PB0 to PB7
PORT F
PF0 to PF3
4
4
PF4 to PF7
AV
REF
AVss
MP
PI4/INT1
PORT K
1
PK0
PROGRAMMABLE
PATTERN
GENERATOR (CH1)
RAM
10
2
3
2
4
4
2
2
SERIAL
INTERFACE UNIT
(CH1)
FIFO
8BIT TIMER/COUNTER 0
8BIT TIMER 1
V SYNC SEPARATOR
CAPSTAN
DRUM
CTL
SERVO INPUT
CONTROL
PROGRAMMABLE PRESCALER
14BIT PWM GENERATOR
12BIT PWM GENERATOR CH0
12BIT PWM GENERATOR CH1
PULSE MEASURE UNIT
SO0
PI6/SO1
PI5/SCK1
PE1/EC
PI3/TO
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PI0/PCK/OSCI
PK0/OSCO
PI1/PO
PE0/XOUT
PE2/PWM0
PE4/DAA0
PE6/DAB0
PE3/PWM1
PE5/DAA1
PE7/DAB1
PG4/PMI
PG7/PMSK
PI2/PWM
1
7
PI0
PPO100
to
PPO107
PPO112
to
PPO113
RTO3
to
RTO7
PPO000 to PPO018
19
10
PROGRAMMABLE
PATTERN
GENERATOR (CH0)
Block Diagram
Page 3
– 3 –
CXP87132/87140
PI6/SO1
PI7/SI1
PE0/INT0/XOUT
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PF2/DPG
PG3/PBCTL
PG4/SYNC0/PMI
PG5/SYNC1
PG6/EXI0
PG7/EXI1/PMSK
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7
AV
DD
AVREF
AVSS
PF4/AN8
PB5/PPO013/PPO113
PB4/PPO012/PPO112
PB3/PPO011
PB2/PPO010
PB1/PPO009
PB0/PPO008
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3
PC2/PPO018
PC1/PPO017
PC0/PPO016
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB6/PPO014
PB7/PPO015
PA0/PPO000/PPO100
PA1/PPO001/PPO101
PA2/PPO002/PPO102
PA3/PPO003/PPO103
PA4/PPO004/PPO104
PA5/PPO005/PPO105
PA6/PPO006/PPO106
PA7/PPO007/PPO107
NC
V
DD
V
SS
PK0/OSCO
PI0/PCK/OSCI
PI1/PO
PI2/PWM
PI3/TO
PI4/INT1
PI5/SCK1
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
MP
RST
V
SS
XTAL
EXTAL
CS0
SI0
SO0
SCK0
PF7/AN11
PF6/AN10
PF5/AN9
Mask
option
81
82
83
84
88
87
86
85
89
90
100
99
98
97
96
95
94
91
92
93
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
Pin Configuration 1 (Top View) 100 pin QFP Package
Note) 1. NC (Pin 90) is always connected to VDD.
2. Vss (Pins 41 and 88) are both connected to GND.
– 4 –
Page 4
CXP87132/87140
Pin Configuration 2 (Top View) 100 pin LQFP Package
PI6/SO1
PI7/SI1
PE0/INT0/XOUT
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PF2/DPG
PG3/PBCTL
PG4/SYNC0/PMI
PG5/SYNC1
PG6/EXI0
PG7/EXI1/PMSK
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PB3/PPO011
PB2/PPO010
PB1/PPO009
PB0/PPO008
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3
PC2/PPO018
PC1/PPO017
PC0/PPO016
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
PD7
PD6
PD5
PB6/PPO014
PB7/PPO015
PA0/PPO000/PPO100
PA1/PPO001/PPO101
PA2/PPO002/PPO102
PA3/PPO003/PPO103
PA4/PPO004/PPO104
PA5/PPO005/PPO005
PA6/PPO006/PPO106
PA7/PPO007/PPO107
NC
V
DD
V
SS
PK0/OSCO
PI0/PCL/OSCI
PI1/PO
PI2/PWM
PI3/TO
PI4/INT1
PI5/SCK1
PH2
PH1
PH0
MP
RST
V
SS
XTAL
EXTAL
CS0
SI0
SO0
SCK0
PF7/AN11
PF6/AN10
PF5/AN9
Mask
option
PH7
PH6
PH5
PH4
PH3
PD4
PD3
PD2
PD1
PD0
PF4/AN8
AV
SS
PF3/AN7
AV
DD
AVREF
PB4/PPO012/PPO112
PB5/PPO013/PPO113
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
73
74
75
76
77
78
79
80
81
82
83
84
88
87
86
85
89
90
100
99
98
97
96
95
94
91
92
93
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
26 27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
Note) 1. NC (Pin 88) is always connected to VDD.
2. Vss (Pins 39 and 86) are both connected to GND.
Page 5
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CXP87132/87140
Output/
Real time
output
Output/
Real time
output
I/O/
Real time
output
I/O/
Real time
output
I/O
Input/Input/Output
Input/Input/Input
Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Input
Input/Input
Output/Input
I/O
Ouput
Input
Input
(Port A)
8-bit output port. Data is gated
with PPO0 and PPO1 contents
by OR-gate and they are output.
(8 pins)
(Port B)
8-bit output port. Data is gated
with PPO0 and PPO1 contents
by OR-gate and they are output.
(8 pins)
(Port C)
8-bit I/O port. Enables to
specify I/O by a bit unit.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)
(Port D)
8-bit I/O port. Enable to specify I/O by 4-bit unit.
Enables to drive 12mA sink current. (During 5V ± 0.5V operation)
(8 pins)
(Port E)
8-bit port. Lower 2 bits are
input port and upper 6 bits
are output port.
(8 pins)
Analog input pins to A/D converter. (12 pins)
(Port F)
Lower 4 bits are input port and upper 4 bits are output port.
Lower 4 bits also serve as standby release input pin.
(8 pins)
Serial clock (CH0) I/O pin.
Serial data (CH0) output pin.
Serial data (CH0) input pin.
Serial chip select (CH0) input pin.
External event
input pin for
timer/counter.
Input pin to request
external interruption.
Active when falling edge.
Input pin to request
external interruption.
Active when falling edge.
1/2 dividing clock
output of XTAL
or OSCO.
PWM output pins.
(2 pins)
DA gate pulse output pins.
(4 pins)
Programmable pattern generator
(PPG0, PPG1) output.
Functions as high precision real time
pulse output port.
(
PPG0 19 pins
)
PPG1 10 pins
Real time pulse generator (RTG) output.
Functions as high precision real time
pulse output port. (5 pins)
Symbol I/O Description
PA0/PPO000
/PPO100
to
PA7/PPO007
/PPO107
PB0/PPO008
to
PB7/PPO015
PC0/PPO016
to
PC2/PPO018
PC3/RTO3
to
PC7/RTO7
PD0 to PD7
PE0/INT0
/XOUT
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
AN0 to AN3
PF0/AN4
to
PF3/AN7
PF4/AN8
to
PF7/AN11
SCK0
SO0
SI0
CS0
Pin Description
Page 6
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CXP87132/87140
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
/PMI
PG5/SYNC1
PG6/EXI0
PG7/EXI1/
PMSK
PH0 to PH7
PI0/PCK
/OSCI
PI1/PO
PI2/PWM
PI3/TO
PI4/INT1
PI5/SCK1
PI6/SO1
PI7/SI1
PJ0 to PJ7
Input/Input
Input/Input
Input/Input
Input/Input
Input/Input/Input
Input/Input
Input/Input
Input/Input/Input
Output
Input/Input/Input
I/O/Output
I/O/Output
I/O/Output
I/O/Input
I/O/I/O
I/O/Output
I/O/Input
I/O
Capstan FG input pin.
Drum FG input pin.
Drum PG input pin.
Playback CTL pulse input pin.
Composite sync
signal input pin.
Measuring pulse signal input pin
of pulse cycle measuring unit.
Measuring enable signal input pin
of pulse cycle measuring unit.
(Port G)
8-bit input port.
(8 pins)
(Port H)
8-bit output port; large current, N-ch open drain output.
(8 pins)
External clock input
pin of general
purpose prescaler.
General purpose prescaler output pin.
14-bit PWM output pin.
Timer/counter output pin. (duty = 50%)
Input pin to request external interruption.
Active when falling edge.
Serial clock (CH1) I/O pin.
Serial data (CH1) output pin.
Serial data (CH1) input pin.
(Port I)
Lower 1 bit is
input port
(mask option)
and upper 7 bits
are I/O port.
I/O port can be
specified by a bit
unit.
(8 pins)
Symbol I/O Description
External input pin
to FRC capture
unit.
Connecting pin of crystal for
general purpose prescaler
oscillation circuit. (Mask option)
(Port J)
8-bit I/O port. Function as standby release input can be specified by a
bit unit. I/O can be specified by a bit unit.
Page 7
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CXP87132/87140
PK0/OSCO
RST
MP
AVDD
AVREF
AVSS
VDD
VSS
Input/Output
I/O
Input
Input
Connecting pin of crystal for system clock oscillation. When supplying
the external clock, input the external clock to EXTAL pin and input
opposite phase clock to XTAL pin.
Input port. (Mask option)
System reset pin of active "L" level. RST pin is I/O pin, which outputs
"L" level by incorporated power on reset function when power on.
(Mask option)
Microprocessor mode input pin. Always connect to GND.
Positive power supply pin of A/D converter.
Reference voltage input pin of A/D converter.
GND pin of A/D converter.
Positive power supply pin.
GND pin. Connect both Vss pins to GND.
Connecting pin of crystal for
general purpose prescaler
oscillation circuit. (Mask opiton)
XTAL
EXTAL
Output
Input
Symbol I/O Description
Page 8
– 8 –
CXP87132/87140
Pin When resetCircuit format
Port A
Port B
Port B
Port C
Port D
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PA0/PPO000
/PPO100
to
PA7/PPO007
/PPO107
PB4/PPO012
/PPO112
to
PB5/PPO013
/PPO113
10 pins
PB0/PPO008
to
PB3/PPO011
PB6/PPO014
to
PB7/PPO015
6 pins
PC0/PPO016
to
PC2/PPO018
PC3/RTO3
to
PC7/RTO7
8 pins
PD0
to
PD7
8 pins
PPO0 data
Data bus
Output becomes active from high
impedance by data writing to port register.
Port A or Port B
RD
Input/Output Circuit Formats for Pins
PPO0 data
PPO1 data
Port A or Port B
Data bus
Output becomes active from high
impedance by data writing to port register.
RD
Data bus
PPO, RTO data
Port C data
Port C direction
Data bus
RD (Port C)
Port D data
Port D direction
(Every bit)
(Every 4 bits)
PD0 to PD3
PD4 to PD7
Input
protection
circuit
IP
IP
Large
current
12mA
RD (Port D)
Page 9
– 9 –
CXP87132/87140
A
Port E
Port E
Port E
Port E
Hi-Z
Hi-Z
Hi-Z
High level
PE1/EC/INT2
1 pin
PE0/INT0
/XOUT
1 pin
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
4 pins
PE6/DAB0
PE7/DAB1
2 pins
Pin When resetCircuit format
Schmitt input
IP
Data bus
PS1
OSCO
Port E function
select register
RD (Port E)
DA gate output or
PWM output
Hi-Z control
Data bus
1/2
Port E data
Port E function
select register
MPX
RD (Port E)
MPX
Data bus
IP
To interruption
circuit
Data bus
DA gate output
Hi-Z control
Port E data
Port E function
select register
AA
RD (Port E)
RD (Port E)
MPX
Page 10
– 10 –
CXP87132/87140
Port F
Port F
Port G
Hi-Z
Hi-Z
Hi-Z
Hi-Z
AN0
to
AN3
4 pins
PF0/AN4
to
PF3/AN7
4 pins
PF4/AN8
to
PF7/AN11
4 pins
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0/PMI
PG5/SYNC1
PG6/EXI0
PG7/EXI1/PMSK
8 pins
Port H
Hi-Z
PH0
to
PH7
8 pins
IP
A/D converter
Input multiplexer
Pin When resetCircuit format
Input multiplexer
IP
RD (Port F)
A/D converter
Data bus
Port F data
Data bus
RD
(Port F)
Note) For PG4/SYNC0, PG5/SYNC1, CMOS schmitt input and TTL schmitt input
can be selected with the mask option.
Schmitt input
IP
Port/AD select
Input multiplexer
Pulse cycle measuring unit input
Servo input
Data bus
RD (Port G)
IP
A/D converter
Port H data
Data bus
RD (Port H)
Large current
12mA
Page 11
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CXP87132/87140
A
A
AAA
A
A
Port I
Port I
Port I
Port J
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PI1/PO
PI2/PWM
PI3/TO
3 pins
PI4/INT1
PI7/SI1
2 pins
PI5/SCK1
PI6/SO1
2 pins
PJ0
to
PJ7
8 pins
Pin When resetCircuit format
Port I
function select
PI1: From general purpose prescaler
PI2: From 14-bit PWM
PI3: From timer/counter
Port I data
Port I direction
Data bus
RD (Port I)
Port I data
Port I direction
Data bus
RD (Port I)
PI4: To interruption circuit
PI7: To serial CH1
A
MPX
A
Schmitt input
IP
IP
Data bus
Data bus
Port I
function select
From serial CH1
Port I data
Port I direction
RD (Port I)
Port J direction
Port J data
A
MPX
A
MPX
Note)
PI5 is schmitt input
PI6 is inverter input
To serial CH1
IP
IP
Standby release
RD
(Port J)
Edge detection
Page 12
– 12 –
CXP87132/87140
CS0
SI0
2 pins
Hi-Z
SO0
2 pins
RST
1 pin
Low level
MP
1 pin
Hi-Z
Port I
Port K
Oscillation
Hi-Z
PI0/PCK/OSCI
PK0/OSCO
2 pins
SCK0 output enable
Internal serial clock
from SIO
IP
Schmitt input
External serial clock to SIO
IP
EXTAL
XTAL
• Shows the circuit
composition during
oscillation.
• Feedback resistor is
removed during stop.
1 pin
Hi-Z
SCK0
1 pin
Hi-Z
EXTAL
XTAL
Oscillation
Pin When resetCircuit format
Schmitt input
IP
SO0 from SIO
SO0 output enable
To SI0
Mask option
OSCI
OSCO
OP
Pull-up resistor
Schmitt input
IP
IP
Fig. 1
From power on reset circuit
(mask option)
CPU mode
IP
PI0/PCK
or PK0
Note) Circuit format of Fig. 1 or Fig. 2 can be
selected with mask option.
IP
Fig. 2
RD Port I
Port K
Data bus
Page 13
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CXP87132/87140
∗1
AVDD and VDD should be set to the same voltage.
∗2
VIN and VOUT should not exceed VDD + 0.3V. (CS0, SI0, PG and PH excluded.)
∗3
The large current operation transistors are the N-CH transistors of the PD and PH ports.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
Power supply voltage
Input voltage
Output voltage
High level output current
High level total output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
VDD
AVDD
AVSS
VIN
VOUT
IOH
∑IOH
IOL
IOLC
∑IOL
Topr
Tstg
PD
Low level output current
–0.3 to +7.0
AVss to +7.0
∗1
–0.3 to +0.3
–0.3 to +7.0
∗2
–0.3 to +7.0
∗2
–5
–50
15
20
130
–20 to +75
–55 to +150
600
380
V
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
mW
Total of output pins
Other than large current output
pins
Large current output pin
∗3
Total of output pins
QFP
LQFP
Item Symbol Rating Unit Remarks
Absolute Maximum Ratings (Vss = 0V reference)
Page 14
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CXP87132/87140
Analog power supply
High level
input voltage
Low level
input voltage
Operating temperature
Power supply voltage
5.5
5.5
5.5
5.5
VDD
VDD
5.5
5.5
VDD + 0.3
0.3VDD
0.2VDD
0.2VDD
0.8
0.4
+75
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
Item Symbol Min. Max. Unit Remarks
3.0
2.7
2.5
3.0
0.7VDD
0.8VDD
2.2
VDD + 0.4
0
0
0
–0.3
–20
AVDD
VIH
VIHS
VIHTS
VIHEX
VIL
VILS
VILTS
VILEX
Topr
Guaranteed range during high speed mode
(1/2 dividing clock) operation
Guaranteed range during low speed mode
(1/16 dividing clock) operation
Guaranteed data hold operation range
during stop
∗1
∗2
CMOS schmitt input∗3and PE0/INT0 pins
CMOS schmitt input
∗4
TTL schmitt input
∗5, ∗8
EXTAL pin
∗6
∗2, ∗8
∗2, ∗7
CMOS schmitt input
∗3, ∗4
and PE0/INT0 pins
TTL schmitt input
∗5, ∗8
EXTAL pin
∗6
VDD
∗1
AVDD and VDD should be set to the same voltage.
∗2
Normal input port (each pin of PC, PD, PF0 to PF3, PI, PJ, and PK), MP pin.
∗3
Each pin of SCK0, RST, PE1/EC/INT2, PI1/PO, PI4/INT1, PI5/SCK1 and PI7/SI1.
∗4
Each pin of CS0, SI0, and PG (for PG4 and PG5, when CMOS schmitt input is selected.)
∗5
Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option)
∗6
It specifies only when the external clock is input.
∗7
In case of 3.0 to 3.6V supply voltage (VDD).
∗8
In case of 4.5 to 5.5V supply voltage (VDD).
Recommended Operating Conditions (Vss = 0V reference)
Page 15
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CXP87132/87140
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 0.4V
High level
output voltage
4.0
3.5
0.5
–0.5
–1.5
V
V
V
V
V
µA
µA
µA
µA
PD, PH
PA to PE,
PF4 to PF7,
PH (VOL only)
PI1 to PI7, PJ,
SO, SCK,
RST∗1(VOL only)
EXTAL
RST
∗2
Item Symbol Pin Condition Min.
Other than VDD,
Vss, AVDD, and
AVss pins
Clock 1MHz
0V for no measured pins
VDD
IDD1
IIZ
IDDS1
IDDS3
CIN
VOH
VOL
IIHE
IILE
IILR
Low level
output voltage
Input current
Typ.
0.4
0.6
1.5
40
–40
–400
±10
Max. Unit
DC Characteristics
Supply voltage (VDD) 4.5 to 5.5V (Ta = –20 to +75°C, Vss = 0V reference)
∗
1
RST pin specifies only when the power on reset circuit has been selected with mask option.
∗2
RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistance is selected.
∗3
When entire output pins are open.
∗4
When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).
VDD = 5V ± 10%
∗4
Sleep mode
VDD = 5V ± 10%
VDD = 5.5V
Supply
current
∗3
Input capacity
VDD = 5.5V,
VI = 0, 5.5V
Crystal oscillation
(C1 = C2 = 15pF) of 16MHz
Stop mode
I/O leakage
current
PA to PK,
MP,
AN0 to AN3,
CS, SI, SO,
SCK, RST
∗2
25
1
10
45
5
10
20
mA
mA
µA
pF
Electrical Characteristics
Page 16
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CXP87132/87140
VDD = 3.0V, IOH = –0.15mA
VDD = 3.0V, IOH = –0.5mA
VDD = 3.0V, IOL = 1.2mA
VDD = 3.0V, IOL = 1.6mA
VDD = 3.0V, IOL = 5.0mA
VDD = 3.6V, VIH = 3.6V
VDD = 3.6V, VIL = 0.3V
VDD = 3.6V, VIL = 0.3V
High level
output voltage
2.7
2.3
0.3
–0.3
–0.9
V
V
V
V
V
µA
µA
µA
µA
PD, PH
EXTAL
RST
∗2
Item Symbol Pin Condition Min.
Clock 1MHz
0V for no measured pins
VDD
IDD2
IIZ
IDDS2
IDDS3
CIN
VOH
VOL
IIHE
IILE
IILR
Low level
output voltage
Input current
Typ.
0.3
0.5
1.0
20
–20
–200
±10
Max. Unit
Supply voltage (VDD) 3.0 to 3.6V (Ta = –20 to +75°C, Vss = 0V reference)
∗1
RST pin specifies only when the power on reset circuit has been selected with mask option.
∗2
RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistance is selected.
∗3
When entire output pins are open.
∗4
When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).
VDD = 3.3V ± 0.3V
∗4
Sleep mode
VDD = 3.3V ± 0.3V
VDD = 5.5V
Supply
current
∗3
Input capacity
VDD = 5.5V,
VI = 0, 5.5V
Crystal oscillation
(C1 = C2 = 15pF) of 12MHz
Stop mode
I/O leakage
current
PA to PK,
MP,
AN0 to AN3,
CS, SI, SO,
SCK, RST
∗2
12
0.5
10
25
2.5
10
20
mA
mA
µA
pF
PA to PE,
PF4 to PF7,
PH (VOL only)
PI1 to PI7, PJ,
SO, SCK,
RST∗1(VOL only)
Other than VDD,
Vss, AVDD, and
AVss pins
Page 17
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CXP87132/87140
∗1
tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2
bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
XTAL
t
XH tXLtCF tCR
0.4V
V
DD – 0.4V
1/fc
EXTAL
A
A
Crystal oscillation
Ceramic oscillation
EXTAL
XTAL
External clock
EXTAL
XTAL
74HC04
C1
C2
AC Characteristics
(1) Clock timing
System clock frequency
System clock input pulse width
System clock input
rising and falling times
Event count clock input
pulse width
Event count clock input
rising and falling times
fC
tXL,
tXH
tCR,
tCF
tEL,
tEH
tER,
tEF
XTAL
EXTAL
XTAL
EXTAL
XTAL
EXTAL
PE1/EC
PE1/EC
MHz
ns
ns
ns
ms
Item Symbol Pin Condition Unit
Fig. 1,
Fig. 2
Fig. 1,
Fig. 2 (External clock drive)
Fig. 1, Fig. 2
(External clock drive)
Fig. 3
Fig. 3
Min.
1
1
28
37.5
tsys × 4
∗1
Max.
16
12
200
20
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)
Fig. 1. Clock timing
VDD = 4.5 to 5.5V
VDD = 4.5 to 5.5V
Fig. 2. Clock applied condition
EC
tEH tELtEF tER
0.2VDD
0.8VDD
Fig. 3. Event count clock timing
AAA
AAA
Page 18
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CXP87132/87140
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI →SI0, and SO → SO0 respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
CS ↓ → SCK
delay time
CS ↑ → SCK
floating delay time
CS ↓ → SO
delay time
CS ↓ → SO
floating delay time
CS
High level width
SCK
cycle time
SCK
High and Low level widths
SI input setup time
(against SCK ↑)
SI input hold time
(against SCK ↑)
SCK ↓ → SO delay time
tDCSK
tDCSKF
tDCSO
tDCSOF
tWHCS
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK0
SCK0
SO0
SO0
CS0
SCK0
SCK0
SI0
SI0
SO0
ns
ns
ns
ns
ns
Symbol Pin Min.
tsys + 200
tsys + 200
tsys + 200
tsys + 200
tsys + 200
2tsys + 200
8000/fc
tsys + 100
8000/fc – 100
–tsys + 100
200
2tsys + 100
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2tsys + 200
100
Max. UnitCondition
Page 19
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CXP87132/87140
Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively.
Note 3) The load of SCK output mode and SO output delay time is 50pF.
Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)
Item
CS ↓ → SCK
delay time
CS ↑ → SCK
floating delay time
CS ↓ → SO
delay time
CS↓ → SO
floating delay time
CS
High level width
SCK
cycle time
SCK
High and Low level widths
SI input setup time
(against SCK ↑)
SI input hold time
(against SCK ↑)
SCK ↓ → SO delay time
tDCSK
tDCSKF
tDCSO
tDCSOF
tWHCS
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK0
SCK0
SO0
SO0
CS0
SCK0
SCK0
SI0
SI0
SO0
ns
ns
ns
ns
ns
Symbol Pin Min.
tsys + 250
tsys + 200
tsys + 250
tsys + 200
tsys + 200
2tsys + 200
8000/fc
tsys + 100
8000/fc – 150
–tsys + 100
200
2tsys + 100
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2tsys + 250
125
Max. UnitCondition
Page 20
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CXP87132/87140
Fig. 4. Serial transfer timing (CH0)
CS0
SCK0
0.2V
DD
0.8VDD
tWHCS
tDCSK tDCSKF
0.8VDD
0.2VDD
0.8VDD
tKCY
tKL tKH
0.8VDD
0.2VDD
SI0
t
SIK
Input
data
tDCSO tKSO tDCSOF
Output data
0.8V
DD
0.2VDD
SO0
tKSI
Page 21
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CXP87132/87140
Serial transfer (CH1) (SIO mode) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pin Min. Max. UnitCondition
SCK1 cycle time
SCK1 High and Low
level widths
SI1 input setup time
(against SCK1 ↑)
SI1 input hold time
(against SCK1 ↑)
SCK1 ↓ → SO1 delay
time
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK1
SCK1
SI1
SI1
SO1
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
2tsys + 200
16000/fc
tsys + 100
8000/fc – 50
100
200
tsys + 200
100
tsys + 200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Serial transfer (CH1) (SIO mode) (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)
Item Symbol Pin Min. Max. UnitCondition
SCK1 cycle time
SCK1 High and Low
level widths
SI1 input setup time
(against SCK1 ↑)
SI1 input hold time
(against SCK1 ↑)
SCK1 ↓ → SO1 delay
time
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK1
SCK1
SI1
SI1
SO1
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
2tsys + 200
16000/fc
tsys + 100
8000/fc – 150
100
200
tsys + 200
100
tsys + 250
125
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF.
Page 22
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CXP87132/87140
Fig. 5. Serial transfer CH1 timing (SIO mode)
SCK1
SI1
SO1
t
KCY
tKL tKH
0.2VDD
0.8VDD
tSIK tKSI
tKSO
Input data
Output data
0.2V
DD
0.8VDD
0.2VDD
0.8VDD
Page 23
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CXP87132/87140
SO1 cycle time
SI1 data setup time
SI1 data hold time
tLCY
tLSU
tLHD
SO1
SI1
SI1
SI1
Note 1)
2
2
104 µs
µs
µs
Item Symbol Pin Condition Min. Typ. Max. Unit
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Note 1) tLCY specifies only serial mode register (CH1) (SIOM1: Address 01FAH) lower 2 bits (SO1 clock
selection) has been set at 104µs.
Note 2) The load of SO1 pin is 50pF + 1TTL.
SO1 cycle time
SI1 data setup time
SI1 data hold time
tLCY
tLSU
tLHD
SO1
SI1
SI1
SI1
Note 1)
2
2
104 µs
µs
µs
Item Symbol Pin Condition Min. Typ. Max. Unit
Serial transfer (CH1) (Special mode)
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)
Note 1) tLCY specifies only serial mode register (CH1) (SIOM1: Address 01FAH) lower 2 bits (SO1 clock
selection) has been set at 104µs.
Note 2) The load of SO1 pin is 50pF.
Fig. 6. Serial transfer CH1 timing (Special mode)
SO1
SI1
tLCY
Start bit Output data bit
t
LCY
0.5VDD
0.8VDD
0.2VDD
tLCY/2
tLSU tLHD
Input
data bit
Serial transfer (CH1) (Special mode)
Page 24
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CXP87132/87140
Fig. 7. Definitions of A/D converter terms
Conversion time
Sampling time
Reference input voltage
Analog input voltage
tCONV
tSAMP
VREF
VIAN
AVREF
AN0 to AN11
IREF
Only for A/D converter
operation
Ta = 25°C
VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V
Operating mode
AVREF = 4.0 to 5.5V
VDD = AVDD = 4.5 to 5.5V
Sleep mode
Stop mode
Linearity error
Absolute error
Resolution
AVREF current
AVREF
µs
µs
V
V
AVDD
AVREF
1.0
mA
10
µA
0.6
160/fADC
∗1
12/fADC
∗1
AVDD – 0.5
0
Item Symbol Pin Condition Min. Typ. Max.
Unit
Bits
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)
8
±1±2LSB
LSB
Analog input
Linearity error
V
FTVZT
00H
01H
FEH
FFH
Digital conversion value
Conversion time
Sampling time
Reference input voltage
Analog input voltage
tCONV
tSAMP
VREF
VIAN
AVREF
AN0 to AN11
IREF
Only for A/D converter
operation
Ta = 25°C
VDD = AVDD = AVREF = 3.3V
VSS = AVSS = 0V
Operating mode
AVREF = 2.7 to 3.6V
Sleep mode
Stop mode
Linearity error
Absolute error
Resolution
AVREF current
AVREF
µs
µs
V
V
AVDD
AVREF
0.7
mA
10
µA
0.4
160/fADC
∗1
12/fADC
∗1
AVDD – 0.3
0
Item Symbol Pin Condition Min. Typ. Max.
Unit
Bits
(Ta = –20 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V reference)
8
±1±2LSB
LSB
A/D converter characteristics
VDD = AVDD = 3.0 to 3.6V
∗1
The value of fADC is as follows by selecting ADC
operation clock (MSC: Address 01FFH bit 0).
When PS2 is selected, fADC = fc/2
When PS1 is selected, fADC = fc
Page 25
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CXP87132/87140
External interruption
high and low level widths
Reset input low level width
INT0
INT1
INT2
PJ0 to PJ7
RST
1
32/fc
µs
µs
Item Symbol Pin Condition Min. Max. Unit
tIH
tIL
tRSL
(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)
0.2VDD
0.8VDD
tIH tIL
INT0
INT1
INT2
PJ0 to PJ7
(During standby release input)
(Falling edge)
Fig. 8. Interruption input timing
tRSL
0.2VDD
RST
Fig. 9. Reset input timing
Power supply rising edge
Power supply cut-off time
tR
tOFF
VDD
Power on reset
Repetitive power on reset
0.05
1
30 ms
ms
Item Symbol Pin Condition Min. Max. Unit
(5) Power on reset
Power on reset
∗
(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)
0.2V
0.2V
3.0V
V
DD
tR tOFF
The power supply should rise smoothly.
Fig. 10. Power on reset
∗
Specifies only when power on reset function is selected.
Page 26
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CXP87132/87140
External clock input frequency
External clock input pulse width
External clock input
rising and falling times
Prescaler output delay time
(against PCK ↑)
Prescaler output
rising and falling times
fPCK
tWH, tWL
tR,
tF
tPLH
tPHL
tTLH
tTLH
PCK
PCK
PCK
PO
PO
External clock input
PCK tR = tF = 6ns
External clock input
PCK tR = tF = 6ns
33
80
60
50
20
12
200
130
100
100
40
MHz
ns
ns
ns
ns
ns
ns
Item Symbol Pin Condition Min. Typ. Max. Unit
(6) General purpose prescaler
Note) The load of PO pin is 50pF.
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
External clock input frequency
External clock input pulse width
External clock input
rising and falling times
Prescaler output delay time
(against PCK ↑)
Prescaler output
rising and falling times
fPCK
tWH, tWL
tR,
tF
tPLH
tPHL
tTLH
tTLH
PCK
PCK
PCK
PO
PO
External clock input
PCK tR = tF = 6ns
External clock input
PCK tR = tF = 6ns
33
130
90
100
30
12
200
220
150
280
70
MHz
ns
ns
ns
ns
ns
ns
Item Symbol Pin Condition Min. Typ. Max. Unit
General purpose prescaler
Note) The load of PO pin is 50pF.
(Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)
1/fPCK
tF
tWH
0.8VDD
tR
tWL
0.5VDD
0.2VDD
tPLH
0.8VDD
0.5VDD
0.2VDD
tTLH
tTHL
tPHL
PCK
PO
Fig. 11. General purpose prescaler timing
Page 27
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CXP87132/87140
(7) Others (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)
Item
CFG input
high and low level widths
DFG input
high and low level widths
DPG minimum pulse width
DPG minimum
removal time
PBCTL input
high and low level widths
EXI input
high and low level widths
PMI input
high and low level widths
PMSK input
high and low level widths
tCFH
tCFL
tDFH
tDFL
tDPW
trem
tCTH
tCTL
tEIH
tEIL
tPIH
tPIL
tPSH
tPSL
CFG
DFG
DPG
DPG
PBCTL
EXI0
EXI1
PMI
PMSK
ns
ns
ns
ns
ns
ns
ns
ns
Symbol Pin Min.
tFRC × 24 + 200
tFRC × 8 + 200
50
50
tFRC × 8 + tsys + 200
tFRC × 8 + tsys + 200
tsys + 200
tsys + 200
Max. Unit
tsys = 2000/fc
tsys = 2000/fc
Condition
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The value of tFRC is as follows by selecting FRC clock (FRCS: 01EEH bit 7)
When PS0 is selected, tFRC = 1000/fc (ns)
When PS1 is selected, tFRC = 2000/fc (ns)
Page 28
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CXP87132/87140
0.8VDD
CFG
tCFH tCFL
0.2VDD
0.8VDD
DFG
tDFH tDFL
0.2VDD
0.8VDD
PBCTL
tCTH tCTL
0.2VDD
0.8VDD
EXI0
EXI0
tEIH tEIL
0.2VDD
0.8VDD
trem tDPW
trem
DPG
Fig. 12. Other timings
Page 29
– 29 –
CXP87132/87140
0.8VDD
PMI
tPIH tPIL
0.2VDD
0.8VDD
PMSK
tPSH tPSL
0.2VDD
Page 30
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CXP87132/87140
Supplement
A
EXTAL
XTAL
C
1
C2
Rd
Main clock
∗1
In PG4/SYNC0/PMI pin and PG5/SYNC1 pin, the input circuit format can be selected every pin.
Reset pin pull-up resistor
Power on reset circuit
Genaral purpose prescaler oscillation circuit
Input circuit format
∗1
Non-existent
Non-existent
Non-existent
CMOS schmitt
Item
Content
Existent
Existent
Existent
TTL schmitt
Manufacturer Model fc (MHz) C1 (pF) C2 (pF) Rd(Ω)
Circuit
example
RIVER ELETEC
CORPORATION
HC-49/U03
KINSEKI LTD.
HC-49/U (-S)
8.00
10.00
12.00
16.00
8.00
10.00
12.00
16.00
10
5
22 (15)
15
12
10
5
22 (15)
15
12
0
0
(i)
(i)
Mask Option Table
Fig. 13. Recommended oscillation circuit
AAA
Page 31
– 31 –
CXP87132/87140
0.1
0.5
1.0
5.0
10.0
20.0
2 3 4 5 6 7
0.1
0.5
1.0
5.0
10.0
20.0
2 3 4 5 6 7
5
10
15
20
25
51 10 15
5
10
15
20
25
51 10 15
IDD vs. VDD
(fc = 16MHz, Ta = 25°C, Typical)
IDD vs. VDD
(fc = 12MHz, Ta = 25°C, Typical)
1/2 dividing mode
1/16 dividing mode
1/4 dividing mode
Sleep mode
I
DD
– Supply current [mA]
I
DD
– Supply current [mA]
VDD – Supply voltage [V]
V
DD – Supply voltage [V]
1/2 dividing mode
1/16 dividing mode
1/4 dividing mode
Sleep mode
fc – System clock [MHz]
I
DD
– Supply current [mA]
IDD vs. fc
(VDD = 3.3V, Ta = 25°C, Typical)
fc – System clock [MHz]
I
DD
– Supply current [mA]
1/2 dividing mode
1/16 dividing mode
1/4 dividing mode
Sleep mode
1/2 dividing mode
1/16 dividing mode
1/4 dividing mode
Sleep mode
IDD vs. fc
(VDD = 5V, Ta = 25°C, Typical)
Characteristics Curve
Page 32
– 32 –
CXP87132/87140
Package Outline Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
PACKAGE STRUCTURE
23.9 ± 0.4
QFP-100P-L01
100PIN QFP (PLASTIC)
20.0 – 0.1
+ 0.4
0.15 – 0.05
+ 0.1
15.8 ± 0.4
17.9 ± 0.4
14.0 – 0.1
+ 0.4
2.75 – 0.15
+ 0.35
A
0.65
M
0.13
QFP100-P-1420
1.7g
1
100
81
80 51
50
31
30
0.3 – 0.1
+ 0.15
DETAIL A
0° to 10°
0.8 ± 0.2
(16.3)
0.15
0.1 – 0.05
+ 0.2
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42 ALLOY
PACKAGE STRUCTURE
DETAIL A
LQFP-100P-L01
LQFP100-P-1414
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗ 14.0 ± 0.1
75
51
50
26
25
1
76
0.5
0.18 – 0.03
+ 0.08
(0.22)
A
1.5 – 0.1
+ 0.2
0.127 – 0.02
+ 0.05
0.5 ± 0.2
(15.0)
0° to 10°
0.1 ± 0.1
0.5 ± 0.2
100
0.1
NOTE: Dimension “∗” does not include mold protrusion.
0.8g
0.13
M
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