Datasheet CXP85640, CXP85632 Datasheet (Sony)

CXP85632/85640

For the availability of this product, please contact the sales office.

CMOS 8-bit Single Chip Microcomputer

Description

The CXP85632/85640 is a CMOS 8-bit micro­computer which consists of A/D converter, serial
interface, timer/counter, time-base timer, closed
caption decoder, data slicer, on-screen display
function, I2C bus interface, PWM output, remote
control receiver, HSYNC counter and watchdog
timer as well as basic configuration like 8-bit CPU,
ROM, RAM and I/O port.

Also this IC provides power-on reset function and
sleep function which enables to lower power
consumption.

Features

• A wide instruction set (213 instructions) to cover various types of data.

— 16-bit arithmetic/multiplication and division/boolean bit operation instructions

• Minimum instruction cycle 333ns at 12MHz operation

• Incorporated ROM 32K bytes (CXP85632)

40K bytes (CXP85640)

• Incorporated RAM 1888 bytes

(excluding the closed caption decoder and on-screen display VRAM)

• Peripheral functions

— A/D converter 8 bits, 6 channels, successive approximation method

(Conversion time of 26.7µs/12MHz)
— Serial interface 8-bit clock, sync type, 1 channel
— Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer
— Closed caption decoder

Incorporated decode slicer,

conforming to FCC, 8 × 13 dots, 192 character types, 15 character colors,

4 lines of 34 characters, italic, underline, vertical scroll,

15 frame background colors/half blanking
— On-screen display (OSD) function

12 × 16 dots, 128 character types, 15 character colors, 4 lines of 24 characters,

8 frame background colors/half blanking, edging per line (half dot), vertical scroll

jitter elimination circuit
— I2C bus interface
— PWM output 8 bits, 4 channels
— Remote control receiver circuit

Incorporated 6-stage FIFO 8-bit pulse measurement counter
— HSYNC counter 2 channels
— Watchdog timer

• Interruption 15 factors, 15 vectors, multi-interruption possible

• Standby mode SLEEP

• Package 64-pin plastic SDIP/QFP

• Piggyback/evaluation chip CXP85690 64-pin ceramic PSDIP (accommodates custom font)

64 pin SDIP (PIastic) 64 pin QFP (PIastic)

Structure

Silicon gate CMOS IC

Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conform to the I2C Standard Specifications as defined by Philips.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E95510-PS

Vss
V

DD

MP
RST
XTAL
EXTAL

PA0 to PA78PB0 to PB78PC0 to PC78PD0 to PD78PE0 to PE23PF0 to PF7

8

PORT A

PORT B

PORT C

PORT D

PORT E

PORT F

RAM

1888 BYTES

SYSTEM CONTROL

CLOCK GENERATOR/

CXP85632/85640

PWM0 to PWM3

DD

INT2
INT1
INT0

CVss
CV
Cap
Rex

SPC700 CPU CORE

2

DATA SLICER

CC DECODER

ROM

32K/40K BYTES

3

2

ON SCREEN DISPLAY

PRESCALER/

TIME BASE TIMER

INTERRUPT CONTROLLER

SERIAL INTERFACE UNIT

WATCHDOG TIMER

FIFO

8BIT TIMER 1

8BIT TIMER/COUNTER 0

REMOCON

HSYNC COUNTER 0

8BIT PWM 4CH

C BUS

2

I

INTERFACE UNIT

HSYNC COUNTER 1

A/D CONVERTER 6CH

SCL1
SCL0

SDA1
SDA0

VIN

Block Diagram

XLC

R

EXLC

I

B

G

YS

YM

VSYNC

HSYNC

SI

SO

SCK

EC

TO

RMC

HSC0

HSC1

AN0 to AN5

– 2 –

Pin Assignment (Top View) 64-pin SDIP

CXP85632/85640

PC3
PC2

PC1
PC0

EC/PD7

RMC/PD6

HS1/PD5
HS0/PD4

SI/PD3

SO/PD2

SCK/PD1

INT2/PD0

HSYNC/PA7

VSYNC/PA6

RST

Vss

XTAL

EXTAL
PA5/AN5
PA4/AN4
PA3/AN3

PA2/AN2
PA1/AN1
PA0/AN0

CVss

Cap
Rex

VIN

CV

INT1/PB7

PB6
PB5

DD

10
11
12
13
14
15
16
17
18
19
20

23

26

29
30

32

21
22

24
25

27
28

31

1

2
3
4

5
6
7
8
9

64

63

62

61
60

59

58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

43

42

41
40
39

38
37
36
35

34
33

PC4
PC5

PC6
PC7

PF0/PWM0

PF1/PWM1
PF2/PWM2
PF3/PWM3
PF4/SCL0
PF5/SCL1
PF6/SDA0
PF7/SDA1
PE0/TO

PE1
PE2/INT0
MP
Vss
VDD
NC
EXLC
XLC
YM

YS
I
B
G
R

PB0
PB1
PB2

PB3
PB4

Note) 1. NC (Pin 46) must be connected to VDD.

2. Vss (Pins 16 and 48) must be connected to GND.

3. MP (Pin 49) must be connected to GND.

4. Cap (Pin 26) must be connected to CVSS via a capacitor.

5. Rex (Pin 27) must be connected to CVDD via a resistor of 33kΩ.

– 3 –

Pin Assignment (Top View) 64-pin QFP

PD6/RMC

PD7/EC

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PF0/PWM0

PF2/PWM2

PF1/PWM1

CXP85632/85640

HS1/PD5
HS0/PD4

SI/PD3

S0/PD2

SCK/PD1

INT2/PD0

HSYNC/PA7
VSYNC/PA6

RST

Vss

XTAL

EXTAL

PA5/AN5

PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0

CVss

10

11
12
13
14
15
16
17
18
19

62

64

63

61

60

59

1
2

3

4
5

6

7
8

9

58

57

56

55

54

53

52

51
50
49
48
47
46
45
44

42

40
39

37
36
35

33

43

41

38

34

PF3/PWM3
PF4/SCL0
PF5/SCL1
PF6/SDA0
PF7/SDA1
PE0/TO
PE1

PE2/INT0
MP
Vss

V

DD

NC
EXLC
XLC
YM
YS
I

B
G

20

Cap

21

Rex

22

VIN

23

DD

CV

25

24

PB6

INT1/PB7

26

PB5

27

PB4

28

PB3

29

PB2

30

PB1

31

PB0

Note) 1. NC (Pin 40) must be connected to VDD.

2. Vss (Pins 10 and 42) must be connected to GND.

3. MP (Pin 43) must be connected to GND.

4. Cap (Pin 20 ) must be connected to CVSS via a capacitor.

5. Rex (Pin 21) must be connected to CVDD via a resistor of 33kΩ.

32

R

– 4 –

Pin Functions

CXP85632/85640

Pin name

PA0/AN0

to

PA5/AN5
PA6/VSYNC
PA7/HSYNC

PB0 to PB6

PB7/INT1

PC0 to PC7

PD0/INT2
PD1/SCK

PD2/SO
PD3/SI
PD4/HS0
PD5/HS1
PD6/RMC

I/O

I/O/Analog input

I/O/Input
I/O/Input

I/O

I/O/Input

I/O

I/O/Input
I/O/I/O

I/O/Output
I/O/Input
I/O/Input
I/O/Input
I/O/Input

Functions

(Port A)
8-bit I/O port. I/O

Analog inputs to A/D converter. (6 pins)

can be set in a unit
of single bits.
(8 pins)

OSD display vertical sync signal input.
OSD display horizontal sync signal input.

(Port B)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

Input for external interruption request. Active at
the falling edge.

(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. (8 pins)

Input for external interruption request. Active at
the falling edge.

(Port D)
8-bit I/O port. I/O
can be set in a unit
of single bits.
Capable of driving
12mA sync current.
(8 pins)

Serial clock I/O.
Serial data output.
Serial data input.
HSYNC counter (CH0) input.
HSYNC counter (CH1) input.

Remote control receiver circuit input.
PD7/EC
PE0/TO
PE1

PE2/INT0
PF0/PWM0

to

PF3/PWM3
PF4/SCL0

PF5/SCL1
PF6/SDA0

PF7/SDA1
R, G, B, I, YS, YM

I/O/Input
I/O/Output
I/O

I/O/Input

Output/Output

Output/I/O

Output/I/O
Output

External event input for timer/counter.

(Port E)

Rectangular wave output for timer/counter.

3-bit I/O port. I/O
can be set in a unit
of single bits.
(3 pins)

(Port F)
8-bit output port
with large current

Input for external interruption request.

Active at the falling edge.

8-bit PWM outputs.

(4 pins)

(12mA) N-ch open
drain output.

Transfer clock I/O for I2C bus interface. (2 pins)

Lower 4 bits are
12V drive and upper
4 bits are 5V drive.

Transfer data I/O for I2C bus interface. (2 pins)

OSD display 6-bit outputs. (6 pins)

– 5 –

CXP85632/85640

Pin name
EXLC
XLC

VIN

Cap

Rex
CVDD

CVSS
EXTAL
XTAL

RST

MP
NC

I/O Functions
Input
Output

Input

—

—

OSD display clock oscillation I/O.
Oscillator frequency is determined by external L and C.

Input of external composite video signal. Input a 2Vp-p signal via a
capacitor.

Capacitor connection for the data slicer. Connect a capacitor between
Cap and CVSS.

Resistor connection for the data slicer. Connect a 33kΩ resistor
between Rex and CVDD.

Positive power supply for data slicer.

GND for data slicer.
Input
Output

System clock oscillator crystal connection. When using an external

clock, input to EXTAL pin and leave XTAL pin open.

Low level active system reset. This pin acts as I/O pin and outputs low
I/O

level through incorporated power-on reset function when the power

turned on. (Mask option)
Input

Test mode input. Must be connected to GND.

Not connected.

Under normal conditions, connect to VDD.

VDD
Vss

Positive power supply.

GND. Connect two VSS pins to GND.

– 6 –

I/O Circuit Format for Pins

Pin When resetCircuit format

Port A

CXP85632/85640

Port A data

PA0/AN0

to

PA5/AN5

6 pins

PA6/VSYNC
PA7/HSYNC

Data bus

Port A function selection

“0” when reset

A/D converter

Port A

Data bus

Port A direction
“0” when reset

RD (Port A)

RD (Port A)

Input multiplexer

Port A data

Port A direction

Schmitt input

IP

IP

Input
protection
circuit

Hi-Z

Hi-Z

2 pins

PB0 to PB6
PB7/INT1
PC0 to PC7

16 pins

VSYNC, HSYNC

Port B
Port C

Data bus

Port B, C data

Port B, C direction

“0” when reset

RD (Port B, C)

INT1

Input polarity

"0" when reset

IP

Hi-Z

Schmitt input

– 7 –

Pin When resetCircuit format

Port D

Port D data

PD0/INT2
PD3/SI
PD4/HS0
PD5/HS1

Port D direction

“0” when reset

PD6/RMC
PD7/EC

6 pins

Data bus

RD (Port D)

INT2, SI, HS0, HS1, RMC, EC

Port D

SCK, SO

Serial output enable

Schmitt input

∗

∗

IP

Large current 12mA

CXP85632/85640

Hi-Z

PD1/SCK
PD2/SO

2 pins

PE0/TO
PE1
PE2/INT0

Port E

Port D data

Port D direction

“0” when reset

Data bus

RD (Port D)

SCK only

TO

Port E function selection

“1” when reset

Port E data

“1” when reset for PE0, 1

Port E direction

“1” when reset for PE0, 1
“0” when reset for PE2

Data bus

Schmitt input

∗

Large current 12mA

Schmitt input
only for PE2

∗

IP

Hi-Z

PE0, PE1:

IP

High

PE2: Hi-Z

3 pins

RD (Port E)

INT0

– 8 –

Pin When resetCircuit format

CXP85632/85640

PF0/PWM0

to

PF3/PWM3

4 pins

PF4/SCL0
PF5/SCL1
PF6/SDA0
PF7/SDA1

4 pins

Port F

Port F

PWM0 to PWM3

Port F selection

“0” when reset

Port F data

“1” when reset

SCL, SDA

I2C output enable

Port F data

“1” when reset

SCL, SDA

2

C circuit)

(I

Schmitt input

Hi-Z

∗

∗

12V drive voltage

Large current 12mA

∗

Hi-Z

IP

BUS SW

To internal I

(To SCL1 for SCL0)

∗

Large current 12mA

2

C pins

R
G
B

I

YS

YM

6 pins

EXLC
XLC

2 pins

R, G, B, I, YS, YM

Output polarity
“0” when reset

EXLC

XLC

Hi-Z

Output becomes active
by data writing to output
polarity register.

IP

Oscillator control

Oscillation

halted

IP

OSD display clock

– 9 –

Pin When resetCircuit format

A

EXTAL

EXTAL

IP

XTAL

XTAL

2 pins

Pull-up resistor

RST

Mask option

OP

Schmitt input

1 pin

• Diagram indicates equivalent
circuit during oscillation.

• Feedback resistor is disconnected
during STOP.
(This device does not enter in the
STOP mode.)

From power-on reset circuit
(Mask option)

CXP85632/85640

Oscillation

Low level

– 10 –

CXP85632/85640

Absolute Maximum Ratings (Vss = 0V reference)

Item Symbol Ratings Unit Remarks
Supply voltage
Input voltage
Output voltage
Medium voltage tolerance output voltage
High level output current
High level total output current

VDD
VIN
VOUT
VOUTP
IOH
ΣIOH

IOL

–0.3 to +7.0
–0.3 to +7.0
–0.3 to +7.0

–0.3 to +15.0

–5

–50

15

∗1
∗1

V
V
V

V
mA
mA

mA

PF0 to PF3 pins

Total of all output pins
Excludes large current output

port (value per pin)

Low level output current

IOLC

Low level total output current
Operating temperature
Storage temperature

Allowable power dissipation

∗1

VIN and VOUT should not exceed VDD + 0.3V.

∗2

The large current output port is Port D (PD) and Port F (PF).

ΣIOL
Topr
Tstg

PD

20

100

–20 to +75

–55 to +150

1000

600

mA
mA

mW
mW

Large current output port
(value per pin∗2)

Total of all output pins
°C
°C

SDIP

QFP

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.

Recommended Operating Conditions (Vss = 0V reference)

Item Symbol Min. Max. Unit Remarks

Guaranteed operation range for 1/2 or 1/4

4.5

Supply voltage

VDD

3.5

2.5

Data slicer supply
voltage

CVDD

VIH
High level
input voltage

VIHS

VIHEX

VIL
Low level
input voltage

VILS

VILEX
Operating temperature

∗1

This device does not enter in the STOP mode.

∗2

PA, PB, PC, PE0, PE1, SCL0, SCL1, SDA0, SDA1 pins.

∗3

INT2, SCK, SO, SI, HS0, HS1, RMC, EC, INT1, HSYNC, VSYNC, RST pins.

∗4

Specifies only during external clock input.

∗5

CVDD and VDD should be set to the same voltage.

Topr

4.5

0.7VDD

0.8VDD

VDD – 0.4

0
0

–0.3

–20

5.5

5.5

5.5

5.5

VDD
VDD

VDD + 0.3

0.3VDD

0.2VDD

0.4

+75

V

frequency dividing mode
Guaranteed operation range for 1/16

V

frequency dividing or SLEEP mode

V

Guaranteed data hold range for STOP mode

∗5

V

∗2

V

∗3

V
V
V
V
V

EXTAL pin

∗2
∗3

EXTAL pin

∗4

∗4

°C

∗1

– 11 –

CXP85632/85640

DC Characteristics (Ta = –20 to +75°C, Vss = 0V reference)

Item

High level
output voltage

Low level
output voltage

Input current

I/O leakage current

Open drain output
leak current
(N-ch Tr off case)

Symbol

VOH

VOL

IIHE

IIHL

IILR

IIZ

ILOH

Pin Condition Min. Typ. Max. Unit

PA to PD, PE, R, G,
B, I, YS, YM

PA to PD, PE, R, G,
B, I, YS, YM,
PF0 to PF3, RST

∗1

PD, PF
PF4 to PF7

(SCL0, SCL1,
SDA0, SDA1)

EXTAL

∗2

RST
PA to PE, HSYNC,

VSYNC, R, G, B, I,
YS, YM, RST

∗2

PF0 to PF3
PF4 to PF7

VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA

VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA

VDD = 4.5V, IOL = 12.0mA
VDD = 4.5V, IOL = 3.0mA

VDD = 4.5V, IOL = 4.0mA
VDD = 5.5V, VIH = 5.5V

VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 0.4V

VDD = 5.5V,
VI = 0, 5.5V

VDD = 5.5V, VOH = 12.0V
VDD = 5.5V, VOH = 5.5V

4.0

3.5

0.5
–0.5
–1.5

0.4

0.6

1.5

0.4

0.6
40

–40

–400

±10

50
10

V
V

V
V

V
V

V

µA
µA
µA

µA

µA
µA

I2C bus switch
connection impedance
(Output Tr off case)

RBS

SCL0: SCL1
SDA0: SDA1

VDD = 4.5V
VSCL0 = VSCL1 = 2.25V
VSDA0 = VSDA1 = 2.25V

120

1/2 frequency dividing mode

IDD

VDD = 5.5V
12MHz crystal oscillation

18

30

(C1 = C2 = 15pF)
SLEEP mode

VDD = 5.5V,
12MHz crystal oscillation

0.9

3

Supply current

IDDSL

VDD

∗3

(C1 = C2 = 15pF)

∗4

—

—

—

IDDST

STOP mode
VDD = 5.5V,
termination of 12MHz
oscillation

ICVDD

Input capacitance

∗1

RST pin is specified only when the power-on reset circuit is selected with mask option.

∗2

In RST pin, the input current is specified when the pull-up resistor is selected; the leakage current when no

CIN

CVDD
PA to PE, SCL, SDA,

EXLC, EXTAL, VIN,
RST

VDD = 5.5V

1MHz clock
0V for all pins excluding
measured pins

—

5.0

10

10.0

20

resistor is selected.

∗3

When all pins are open. Specifies only when the OSD oscillation stops.

∗4

This device does not enter in the STOP mode.

Ω

mA

mA

µA

mA

pF

– 12 –

AC Characteristics

A

A

(1) Clock timing

CXP85632/85640

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item System Pin Condition Min. Max. Unit

System clock frequency

System clock input
pulse width

System clock
rise and fall times

Event counter input
clock pulse widtth

Event counter input clock
rise and fall times

∗

1

tsys indicates three values according to the contents of the clock control register (CLC: 00FEH) upper

2 bits. (CPU clock selection)

fC

tXL,
tXH

tCR,
tCF

tEH,
tEL

tER,
tEF

XTAL
EXTAL

EXTAL

EXTAL

EC

EC

Fig. 1, Fig. 2

Fig. 1, Fig. 2
External clock drive

Fig 1, Fig 2
External clock drive

Fig. 3

Fig. 3

tsys

37.5

∗1

+ 50

Typ.

12.0

200

20

tsys (ns) = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Fig. 1. Clock timing

1/fc

MHz

ns

ns

ns

ms

EXTAL

Fig. 2. Clock applied condition

Crystal oscillator
Ceramic oscillator

EXTAL

AA

C

1 C2

Fig. 3. Event count clock timing

EC

t

XH tXLtCF tCR

External clock

XTAL

EH tELtEF tER

t

EXTAL

AA

XTAL

OPEN

DD – 0.4V

V

0.4V

0.8VDD

0.2VDD

– 13 –

CXP85632/85640

(2) Serial transfer (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

SCK cycle time

SCK
high and low level widths

SI input set-up time
(for SCK↑)

SI input hold time
(for SCK↑)

System Pin Condition Min. Max. Unit

tKCY

tKH
tKL

tSIK

tKSI

SCK

Input mode
Output mode
SCK input mode

SCK

SCK output mode
SCK input mode

SI

SCK output mode
SCK input mode

SI

SCK output mode

1000

8000/fc

400

4000/fc – 50

100
200
200
100

SCK input mode

SCK ↓ → SO delay time

tKSO

SO

SCK output mode

Note) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL.

Fig. 4. Serial transfer timing

tKCY

200
100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

SCK

SI

SO

tKL tKH

tSIK

Input data

tKSO

0.8VDD

0.2VDD

0.8VDD

0.2VDD

tKSI

0.8VDD

0.2VDD

Output data

– 14 –

CXP85632/85640

(3) A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Typ. Max. Unit
Resolution
Linearity error
Zero transition

voltage
Full-scale transition

voltage
Conversion time
Sampling time
Analog input voltage

∗1

VZT

∗2

VFT

tCONV
tSAMP

VIAN

AN0 to AN5

Fig. 5. Definitions for A/D converter terms

FF

H

FEH

Digital conversion value

Linearity error

8

±1

Ta = 25°C
VDD = 5.0V

–50

10

70

Vss = 0V

4910

160/fADC

12/fADC

∗3

∗3

0

∗1

VZT: Digital conversion values change between 00H←→01H.

∗2

VFT: Digital conversion values change between 0EH←→0FH.

∗3

fADC indicates the below values due to the bit 6 (CKS) of

4970

5030

VDD

A/D control registor (ADC: 00F9H) and the bit 7 (PCK1) and
bit 6 (PCK0) of clock control registor (CLC: 00FEH)

Bits

LSB

mV

mV

µs
µs

V

01H
00H

VZT VFT

Analog input

PCK1, 0

00 (φ = fEX/2)
01 (φ = fEX/4)
11 (φ = fEX/16)

CKS

0 (φ/2 selection) 1 (φ selection)

fADC = fC/2
fADC = fC/4

fADC = fC/16

fADC = fC
fADC = fC/2
fADC = fC/8

– 15 –

(4) Interrupt, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Max. Unit

CXP85632/85640

External interrupt
high and low level widths

Reset input low level width

Fig. 6. Interrupt input timing

INT0
INT1
INT2
(falling edge)

Fig. 7. RST input timing

RST

tIH
tIL

tRSL

INT0
INT1
INT2

RST

tIH tIL

0.8VDD

tRSL

0.2VDD

1

32/fc

µs

µs

0.2VDD

(5) Power-on reset

∗1

Item Symbol Pin Condition Min. Max. Unit

Power supply rise time

tR

Power-on reset

VDD

Power supply cutt-off time

∗1

Specified only when power-on reset function is selected.

tOFF

Repeated power-on reset

Fig. 8. Power-on reset

DD

V

4.5V

0.2V

tR tOFF

Take care when turning on power.

(Ta = –20 to +75°C, Vss = 0V reference)

0.05
1

50 ms

ms

0.2V

– 16 –

CXP85632/85640

(6) I2C bus timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item
SCL clock frequency
Bus-free time before starting transfer
Hold time for starting transfer
Clock low level width
Clock high level width
Set-up time for repeated transfers
Data hold time
Data set-up time
SDA, SCL rise time
SDA, SCL fall time
Set-up time for transfer completion

∗1

For data hold time, the SCL rise time is not taken into account so that 300ns must be exceeded.

Symbol Pin Condition Min. Max. Unit

fSLC

tBUF
tHD; STA
tLOW
tHIGH
tSU; STA
tHD; DAT
tSU; DAT
tR
tF
tSU; STO

SCL
SDA, SCL
SDA, SCL
SCL
SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL

0

4.7

4.0

4.7

4.0

4.7

∗1

0

250

4.7

Fig. 9. I2C bus transfer data timing

100

1

300

kHz

µs
µs
µs
µs
µs
µs
ns
µs
ns
µs

SDA

t

BUF

SCL

tHD; STA

SP

tLOW

Fig. 10. I2C device recommended circuit

I2C

device

RS RS RS RS RP RP

SDA0
(or SDA1)

SCL0
(or SCL1)

I2C

device

tFtR

tSU; DATtHIGHtHD; DAT

tHD; STA

tSU; STA

t

SU; STO

PSt

• A pull-up resistor must be connected to SDA0 (or SDA1), and SCL0 (or SCL1).

• The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce spike

noise caused by CRT flashover.

– 17 –

(7) OSD (On Screen Display) timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

CXP85632/85640

Item

OSD clock frequency

HSYNC pulse width
HSYNC after-write

rise and fall times
VSYNC before-write

rise and fall times

Fig. 11. OSD timing

For OPOL register (01FDH)

HSYNC

bit 7 at “0”

Symbol

fOSC

tHWD
tHCG

tVCG

Pin Condiiton

EXLC
XLC

HSYNC
HSYNC

VSYNC

tVCG

Fig. 12

Fig. 11
Fig. 11

Fig. 11

tHWD

Min. Max.

4

16.5

1.2
200

1.0

tHCG

0.8VDD

0.2VDD

Unit

MHz

µs
ns

µs

For OPOL register (01FDH)

VSYNC

bit 6 at “0”

0.8VDD

0.2VDD

Fig. 12. LC oscillator circuit connection

EXLC XLC

∗

1

L

∗1

The XLC series resistor can reduce the occurrence of undersired radiation.

R

2C1

C

– 18 –

CXP85632/85640

(8) Data slicer external circuit (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

VIN pin coupling capacitor

Cap pin capacitor

Rex pin pull-up resistor
Composite video signal input

Symbol Pin Min. Unit

CVIN

Ccap

Rrex
Video In

VIN

Cap

Rex
VIN

Fig. 13. Data slicer external recommeded circuit

5.0V

Rrex

CVDD

Rex

Typ. Max.

0.47

4700

33

2.0

µF

pF

kΩ

Vp-p

Remarks

B or more of temperature
characteristics is
recommended.

B or more of temperature
characteristics is
recommended.

CVIN R1

IN

V

C

1R2Video In

Cap

Ccap

CVss

[Recommended Constant]

R1 = 100Ω (error: 5%; allowable power dissipation: 1/8 W or more)
R2 = 1MΩ (error: 5%; allowable power dissipation: 1/8 W or more)
C1 = 820pF (ceramic), B or more of temperature characteristics is recommended.

– 19 –

Supplement

A

A

Fig. 14. SPC700 Series recommended oscillation circuit

(i)

EXTAL

EXTAL

AA

AA

XTAL

XTAL

Rd

Rd

C2C1

CXP85632/85640

Manufacturer

RIVER ELETEC
CO., LTD.

KINSEKI LTD.

∗1

The XTAL series resistor can reduce the effect of electrostatic discharge noise.

Mask Option Table

Item
Reset pin pull-up resistor
Power-on reset circuit

Model fc (MHz)

HC-49/U03
HC-19/U (-S)

Non-existent
Non-existent

12.0

12.0

Inclusion

C1 (pF) C2 (pF)

5

15

Existent
Existent

5

15

Rd (Ω)

∗1

0

∗1

0

Circuit

example

(i)
(i)

– 20 –

Fig. 15. Characteristics curves

CXP85632/85640

100

10

Supply current [mA]

DD –

I

1

(fc = 12MHz, Ta = 25°C, Typical)

IDD vs. VDD

1

frequency
dividing mode

2

frequency

1

dividing mode

4

frequency

1

dividing mode

16

SLEEP mode

50

45

40

35

30

25

Supply current [mA]

20

DD –

I

15

10

(VDD = 5V, Ta = 25°C, Typical)

IDD vs. fc

1

frequency
dividing mode

2

frequency

1

dividing mode

4

1

frequency
dividing mode

16

0.1
23456

V

DD – Supply voltage [V]

Parameter curve for OSD oscillation L vs. C

(theoretically calculated value)

100

10

Inductance [µH]

–

L

f

OSC = C = C1 // C2

0

2π LC

C1, C2 – Capacitance [pF]

5

0

– System clock [MHz]

fc

1

50 100

SLEEP mode

161284

10MHz
12MHz
14MHz

16MHz

– 21 –

Package Outline Unit: mm

CXP85632/85640

64PIN SDIP (PLASTIC) 750mil

+ 0.4

57.6 – 0.1

64

33

+ 0.3

19.05

17.1 – 0.1

+ 0.1

132

1.778
+ 0.4

4.75 – 0.1

0.5 MIN

0.5 ± 0.1

3 MIN

0.9 ± 0.15

PACKAGE STRUCTURE

EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY

8.6g

SONY CODE
EIAJ CODE
JEDEC CODE

SDIP-64P-01

SDIP064-P-0750-A

MOLDING COMPOUND

LEAD TREATMENT
LEAD MATERIAL

PACKAGE WEIGHT

0.25 – 0.05

0° to 15°

52

64

SONY CODE

EIAJ CODE

JEDEC CODE

64PIN QFP(PLASTIC)

23.9 ± 0.4
+ 0.4

20.0 – 0.1

51

1

1.0

+ 0.15

0.4 – 0.1

33

32

+ 0.4

14.0 – 0.1

17.9 ± 0.4

20

19

± 0.12

+ 0.35

2.75 – 0.15

M

PACKAGE STRUCTURE

QFP–64P–L01

∗

QFP064–P–1420

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN
SOLDER/PALLADIUM

COPPER /42 ALLOY

1.5g

0.15 – 0.05

+ 0.2

0.1 – 0.05

PLATING

+ 0.1

0.15

16.3

0.8 ± 0.2

– 22 –