Datasheet CXP84724, CXP84720, CXP84716 Datasheet (Sony)

CXP84716/84720/84724

CMOS 8-bit Single Chip Microcomputer

Description

The CXP84716/84720/84724 is a CMOS 8-bit micro­computer integrating on a single chip an A/D converter,
serial interface, timer/counter, time base timer, capture
timer/counter, FRC capture unit, high-precision timing
pattern generation circuit, PWM output, and the like
besides the basic configurations of 8-bit CPU, ROM,
RAM, and I/O port.

The CXP84716/84720/84724 also provides the
sleep/stop functions that enable to execute the power­on reset function and lower the power consumption.

Features

• A wide instruction set (213 instructions) which covers various types of data.

— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions

• Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V)

333ns at 12MHz operation (3.0 to 5.5V)

• Incorporated ROM capacity 16K bytes (CXP84716)

20K bytes (CXP84720)
24K bytes (CXP84724)

• Incorporated RAM capacity 1120 bytes

• Peripheral functions

— A/D converter 8 bits, 8 channels, successive approximation method

(Conversion time 1.6µs at 16MHz)

— Serial interface Srart-stop synchronization (UART), 1 channel

Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 2 channels
8-bit clock syncronization (MSB/LSB first selectable), 1 channel

— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer,

16-bit capture timer/counter
— FRC capture unit Incorporated 24-bit and 6-stage FIFO
— High-precision timing pattern generation circuit

PPG: maximum of 11 pins, 16 stages programmable, 2 channels
— PWM output 8 bits, 8 channels

• Interruption 19 factors, 15 vectors, multi-interruption possible

• Standby mode Sleep/stop

• Package 100-pin plastic QFP/LQFP

• Piggyback/evaluator CXP84700

100 pin QFP (Plastic) 100 pin LQFP (Plastic)

Structure

Silicon gate CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E96Z13-PS

CXP84716/84720/84724

V

SS

V

DD

RST
XTAL

EXTAL

INT4
INT3
INT2
INT1
INT0
NMI

PA0 to PA7

8

PORT A

CLOCK

GENERATOR/

SYSTEM CONTROL

SPC 700

CPU CORE

NMI

PB0 to PB7
8

PORT B

PC0 to PC7

PD0 to PD7

8

PORT C

RAM

1120 BYTES

ROM

16K/20K/24K

8

PORT D

BYTES

PE0 to PE5

PE6 to PE7

PF0 to PF5

PF6

PF7

6

2

PORT E

6

PORT F

INTERRUPT CONTROLLER

PG0 to PG7

8

PORT G

PH0 to PH7
8

PORT H

FIFO

FRC

CAPTURE UNIT

PRESCALER/

TIME BASE TIMER

PI0 to PI7
8

PORT I

RAM

BUFFER

PJ0 to PJ7

8

PORT J

(CH1)

PATTERN

GENERATOR

PROGRAMMABLE

RAM

BUFFER

11 11 4

(CH0)

PATTERN

GENERATOR

PROGRAMMABLE

2

2

EXI3
to
EXI0

PPO21
to
PPO11

PPO10
to
PPO0

AV

REF

AV

REF

AV

SS

Block Diagram

A/D CONVERTER

UART RECEIVER

GENERATOR

UART BAUD RATE

UART TRANSMITTER

8

TxD

RxD

AN0 to AN7

8 BIT PWM GENERATOR 1

8 BIT PWM GENERATOR 2

8 BIT PWM GENERATOR 3

8 BIT PWM GENERATOR 4

8 BIT PWM GENERATOR 5

8 BIT PWM GENERATOR 6

8 BIT PWM GENERATOR 0

PWM0

PWM1

PWM2

PWM3

PWM4

8 BIT PWM GENERATOR 7

PWM5

PWM6

PWM7

– 2 –

RAM

BUFFER

SERIAL

UNIT (CH0)

INTERFACE

SI0

CS0

SO0

SCK0

RAM

BUFFER

SERIAL

UNIT (CH1)

INTERFACE

SI1

CS1

SO1

(CH2)

8 BIT TIMER 1

SERIAL INTERFACE UNIT

SI2

SCK1

8 BIT TIMER/COUNTER 0

EC0

SO2

SCK2

16 BIT CAPTURE

TIMER/COUNTER 2

TO

EC1

CINT

Pin Assignment (Top View) 100-pin QFP package

PG3/PWM3

PG4/PWM4

PG5/PWM5

PG6/PWM6

PG7/PWM7

PF0

PF1

PF2

NC

PG1/PWM1

PG2/PWM2

DD

V

SS

PG0/PWM0

V

PI6/SI2

PI7/SO2

PI4/INT4

PI5/SCK2

PI2/INT2

PI3/INT3

CXP84716/84720/84724

PF3
PF4
PF5

PF6/TxD

PF7/RxD
PD0/PPO0
PD1/PPO1
PD2/PPO2
PD3/PPO3
PD4/PPO4
PD5/PPO5
PD6/PPO6
PD7/PPO7

PC0
PC1
PC2
PC3
PC4
PC5
PC6

PC7
PH0/PPO8
PH1/PPO9

PH2/PPO10
PH3/PPO11
PH4/PPO12
PH5/PPO13
PH6/PPO14
PH7/PPO15

PJ0/PPO16

10

12
13
14
15
16
17

19

25

30

11

18

20
21
22
23
24

26
27
28
29

100

99

98

1
2
3
4
5
6
7
8
9

32

31

33

97

34

96

35

95

36

94

37

93

38

92

39

91

40

90

41

89

42

88

43

44

87

45

86

85

46

84

47

48

83

82

49

81

50

80

78

75
74
73
72

65

62
61

79

77
76

71
70
69
68
67
66

64
63

60
59
58
57
56
55
54
53
52
51

PI1/INT1
PI0/INT0
PE7/TO
PE6
PE5
PE4
PE3/NMI
PE2
PE1/EC1
PE0/EC0
PB7/SO1
PB6/SI1
PB5/SCK1
PB4/CS1
PB3
PB2
PB1
PB0/CINT
SO0
SI0
SCK0
CS0
PA7
PA6
PA5
PA4
PA3/AN7
PA2/AN6
PA1/AN5
PA0/AN4

RST

PJ7/EXI1

PJ6/EXI0

PJ5/PPO21

PJ4/PPO20

PJ3/PPO19

PJ2/PPO18

PJ1/PPO17

Note) 1. NC (Pin 90) is left open.

2. VSS (Pins 41 and 88) are both connected to GND.

XTAL

EXTAL

– 3 –

EXI2

EXI3

SS

AV

REF

AV

DD

AV

AN0

AN1

AN2

AN3

SS

V

Pin Assignment (Top View) 100-pin LQFP package

PG2/PWM2

PG3/PWM3

PG4/PWM4

PG5/PWM5

PG6/PWM6

PG7/PWM7

PF0

PF1

PF2

PF3

PF4

DD

V

NC

PG1/PWM1

SS

PG0/PWM0

V

PI6/SI2

PI7/SO2

PI4/INT4

PI5/SCK2

PI2/INT2

PI3/INT3

CXP84716/84720/84724

PE7/TO

PI0/INT0

PI1/INT1

PF5

PF6/TxD

PF7/RxD
PD0/PPO0
PD1/PPO1
PD2/PPO2
PD3/PPO3
PD4/PPO4
PD5/PPO5
PD6/PPO6
PD7/PPO7

PC0
PC1
PC2
PC3
PC4
PC5
PC6

PC7
PH0/PPO8
PH1/PPO9

PH2/PPO10
PH3/PPO11
PH4/PPO12
PH5/PPO13

10
11
12
13
14
15
16
17
18
19

21
22

25

20

23
24

100

99

98

1

2
3
4

5
6
7
8
9

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

PE6
PE5
PE4
PE3/NMI
PE2
PE1/EC1
PE0/EC0
PB7/SO1
PB6/SI1
PB5/SCK1
PB4/CS1
PB3
PB2
PB1
PB0/CINT
SO0
SI0
SCK0
CS0
PA7
PA6
PA5
PA4
PA3/AN7
PA2/AN6

27

26

PH7/PPO15

PH6/PPO14

28

29

PJ1/PPO17

PJ0/PPO16

30

31

PJ3/PPO19

PJ2/PPO18

32

PJ4/PPO20

33

34

PJ6/EXI0

PJ5/PPO21

35

PJ7/EXI1

Note) 1. NC (Pin 88) is left open.

2. VSS (Pins 39 and 86) are both connected to GND.

36

37

RST

38

EXTAL

– 4 –

39

XTAL

40

SS

V

EXI2

41

42

EXI3

43

SS

AV

REF

AV

44

DD

AV

45

46

AN0

47

AN1

48

AN2

49

AN3

50

PA1/AN5

PA0/AN4

Pin Description

CXP84716/84720/84724

Symbol I/O

AN0

to

Input

AN3

PA0/AN4

to

I/O/Input

PA3/AN7

PA4 to PA7
PB0/CINT
PB1 to PB3
PB4/CS1
PB5/SCK1

PB6/SI1
PB7/SO1

I/O
I/O/Input
I/O
I/O/Input
I/O/I/O

I/O/Input
I/O/Output

Analog inputs to A/D converter.
(4 pins)

(Port A)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up
resistor can be set through the
software in a unit of 4 bits.
(8 pins)

(Port B)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up resistor
can be set through the
software in a unit of 4 bits.
(8 pins)

Description

Analog inputs to A/D converter.
(4 pins)

External capture input to 16-bit
timer/counter.

Chip select input for serial interface
(CH1).

Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).

PC0 to PC7

PD0/PPO0

to

PD7/PPO7

PE0/EC0
PE1/EC1
PE2
PE3/NMI
PE4 to PE5
PE6

PE7/TO

I/O

I/O/Real-time
output

Input/Input
Input/Input
Input
Input/Input
Input
Output

Output/Output

(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink
current. Incorporation of pull-up resistor can be set through the software in
a unit of 4 bits.
(8 pins)

(Port D)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up resistor
can be set through the software
in a unit of 4 bits.
Data is gated with PPO contents

PPO0 to PPO7 outputs for programmable
pattern generator (PPG0). Functions as
high-precision real-time pulse output port.
(PPG0: 11 pins; PPG1: 11 pins)

by OR-gate and they are output.
(8 pins)

External event inputs for timer/counter.
(2 pins)

(Port E)
8-bit port. Lower 5 bits are for
input; upper 2 bits are for

Non-maskable interruption request.

output.
(8 pins)

Rectangular wave output for 16-bit
timer/counter.

– 5 –

CXP84716/84720/84724

Symbol I/O

PF0 to PF5

PF6/TxD
PF7/RxD

I/O

Output/Output
Input/Input

PG0/PWM0

to

I/O/Output

PG7/PWM7

PH0/PPO8

to

PH7/PPO15

I/O/Real-time
output

Description

(Port F)
Lower 6 bits are for I/O. I/O can be set in a unit of single bits.
Incorporation of pull-up resistor can be set through the software in a unit
of 4 bits (PF0 to PF3) or 2 bits (PF4,PF5)
PF6 is for output; PF7 is for input.
(8 pins)

UART transmission data output.

UART reception data input.

(Port G)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up
resistor can be set through the

PWM outputs.
(8 pins)

software in a unit of 4 bits.
(8 pins)

(Port H)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up resistor
can be set through the software
in a unit of 4 bits.
Data is gated with PPO contents
by OR-gate and they are output.

PPO8 to PPO11 (PPG0) outputs and
PPO12 to PPO15 (PPG1) outputs for
programmable pattern generator (PPG0,
PPG1).
Functions as high-precision real-time pulse
output port.

(8 pins)

PI0/INT0

to

PI4/INT4
PI5/SCK2

PI6/SI2
PI7/SO2

PJ0/PPO16

to

PJ5/PPO21

PJ6/EXI0
PJ7/EXI1

EXI2 to EXI3
CS0

SCK0
SI0

I/O/Input

I/O/I/O
I/O/Input
I/O/Output

I/O/Real-time
output

I/O/Input
I/O/Input

Input
Input

I/O
Input

(Port I)
8-bit I/O port. I/O can be set in

External interruption request inputs.
(5 pins)

a unit of single bits.
Incorporation of pull-up resistor
can be set through the software
in a unit of 4 bits.
(8 pins)

Serial clock I/O (CH2).
Serial data input (CH2).
Serial data output (CH2).

(Port I)
8-bit I/O port. I/O can be set in
a unit of single bits.
Incorporation of pull-up resistor
can be set through the software

PPO16 to PPO21 outputs for
programmable pattern generator (PPG1).
Functions as high-precision real-time

pulse output port.
in a unit of 4 bits.
Data is gated with PPO contents
by OR-gate and they are output.
(8 pins)

External inputs to FRC capture unit.
(2 Pins)

External inputs to FRC capture unit.
(2 pins)

Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).

SO1

I/O/Output

Serial data I/O (CH0).

– 6 –

CXP84716/84720/84724

Symbol

EXTAL
XTAL

RST

NC
AVDD

AVREF
AVSS
VDD
VSS

Input
Output

I/O

Input

I/O

Description

Connects a crystal for system clock oscillation. When a clock is supplied
externally, input it to EXTAL pin and input a reversed phase clock to XTAL
pin.

System reset; active at Low level. This pin is I/O pin, and outputs Low
level at the power on with the power-on reset function is executed. (Mask
option)

Not connected.
Leave this pin open for normal operation.

Positive power supply of A/D converter.
Reference voltage input of A/D converter.
GND of A/D converter.
Positive power supply.
GND.

– 7 –

Data bus

RD (Ports B, I, J)

Ports B, I, J direction

IP

Ports B, I, J data

Pull-up resistor

"0" when reset

"0" when reset

∗

Schmitt input

CINT
CS1
SI1
EXI0
EXI1

∗

Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)

I/O Circuit Format for Pins

CXP84716/84720/84724

Pin

PA0/AN4

to

PA3/AN7

4 pins

PA4 to PA7
PB1 to PB3
PF0 to PF5

Port A

Port A

Port B

Port F

Data bus

Pull-up resistor

"0" when reset

Port A data

Port A direction

"0" when reset

RD (Port A)

Port A function
selection

"0" when reset

Pull-up resistor
"0" when reset

Ports A, B, F data

Ports A, B, F direction

"0" when reset

Circuit format

A/D converter

∗

IP

Input
protection
circuit

Input multiplexer

∗

Pull-up transistors
approx. 100kΩ (V
approx. 300kΩ (VDD = 3.0 to 3.6V)

DD = 4.5 to 5.5V)

∗

IP

When reset

Hi-Z

Hi-Z

13 pins

PB0/CINT
PB4/CS1
PB6/SI1
PI6/SI2
PJ6/EXI0
PJ7/EXI1

6 pins

Port B

Port I

Port J

Data bus

RD (Ports A, B, F)

∗

Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)

Hi-Z

– 8 –

CXP84716/84720/84724

Data bus

RD (Ports B, I)

IP

Ports B, I function
selection

"0" when reset

∗

Schmitt input

SCK in

Ports B, I data

"0" when reset

Pull-up resistor

"0" when reset

SCK OUT

Serial clock output enable

Ports B, I direction

∗

Pull-up transistors

approx. 100kΩ (V

DD = 4.5 to 5.5V)

approx. 300kΩ (VDD = 3.0 to 3.6V)

PB5/SCK1
PI5/SCK2

2 pins

PB7/SO1
PI7/SO2

Port B

Port I

Port B

Port I

"0" when reset

Serial data output enable

Ports B, I function
selection

"0" when reset

Ports B, I direction

"0" when reset

Pull-up resistor

Ports B, I data

SO

Circuit format

When resetPin

Hi-Z

∗

IP

Hi-Z

2 pins

PC0 to PC7

8 pins

Data bus

Port C

RD (Ports B, I)

Pull-up resistor
"0" when reset

Port C direction

"0" when reset

Data bus

Port C data

RD (Port C)

∗

Pull-up transistors
approx. 100kΩ (V
approx. 300kΩ (VDD = 3.0 to 3.6V)

∗

1

Large current
(12mA: VDD = 4.5 to 5.5V)
(5mA: VDD = 3.0 to 3.6V)

∗

2

Pull-up transistors
approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 300kΩ (VDD = 3.0 to 3.6V)

∗

1

DD = 4.5 to 5.5V)

∗

2

IP

Hi-Z

– 9 –

CXP84716/84720/84724

PD0/PPO0

to

PD7/PPO7
PH0/PPO8

to

PH7/PPO15
PJ0/PPO16

to

PJ5/PPO21

22 pins

PE0/EC0
PE1/EC1
PE2
PE3/NMI
PE4
PE5
PF7/RxD

7 pins

Port D
Port H

Port J

Port E
Port F

Pull-up resistor

"0" when reset

Ports D, H, J data

Ports D, H, J direction

"0" when reset

Data bus

RD (Ports D, H, J)

Schmitt input (Inverter input for PE2, PE4, PE5)

IP

Circuit format

PPO data

RD (Ports E, F)

∗

IP

∗

Pull-up transistors
approx. 100kΩ (V
approx. 300kΩ (VDD = 3.0 to 3.6V)

EC0, EC1, NMI, RxD

Data bus

DD = 4.5 to 5.5V)

When resetPin

Hi-Z

Hi-Z

PE6

1 pin

PE7/TO

1 pin

Port E

Port E data

"1" when reset

Data bus

RD (Port E)

Port E

Port E data

"1" when reset

Port E function selection (upper)

Port E function selection (lower)

"00" when reset

00

01

TO

TO output enable

Internal reset signal

MPX

∗

∗

Pull-up transistors
approx. 150kΩ (V
approx. 400kΩ (VDD = 3.0 to 3.6V)

DD = 4.5 to 5.5V)

High level

High level

with the

resistor of pull-

up transistor

(

ON for reset

)

– 10 –

CXP84716/84720/84724

PF6/TxD

1 pin

PG0/PWM0

to

PG7/PWM7

Port F

UART transmission circuit

Transmission control/
port control

"0" when reset

Port F data

"1" when reset

Data bus

Port G

Pull-up resistor

"0" when reset

Port G function
selection

"0" when reset

Port G data

Port G direction
"0" when reset

RD (Port F)

PWM

Circuit format

When resetPin

High level

∗

IP

Hi-Z

8 pins

PI0/INT0

to

PI4/INT4

5 pins

AN0

to

AN3

4 pins

Data bus

Port I

Data bus

RD (Port G)

RD (Port I)

Pull-up resistor

"0" when reset

Port I data

Port I direction

"0" when reset

IP

INT0
INT1
INT2
INT3
INT4

Input multiplexer

∗

Pull-up transistors
approx. 100kΩ (V
approx. 300kΩ (VDD = 3.0 to 3.6V)

IP

Schmitt input

∗

Pull-up transistors
approx. 100kΩ (V
approx. 300kΩ (VDD = 3.0 to 3.6V)

DD = 4.5 to 5.5V)

A/D converter

DD = 4.5 to 5.5V)

∗

Hi-Z

Hi-Z

– 11 –

CXP84716/84720/84724

EXI2
EXI3

2 pins

CS0
SI0

2 pins

SO0

1 pin

SCK0

SO0 from SIO

SO0 output enable

Internal serial clock
from SIO

SCK0 output enable

Circuit format

Schmitt input

IP

Schmitt input

IP

EXI2, EXI3

SIO

When resetPin

Hi-Z

Hi-Z

Hi-Z

IP

Hi-Z

1 pin

EXTAL
XTAL

2 pins

RST

1 pin

EXTAL

XTAL

External serial clock to SIO

IP

Pull-up resistor

Mask option

OP

Schmitt input

IP

IP

From power-on reset circuit
(Mask option)

• Diagram shows the circuit
composition during oscillation.

• Feedback resistor is removed
during stop mode and XTAL
becomes High level.

Schmitt input

Oscillation

Low level

– 12 –

CXP84716/84720/84724

Absolute Maximum Ratings (Vss = 0V reference)

Item Symbol Rating Unit Remarks

VDD
AVDD

–0.3 to +7.0

AVSS to +7.0

∗1

V
V

Supply voltage

AVSS

AVREF
Input voltagte
Output voltage
High level output current

VIN

VOUT

IOH

∑IOH
High level total output current

IOL
Low level output current

Low level total output current
Operating temperature
Storage temperature

Allowable power dissipation

∗1

AVDD and VDD must be set to the same voltage.

∗2

VIN and VOUT must not exceed VDD + 0.3V.

∗3

The large current output pins are Port C (PC).

IOLC

∑IOL

Topr

Tstg

PD

–0.3 to +0.3

AVSS to +7.0
–0.3 to +7.0
–0.3 to +7.0

–5

–50

15
20

100

–20 to +75

–55 to +150

600
380

∗2
∗2

V
V
V

V
mA
mA

mA
mA

mA

°C
°C

mW

Output (value per pin)
Total for all output pins
All pins excluding large current

outputs (value per pin)
Large current outputs (value per pin)

∗3

Total for all output pins

QFP package
LQFP package

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.

– 13 –

CXP84716/84720/84724

Recommended Operating Conditions (Vss = 0V reference)

Item Symbol Min.

Supply voltage

Analog voltage

High level input
voltage

Low level input
voltage

Operating temperature

VDD

AVDD

VIH

VIHS

VIHEX

VIL

VILS

VILEX

Topr

4.5

3.0

2.7

2.7

3.0

0.7VDD

0.8VDD

0.8VDD
VDD – 0.4
VDD – 0.2

0
0

0
–0.3
–0.3

–20

Max. Unit Remarks

5.5

fc = 16MHz or less

V

Guaranteed operation
range for 1/2 and 1/4

5.5

5.5

5.5

5.5
VDD
VDD
VDD

VDD + 0.3
VDD + 0.2

0.3VDD

0.2VDD

0.2VDD

0.4

0.2
+75

fc = 12MHz or less

V

Guaranteed operation range for 1/16

V

frequency dividing clock or sleep mode
Guaranteed data hold operation range

V

during stop mode

∗1

V

∗2, ∗5

V

∗2, ∗6

V

Hysteresis input

V

EXTAL pin

V

EXTAL pin

V

∗2, ∗5

V

∗2, ∗6

V

Hysteresis input

V

EXTAL pin

V

EXTAL pin

V

∗4, ∗5
∗4, ∗6

∗4, ∗5
∗4, ∗6

frequency dividing clock.

∗3

∗

3

°C

∗1

AVDD and VDD must be set to the same voltage.

∗2

Normal input port (PA, PB1 to PB3, PB7, PC, PD, PE2, PE4, PE5, PF0 to PF5, PG, PH, PI7, PJ0 to PJ5)

∗3

RST, CINT, CS0, CS1, SCK0, SCK1, SCK2, SI0, SI1, SI2, EC0, EC1, NMI, RxD, INT0, INT1, INT2, INT3,
INT4, EXI0, EXI1, EXI2 and EXI3

∗4

Specifies only when the external clock is input.

∗5

This case applies to the range of 4.5 to 5.5V supply voltage (VDD).

∗6

This case applies to the range of 3.0 to 5.5V supply voltage (VDD).

– 14 –

CXP84716/84720/84724

Electrical Characteristics
DC Characteristics (VDD = 4.5 to 5.5V)

(Ta = –20 to +75°C, VSS = 0V reference)

Item Symbol Pins Conditions Min. Typ. Max. Unit

High level
output voltage

Low level
output voltage

Input current

I/O leakage
current

VOH

VOL

IIHE
IILE
IIHT
IILT
IILR

IIL

IIZ

PA to PD,
PE6, PE7,
PF0 to PF6,
PG to PJ,
SCK0, SO0

PA to PD,
PE6, PE7,
PF0 to PF6,
PG to PJ,
SCK0, SO0,

∗1

RST
PC

EXTAL

TEX

∗2

RST
PA to PD∗3,

PF0 to PF
PG to PJ

∗3

5∗3,

PA to PD∗3,
PE0 to PE5,
PF0 to PF5∗3,
PF7,
PG to PJ∗3,
CS0, SCK0,
SI0, EXI2,
EXI3,
AN0 to AN3

∗2

RST

VDD = 4.5V, IOH = –0.5mA

VDD = 4.5V, IOH = –1.2mA

VDD = 4.5V, IOL = 1.8mA

VDD = 4.5V, IOL = 3.6mA

VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 5.5V
VDD = 5.5V, VIL = 0.4V

VDD = 5.5V, VIL = 0.4V

VDD = 4.5V, VIL = 4.0V

VDD = 5.5V
VI = 0, 5.5V

4.0

3.5

0.5

–0.5

0.1
–0.1
–1.5

–2.78

0.4

0.6

1.5
40

–40

10

–10

–400

–45

±10

V

V

V

V

V
µA
µA
µA
µA
µA
µA
µA

µA

– 15 –

CXP84716/84720/84724

Item Symbol Pins Conditions Min.

1/2 frequency dividing clock operation

IDD

VDD = 5.5V, 16MHz crystal oscillation
(C1 = C2 = 15pF)

Supply
current

∗4

IDDS1

VDD

Sleep mode

VDD = 5.5V, 16MHz crystal oscillation
(C1 = C2 = 15pF)

Stop mode

IDDS2

VDD = 5.5V, termination of 16MHz
crystal oscillation

PA to PD,
PE0 to PE5,
PF0 to PF5,
PF7,

Input
capacity

CIN

PG to PJ,
CS0, SCK0,
SI0, EXI2,

Clock 1MHz
0V for all pins excluding measured

pins
EXI3,
AN0 to AN3,
EXTAL,
RST

Typ. Max. Unit

17.5

1.4

10

40

8

10

20

mA

mA

µA

pF

∗1

RST pin specifies the output voltage only when the power-on reset circuit is selected with mask option.

∗2

RST pin specifies the input current when the pull-up resistance is selected, and specifies the leakage
current when no resistance is selected.

∗3

PA to PD, PF0 to PF5 and PG to PJ pins specify the input current when the pull-up resistance is selected,
and specify the leakage current when no resistance is selected.

∗4

When all pins are open.

– 16 –

CXP84716/84720/84724

Electrical Characteristics
DC Characteristics (VDD = 3.0 to 3.6V)

(Ta = –20 to +75°C, VSS = 0V reference)

Item Symbol Pins Conditions Min. Typ. Max. Unit

High level
output voltage

Low level
output voltage

Input current

I/O leakage
current

VOH

VOL

IIHE
IILE
IIHT
IILT
IILR

IIL

IIZ

PA to PD,
PE6, PE7,
PF0 to PF6,
PG to PJ,
SCK0, SO0

PA to PD,
PE6, PE7,
PF0 to PF6,
PG to PJ,
SCK0, SO0,

∗1

RST
PC

EXTAL

TEX

∗2

RST
PA to PD∗3,

PF0 to PF
PG to PJ

5∗3,

∗3

PA to PD∗3,
PE0 to PE5,
PF0 to PF5∗3,
PF7,
PG to PJ∗3,
CS0, SCK0,
SI0, EXI2,
EXI3,
AN0 to AN3

∗2

RST

VDD = 3.0V, IOH = –0.15mA

VDD = 3.0V, IOH = –0.5mA

VDD = 3.0V, IOL = 1.2mA

VDD = 3.0V, IOL = 1.6mA

VDD = 3.0V, IOL = 5.0mA
VDD = 3.6V, VIH = 3.6V
VDD = 3.6V, VIL = 0.3V
VDD = 3.6V, VIL = 3.6V
VDD = 3.6V, VIL = 0.4V

VDD = 3.6V, VIL = 0.3V

VDD = 3.0V, VIL = 2.7V

VDD = 3.6V
VI = 0, 3.6V

2.7

2.3

0.3

–0.3

0.1
–0.1
–0.9

–1.0

0.3

0.5

1

20

–20

10

–10

–200

–20

±10

V

V

V

V

V
µA
µA
µA
µA
µA
µA
µA

µA

– 17 –

CXP84716/84720/84724

Item Symbol Pins Conditions Min.

1/2 frequency dividing clock operation

IDD

VDD = 3.6V, 12MHz crystal oscillation
(C1 = C2 = 15pF)

Supply
current

∗4

IDDS1

VDD

Sleep mode

VDD = 3.6V, 12MHz crystal oscillation
(C1 = C2 = 15pF)

Stop mode

IDDS2

VDD = 3.6V, termination of 12MHz
crystal oscillation

PA to PD,
PE0 to PE5,
PF0 to PF5,
PF7,

Input
capacity

CIN

PG to PJ,
CS0, SCK0,
SI0, EXI2,

Clock 1MHz
0V for all pins excluding measured

pins
EXI3,
AN0 to AN3,
EXTAL,
RST

Typ. Max. Unit

6.5

0.5

10

18

2.0

10

20

mA

mA

µA

pF

∗1

RST pin specifies the output voltage only when the power-on reset circuit is selected with mask option.

∗2

RST pin specifies the input current when the pull-up resistance is selected, and specifies the leakage
current when no resistance is selected.

∗3

PA to PD, PF0 to PF5 and PG to PJ pins specify the input current when the pull-up resistance is selected,
and specify the leakage current when no resistance is selected.

∗4

When all pins are open.

– 18 –

A

A

AC Characteristics
(1) Clock timing

CXP84716/84720/84724

(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)

Item Symbol Pin Conditions Min. Unit

System clock frequency

System clock input pulse
width

System clock input
rise time, fall time

Event count input clock
pulse width

Event count input clock
rise time, fall time

∗1

tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock

control register (CLC: 00FEh).

fC

tXL
tXH

tCR
tCF

tEH
tEL

tER
tEF

XTAL
EXTAL

XTAL
EXTAL

XTAL
EXTAL

EC0
EC1

EC0
EC1

Fig. 1, Fig. 2

Fig. 1, Fig. 2
External clock drive

Fig. 1, Fig. 2
External clock drive

Fig. 3

Fig. 3

VDD = 4.5 to 5.5V

DD = 4.5 to 5.5V

V

1
1

28

37.5

tsys + 50

Typ. Max.

16
12

200

∗1

20

tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (Upper two bits = “11”)

Fig. 1. Clock timing

1/fc

MHz

ns

ns

ns

ms

EXTAL

Fig. 2. Clock applied conditions

C

Fig. 3. Event count clock timing

EC0
EC1

XH tXLtCF tCR

t

Crystal oscillation
Ceramic oscillation

EXTAL

AA

1 C2

XTAL

External clock

EXTAL

AA

74HC04

XTAL

DD – 0.4V (VDD = 4.5 to 5.5V)

V

V

DD – 0.3V

0.4V (VDD = 4.5 to 5.5V)

0.3V

0.8VDD

0.2VDD

t

EH tELtEF tER

– 19 –

CXP84716/84720/84724

(2) Serial transfer (CH0, CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Conditions Min. Max. Unit

CS↓ → SCK
delay time

CS↑ → SCK
floating delay time

CS↓ → SO delay time
CS↑ → SO floating

delay time
CS High level width

SCK cycle time

SCK High and Low
level width

SI input setup time
(for SCK↑)

SI input hold time
(for SCK↑)

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH
tKL

tSIK

tKSI

SCK0
SCK1

SCK0
SCK1

SO0
SO1

SO0
SO1

CS0
CS1

SCK0
SCK1

SCK0
SCK1

SI0
SI1

SI0
SI1

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode
Input mode

Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode

tsys + 200

2tsys + 200

8000/fc

tsys + 100

4000/fc – 50

–tsys + 100

200

2tsys + 200

100

1.5tsys + 200

1.5tsys + 200

1.5tsys + 200

1.5tsys + 200

ns

ns

ns

ns

ns
ns

ns
ns
ns
ns
ns
ns
ns

SCK↓ → SO
delay time

Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper

2 bits (CPU clock selection).

tKSO

SO0
SO1

SCK input mode
SCK output mode

2tsys + 200

100

ns
ns

tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)

Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1

and SO1 for CH1, respectively.

Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.

– 20 –

CXP84716/84720/84724

Serial transfer (CH0, CH1) (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)

Item Symbol Pin Conditions Min. Max. Unit

CS↓ → SCK
delay time

CS↑ → SCK
floating delay time

CS↓ → SO delay time
CS↑ → SO floating

delay time
CS High level width

SCK cycle time

SCK High and Low
level widths

SI input setup time
(for SCK↑)

SI input hold time
(for SCK↑)

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH
tKL

tSIK

tKSI

SCK0
SCK1

SCK0
SCK1

SO0
SO1

SO0
SO1

CS0
CS1

SCK0
SCK1

SCK0
SCK1

SI0
SI1

SI0
SI1

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode
Input mode

Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode

tsys + 200

2tsys + 200

8000/fc

tsys + 100

4000/fc – 100

–tsys + 100

200

2tsys + 200

100

1.5tsys + 250

1.5tsys + 200

1.5tsys + 250

1.5tsys + 200

ns

ns

ns

ns

ns
ns

ns
ns
ns
ns
ns
ns
ns

SCK↓ → SO
delay time

Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper

2 bits (CPU clock selection).

tKSO

SO0
SO1

SCK input mode
SCK output mode

2tsys + 250

125

ns
ns

tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)

Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1

and SO1 for CH1, respectively.

Note 3) The load of SCK output mode and SO output delay time is 50pF.

– 21 –

Fig. 4. Serial transfer CH0, CH1 timing

CXP84716/84720/84724

tWHCS

CS0
CS1

SCK0
SCK1

0.2VDD

tKCY

tDCSK tDCSKF

tKL tKH

0.8VDD

0.2VDD

SIK

t

tKSI

0.8VDD

0.8VDD

SI0
SI1

SO0
SO1

0.8VDD

Input data

0.2VDD

t

DCSO tKSO tDCSOF

Output data

0.8V

DD

0.2VDD

– 22 –

CXP84716/84720/84724

Serial transfer (CH2) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Min. Max. UnitConditions

SCK cycle time

SCK High and Low
level widths

SI input setup time
(for SCK↑)

SI input hold time
(for SCK↑)

SCK↓ → SO delay time

Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2

bits (CPU clock selection).

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK2

SCK2

SI2

SI2

SO2

Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode

1000

8000/fc

400

4000/fc – 50

100
200
200
100

200
100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01’), 16000/fc (Upper 2 bits = “11”)

Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively.
Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF+1TTL.

Serial transfer (CH2) (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference)

Item Symbol Pin Min. Max. UnitConditions

SCK cycle time

SCK High and Low
level widths

SI input setup time
(for SCK↑)

SI input hold time
(for SCK↑)

SCK↓ → SO delay time

Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2

bits (CPU clock selection).

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK2

SCK2

SI2

SI2

SO2

Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode

1000

8000/fc

400

4000/fc – 100

100
200
200
100

250
125

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01’), 16000/fc (Upper 2 bits = “11”)

Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively.
Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF.

– 23 –

Fig. 5. Serial transfer CH2 timing

SCK2

CXP84716/84720/84724

tKCY

tKL tKH

0.8VDD

0.2VDD

tSIK tKSI

0.8VDD

SI2

SO2

tKSO

Input data

0.8VDD

0.2VDD

0.2V

Output data

DD

– 24 –

CXP84716/84720/84724

(3) A/D converter characteristics (Ta = –20 to +75°C, VDD = AVDD = 3.0 to 5.5V, Vss = AVSS = 0V reference)

Item Symbol Pin Conditions Min. Typ. Max. Unit

Resolution
Linearity errror

Zero
transition voltage

Full-scale transition
voltage

Linearity errror
Zero

transition voltage
Full-scale transition

voltage
Convertion time

Sampling time
Reference input

voltage
Analog input voltage

AVREF current

VZT

VFT

VZT

VFT

tCONV
tSAMP

VREF

VIAN

IREF

IREFS

∗1

∗2

∗1

∗2

AVREF

AN0 to AN7

AVREF

Ta = 25°C
VDD = AVDD = AVREF
= 5.0V
VSS = AVSS = 0V

Ta = 25°C
VDD = AVDD = AVREF
= 3.3V
VSS = AVSS = 0V

VDD = AVDD = 4.5 to 5.5V
VDD = AVDD = 3.0 to 3.6V

Operation
mode

VDD = 5.5V
VDD = 3.6V

Sleep mode
Stop mode

8

±3 LSB

–10

4910 mV

10

4970

70 mV

5030

±5

–10

3215

6/fADC

∗3

∗3

26/fADC

AVDD – 0.5
AVDD – 0.3

0

6.5

3280

0.6

0.4

70

3345

AVDD
AVDD

AVREF

1.0

0.7
10

Bits

LSB

mV

mV

µs
µs

V
V

V

mA

mA

µA

Fig.6. Definition of A/D converter terms

FFh
FEh

Digital conversion value

01h
00h

Linearity error

Analog input

∗1

VZT:Value at which the digital conversion value changes

from 00h to 01h and vice versa.

∗2

VFT:Value at which the digital conversion value changes

from FEh to FFh and vice versa.

∗3

fADC indicates the below values due to the contents of bit
6 (CKS) of the A/D control register (ADC: 00F9h).

PS1 selected fADC = fc
PS2 selected fADC = fc/2

V

FTVZT

– 25 –

CXP84716/84720/84724

(4) Interruption, reset input

(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference)

Item Symbol Pin Conditions Min. Max. Unit

External interruption
High, Low level width

Reset input Low level width

Fig. 7. Interruption input timing

INT0
INT1
INT2
INT3
INT4
NMI
(NMI is specified only for
the falling edge)

tIH
tIL

tRSL

INT0
INT1
INT2
INT3
INT4
NMI

RST

tIH tIL

0.8VDD

tIL tIH

1

32/fc

µs

µs

0.2VDD

Fig. 8. RST input timing

tRSL

RST

(5) Power-on reset

∗1

0.2VDD

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference)

Item Symbol Pin Conditions Min. Max. Unit
Power supply rise time
Power supply cut-off time

∗1

Specifies only when the power-on reset function is selected.

tR
tOFF

VDD

Power-on reset
Repetitive power-on reset

Power-on reset function can be selected only for the supply voltage range of 4.5 to 5.5V.

Fig. 9. Power-on reset

4.5V

VDD

0.2V

0.2V

0.05
1

50 ms

ms

tR tOFF

Turn the power on smoothly.

– 26 –

A

Appendix

Fig. 10. Recommended oscillation circuit

(i) Main clock

CXP84716/84720/84724

EXTAL

AA

C

1

Manufacture Model fc (MHz) C1 (pF) C2 (pF) Rd (Ω)

RIVER
ELETEC
co., LTD.

KINSEKI LTD.

Mask Option Table

XTAL

Rd

C2

HC-49/U03

HC-49/U (-S)

8.00

10.00

12.00

16.00

8.00

10.00

12.00

16.00

10

5

22 (15)

15
12

10

5

22 (15)

15
12

0

0

Circuit
example

(i)

(i)

Item Content
Reset pin pull-up resistor
Power-on-reset circuit

∗1

Power-on-reset circuit can not be selected when the supply voltage (VDD) ranges from 3.5 to 4.5V.

∗1

Non-existent
Non-existent

Existent
Existent

– 27 –

Characteristics Curve

CXP84716/84720/84724

(fc = 16MHz, Ta = 25°C, Typical)

20.0

10.0

5.0

1.0

0.5

– Supply current [mA]

DD

I

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

3

VDD – Supply voltage [V]

IDD vs. VDD

45

1/2 dividing mode
1/4 dividing mode

1/16 dividing mode

Sleep mode

Stop mode

6

20

(VDD = 5V, Ta = 25°C, Typical)

15

10

– Supply current [mA]

DD

I

5

0

510 16

fc – System clock [MHz]

IDD vs. fc

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

Sleep mode

(fc = 12MHz, Ta = 25°C, Typical)

20.0

10.0

5.0

1.0

0.5

– Supply current [mA]

DD

I

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

3

DD – Supply voltage [V]

V

IDD vs. VDD

45

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

Sleep mode

6

(VDD = 3.3V, Ta = 25°C, Typical)

20

15

10

– Supply current [mA]

DD

I

5

0

1

51015

fc – System clock [MHz]

IDD vs. fc

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode
Sleep mode

– 28 –

CXP84716/84720/84724

Package Outline Unit: mm

0.65

0° to 15°

100PIN QFP (PLASTIC)

23.9 ± 0.4
+ 0.4

20.0 – 0.1

±0.12

M

0.15

(16.3)

DETAIL A

0.8 ± 0.2

+ 0.4

17.9 ± 0.4

14.0 – 0.01

+ 0.1

0.15 – 0.05

15.8 ± 0.4

A

+ 0.35

2.75 – 0.15

SONY CODE
EIAJ CODE

JEDEC CODE

76

100

0.5 ± 0.08

PACKAGE STRUCTURE

QFP-100P-L01
∗QFP100-P-1420-A

PACKAGE MATERIAL
LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN
SOLDER PLATING

COPPER / 42 ALLOY

1.4g

100PIN LQFP (PLASTIC)

16.0 ± 0.2

∗ 14.0 ± 0.1

75

1

+ 0.08

0.18 – 0.03

0.1 ± 0.1

51

50

(15.0)

A

26

(0.22)

25

+ 0.2

1.5 – 0.1

+ 0.05

0.127 – 0.02

0.5 ± 0.2

0.1

SONY CODE
EIAJ CODE
JEDEC CODE

0° to 10°

DETAIL A

LQFP-100P-L01

∗QFP100-P-1414-A

NOTE: Dimension “∗” does not include mold protrusion.

0.5 ± 0.2

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY/PHENOL RESIN
SOLDER PLATING
42 ALLOY

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