Datasheet CXP84416, CXP84412 Datasheet (Sony)

CXP84412/84416

CMOS 8-bit Single Chip Microcomputer

Description

The CXP84412/84416 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, 32kHz timer/counter, remote control reception circuit and other servo systems besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port.

The CXP84412/84416 also provides and a sleep/ stop function that enables lower power consumption.

Features

• Wide-range instruction system (213 instructions) to cover various types of data.

— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions

• Minimum instruction cycle 400ns at 10MHz operation

122µs at 32kHz operation

• Incorporated ROM capacity 12Kbytes (CXP84412)

16Kbytes (CXP84416)

• Incorporated RAM capacity 448bytes

• Peripheral functions

— A/D converter 8-bit, 8-channel, successive approximation method

(Conversion time of 32µs/10MHz)

— Serial interface Incorporated 8-bit, 8-stage FIFO

(Auto transfer for 1 to 8 bytes), 2 channel

— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer,

32kHz timer/counter — Remote control reception circuit Incorporated 6-stage FIFO 8-bit measurement counter — PWM output for tuner 14 bits

• Interruption 12 factors, 12 vectors, multi-interruption possible

• Standby mode SLEEP/STOP

• Package 80-pin plastic QFP

• Piggyback/evaluation chip CXP84400 80-pin ceramic QFP

80 pin QFP (PIastic)

Structure

Silicon gate CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E93909-ST

CXP84412/84416

Vss V

DD

RST

XTAL EXTAL TX TEX

PE3/NMI PI3/INT3

PI2/INT2 PI1/INT1 PI0/INT0

PA0 to PA7

8

PORT A

PB0 to PB7

8

PORT B

CLOCK GEN./

SYSTEM CONTROL

SPC700

CPU CORE

PC0 to PC7

8

PORT C

RAM

ROM

PE0 to PE3

PE4 to PE5

2

PF0 to PF7

8

PORT F

PD0 to PD7

4

8

PORT DPORT E

32kHz

448 BYTES

12K/16K BYTES

PRESCALER/

INTERRUPT CONTROLLER

2

PG0 to PG7

8

PH0 to PH7

8

PORT GPORT HPORT I

TIMER/COUNTER

TIME BASE TIMER

PI0 to PI7

8

REF

Block Diagram

AV

AVss

A/D CONVERTER

14 BIT PWM GENERATOR

8

AN0 to AN7

PE4/PWM

FIFO

REMOCON

PE2/RMC

PB1/CS0

SERIAL

PB3/SI0

PB4/SO0

PB2/SCK0

FIFO

UNIT 0

INTERFACE

PB6/SI1

PB7/SO1

PB0/CS1

PB5/SCK1

2

8 BIT TIMER 1

8 BIT TIMER/COUNTER 0

PE0/EC

PE5/TO

PE5/ADJ

– 2 –

Pin Assignment (Top View)

CXP84412/84416

PF3 PF4 PF5 PF6

PF7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0 PH1 PH2

10 11 12 13 14 15 16 17 18 19

20 21 22 23

24

80

PF2

79

PF1

78

PF0

77

PG7

76

PG6

75

PG5

74

PG4

73

NC

72

DD

V

71

PG3

PG2

70

69

PG1

68

PG0

67

1

2 3 4

5 6 7 8 9

PI7

66

PI6

65

PI5

60 59 58

64 63 62 61

57 56 55 54 53 52 51 50 49 48 47 46 45 44

42 41

43

PI4 PI3/INT3 PI2/INT2 PI1/INT1 PI0/INT0 PE5/TO/ADJ PE4/PWM PE3/NMI PE2/RMC PE1 PE0/EC PB7/SO1 PB6/SI1 PB5/SCK1 PB4/SO0 PB3/SI0 PB2/SCK0 PB1/CS0 PB0/CS1 PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3

25

PH3

26

PH4

27 28

PH5

PH6

29

PH7

30

RST

31

EXTAL

32

XTAL

33

SS

V

34

TX

35

36

TEX

Note) NC (Pin 73) must be connected to VDD.

– 3 –

SS

AV

37

38

REF

AV

40

39

PA1/AN1

PA0/AN0

PA2/AN2

Pin Description

Pin code I/O Functions

(Port A) 8-bit I/O port. I/O can be

PA0/AN0

to

PA7/AN7

I/O/analog input

set in single bit units. Incorporation of the pull-up resistance can be set through the software

Analog inputs to A/D converter. (8 pins)

in a unit of 4 bits. (8 pins)

CXP84412/84416

PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1

PE0/EC PE1 PE2/RMC PE3/NMI PE4/PWM

PE5/TO/ADJ

I/O/input I/O/input I/O/I/O I/O/input I/O/output I/O/input/output I/O/input I/O/output

I/OPC0 to PC7

I/OPD0 to PD7

Input/input Input Input/input Input/input Output/output

Output/output/ output

I/OPF0 to PF7

Chip select input for serial interface (CH1).

(Port B) 8-bit I/O port. I/O can be set in single bit units. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins)

Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1).

(Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins)

(Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins)

External event inputs for timer/counter.

(Port E) 6-bit port. Lower 4 bits are for inputs; upper 2 bits are for outputs.

Remote control reception circuit input. Non-maskable interruption request input.

Incorporation of pull-up resistor can be set through the software. (8 pins)

14-bit PWM output. Rectangular wave output for 16-bit timer/

counter (duty output 50%). Output for 32kHz oscillation frequency demultiplication.

(Port F) 8-bit output port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins)

– 4 –

Pin code I/O Functions

(Port G)

I/OPG0 to PG7

8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins)

(Port H)

I/OPH0 to PH7

8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins)

CXP84412/84416

PI0/INT0

to

PI3/INT3 PI4 to PI7

EXTAL

TEX

RST NC AVREF AVss VDD Vss

I/O/input

I/O Input OutputXTAL

Input OutputTX Input

Input

(Port I) 8-bit output ports. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set

External interruption request inputs.

through the software in a unit of 4 bits. (8 pins)

Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL.

Crystal connectors for 32kHz timer/counter clock generation circuit. Connect a 32.768kHz crystal oscillator between TEX and TX. For usage as event input, connect clock oscillation source to TEX, and open TX.

Low-level active, system reset. NC. Under normal operating conditions, connect to VDD. Reference voltage input for A/D converter.

A/D converter GND. Vcc supply. GND

– 5 –

Data bus

RD (Port B)

IP

Port B output selection

"0" when reset

∗

Schmitt input

SCK0 in

Port B data

Port B direction

"0" when reset

SCK OUT

Output enable

∗

Pull-up transistors

approx. 100kΩ

Pull-up resistance

SCK1

I/O Circuit Format for Pins

CXP84412/84416

PA0/AN0

to

PA7/AN7

8 pins

PB0/CS1 PB1/CS0 PB3/SI0 PB6/SI1

Port A

Port B

Data bus

Pull-up resistance

"0" when reset

Port A data

Port A direction

"0" when reset

RD (Port A)

Port A input selection

"0" when reset

Pull-up resistance

"0" when reset

Port B data

Port B direction

"0" when reset

Circuit format

A/D converter

Input multiplexer

Schmitt input

∗

Input protection

IP

circuit

∗

Pull-up transistors

approx. 100kΩ

∗

IP

When reset

Hi-Z

4 pins

PB2/SCK0 PB5/SCK1

2 pins

Port B

RD (Port B)

CS1 CS0 SI0 SI1

∗

Pull-up transistors

approx. 100kΩ

Hi-Z

– 6 –

CXP84412/84416

PB4/SO0 PB7/SO1

2 pins

Port B

Data bus

Port C

Pull-up resistance

Output enable

Port B output selection

"0" at reset

Port B data

Port B direction

"0" when reset

RD (Port B)

Pull-up resistance

"0" when reset

Port C data

SO

Circuit format

∗

IP

∗

Pull-up transistors

approx. 100kΩ

∗

2

When reset

Hi-Z

PC0 to PC7

8 pins

PE0/EC PE1 PE2/RMC PE3/NMI

4 pins

PE4/PWM

1 pin

Port E

Data bus

Port C direction

"0" when reset

RD (Port C)

Schmitt input

IP

Note : PE1 No schmitt input.

PWM

Port E output selection

"0" when reset

Port E data

"1" when reset

RD (Port E)

∗

1

High current drive

of 12mA possible

RD (Port E)

∗

1

IP

∗

2

Pull-up transistors

approx. 100kΩ

EC RMC/NMI

Data bus

Hi-Z

H level

– 7 –

CXP84412/84416

PE5/TO/ADJ

1 pin

PD0 to PD7 PF0 to PF7 PG0 to PG7 PH0 to PH7 PI4 to PI7

Port E

Port D Port F

Port G

Port H

Port I

Output enable

Data bus

TO

ADJ16K

ADJ2K

Port E output selection

"00" when reset

Port E output selection

"0" when reset

Port E data

"1" when reset

MPX

RD (Port B)

Pull-up resistance

"0" when reset

Port data

Port direction

"0" when reset

Circuit format

∗

ADJ signals are frequency division outputs for 32kHz oscillation frequency adjustment ADJ2K provides usage as buzzer output.

When reset

H level

∗

IP

Hi-Z

36 pins

PI0/INT0

to

PI3/INT3

4 pins

Port I

Data bus

RD

Pull-up resistance

"0" when reset

Port data

Port direction

"0" when reset

RD

INT0 INT1 INT2 INT3

∗

Pull-up transistors

approx. 100kΩ

∗

IP

Schmitt input

∗

Pull-up transistors

approx. 100kΩ

Hi-Z

– 8 –

CXP84412/84416

A

EXTAL XTAL

2 pins

TEX TX

2 pins

RST

1 pin

EXTAL

XTAL

TEX

TX

Circuit format

IP

Pull-up resistor

OP

• Diagram shows circuit

IP

• When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and TEX and TX become "Low" level and "High" level respectively.

Mask option

IP

composition during oscillation.

• Feedback resistor is removed during stop, and XTAL becomes "High".

• Digram shows circuit circuit composition during oscillation.

Schmitt input

When reset

Oscillation

Hi-z or

L level

(When pull-up

resistance is

added)

– 9 –

CXP84412/84416

Absolute Maximum Ratings (Vss = 0V reference)

Item Symbol Ratings Unit Remarks

VDD

–0.3 to +7.0

V

Supply voltage

Input voltage Output voltage High level output current High level total output current

AVSS VIN VOUT IOH ∑IOH IOL

–0.3 to +0.3 –0.3 to +7.0 –0.3 to +7.0

–5

–50

15

∗1 ∗1

V V V

mA

Output per pin

mA

Total for all output pins

mA

Value per pin, excluding high current outputs

Low level output current

IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation

∗1

VIN and VOUT must not exceed VDD + 0.3V.

∗2

The high current drive transistor is the N-ch transistor of Port C (PC)

∑IOL

Topr

Tstg

PD

20

100

–20 to +75

–55 to +150

600

mA

Value per pin∗2for high current outputs

mA

Total for all output pins °C °C

mW

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.

Recommended Operating Conditions (Vss = 0V reference)

Item Symbol Min. Max. Unit Remarks

4.5

Supply voltage

VDD

3.5

2.7

2.5

VIH

High level input voltage

VIHS VIHEX VIL

Low level input voltage

VILS VILEX

Operating temperature

∗1

High speed mode is 1/2 frequency demultiplication clock selection; low-speed mode is 1/16 frequency

Topr

0.7VDD

0.8VDD

VDD – 0.4

0 0

–0.3

–20

5.5

5.5 VDD VDD

VDD + 0.3

0.3VDD

0.2VDD

0.4 +75

High speed mode guaranteed operation range Low speed mode guaranteed operation range

V

Guaranteed operation range with TEX clock Guaranteed data hold range during STOP

∗

2

V

Hysteresis input

V

EXTAL

V

∗2

V

Hysteresis input

V

EXTAL

V

∗4

∗3

°C

∗1

demultiplication clock selection.

∗2

Value for each pin of normal input ports (PA, PB4, PB7, PC, PD, PE1, PF to PH, PI4 to PI7).

∗3

Value of the following pins: RST, CS0, CS1, SCK0, SCK1, SI0, SI1, EC, RMC, NMI, INT0, INT1, INT2, INT3.

∗4

Specifies only during external clock input.

– 10 –

Electrical Characteristics DC Characteristics

CXP84412/84416

(Ta = –20 to +75°C, Vss = 0V reference)

Item Symbol Pins Conditions Min.

High level output current

VOH

PA to PD,

VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA

PE4, PE5,

VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V

Low level output current

PF to PI

VOL

PC

IIHE

EXTAL

VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 5.5V

VDD = 5.5V, VIL = 0.4V

∗2

VDD = 4.5V, VIL = 4.0V

Input current

IILE IIHT IILT IILR

IIL

TEX

∗1

RST PA to PD∗2,

PF to PI

PE0 to PE3,

I/O leakage current

IIZ

∗1

RST PA to PD∗2, PF to PI

∗2

VDD = 5.5V, VI = 0, 5.5V

High-speed mode operation (1/2 frequency demultiplier clock)

IDD1

VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF)

IDD2

VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF)

4.0

3.5

0.5

–0.5

0.1 –0.1 –1.5

–3.3

Typ.

18

35

Max.

0.4

0.6

1.5 40

–40

10

–10

–400

–5.0

±10

40

100

Unit

V V V V

V µA µA µA µA µA µA µA

µA

mA

µA

Power supply current

∗3

IDDS1

VDD

SLEEP mode

VDD = 5.5V, 10MHz crystal oscillation

1.1

8

(C1 = C2 = 15pF)

IDDS2

VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF)

9

30

STOP mode

IDDS3

VDD = 5.5V, 10MHz crystal oscillation;

10

and termination of 32kHz oscillation

Pins other

Input capacity

CIN

than PE4, PE5, XTAL, TX, AVREF, AVss, VDD,

Clock 1MHz 0V for all pins excluding measured pins

10

20

VSS

∗1

RST specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected.

∗2

Pins PA to PD, and PF to PI specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected.

∗3

When all pins are open.

mA

µA

pF

– 11 –

A

AC Characteristics (1) Clock timing

CXP84412/84416

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Conditions Min. Unit

System clock frequency

System clock input pulse width System clock input

rise time, fall time Event count input clock

pulse width Event count input clock

rise time, fall time

System clock frequency

Event count input clock input pulse width

Event count input clock rise time, fall time

∗

tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control

clock register (address: 00FEH).

fC

tXL, tXH

tCR, tCF

tEH, tEL

tER, tEF

fC

tTL, tTH

tTR, tTF

XTAL EXTAL

EXTAL

EC

TEX TX

TEX

Fig. 1, Fig. 2 Fig. 1, Fig. 2

External clock drive Fig. 1, Fig. 2

External clock drive Fig. 3

Fig. 3 VDD=2.7 to 5.5V

Fig. 2 (32kHz clock application condition)

Fig. 3

1

37.5

tsys + 50

10

∗

32.768

Typ.

Max.

10

200

20

MHz

kHz

tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

ns

ms

µs

ms

Fig. 1. Clock timing

EXTAL

Fig. 2. Clock application conditions

Crystal oscillation Ceramic oscillation

EXTAL

AA

C

1 C2

XTAL

1/fc

tXH tXLtCF tCR

32kHz clock application condition

External clock

EXTAL

AA

74HCO4

XTAL

Crystal oscillation

TEX

AA

C

1

TX

DD – 0.4V

V

0.4V

C2

– 12 –

Fig. 3. Event count clock timing

CXP84412/84416

TEX EC

(2) Serial transfer

Item

CS0 ↓→SCK0 (CS1 ↓→SCK1) delay time

CS0 ↑→SCK0 (CS1 ↑→SCK1) float delay time

CS0 ↓→SO0 (CS1 ↓→SO1) delay time

CS0 ↑→SO0 (CS1 ↑→SO1) float delay time

CS0 (CS1) High level width

SCK0 (SCK1) cycle time

SCK0 (SCK1) High, Low level width

SI0 (SI1) input set-up time (for SCK0 ↑ (SCK1 ↑) )

SI0 (SI1) input hold time

(for SCK0 ↑ (SCK1 ↑) )

SCK0 ↓→SO0 (SCK1 ↓→SO1) delay time

0.8VDD

0.2VDD

EH tELtEF tER

t tTH tTLtTF tTR

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss reference)

Symbol Pin Min.

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH tKL

tSIK

tKSI

tKSO

SCK0 (SCK1)

SO0 (SO1)

CS0 (CS1)

SCK0 (SCK1)

SI0 (SI1)

SO0 (SO1)

Chip select transfer mode (SCK0 (SCK1) = output mode)

Chip select transfer mode

Chip select transfer mode Input mode

Output mode Input mode Output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode

Condition

tsys + 200

2tsys + 200

16000/fc

tsys + 100

8000/fc – 50

100 200

tsys + 200

100

Max. Unit

1.5tsys + 200

1.5tsys +200

1.5tsys + 200

tsys + 200

100

ns

ns ns

ns ns ns ns ns ns ns ns ns

Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the

control clock register (address: 00FEH).

tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL.

– 13 –

Fig. 4. Serial transfer CH0 timing

CS0 (CS1)

0.2V

DD

CXP84412/84416

tWHCS

0.8VDD

tKCY

SCK0 (SCK1)

SI0 (SI1)

tDCSK tDCSKF

tKL tKH

0.8VDD

0.2VDD

tKSI

SIK

t

0.8VDD

Input data

0.2VDD

0.8VDD

SO0 (SO1)

DCSO tKSO tDCSOF

t

Output data

– 14 –

DD

0.8V

0.2VDD

CXP84412/84416

(3) A/D converter characteristics

Item Symbol Pin Condition Min. Typ. Max. Unit

Resolution Linearity error

∗1

Zero transition voltage Full-scale transition

voltage Conversion time Sampling time Reference input voltage Analog input voltage

VZT

∗2

VFT

tCONV tSAMP

VREF VIAN IREF

AVREF current

IREFS

AVREF AN0 to AN7

AVREF

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V

Ta = 25°C VDD = 5.0V

–10

30

8

±3 70 mV

Bits

LSB

VSS = AVSS = 0V

5010

VDD

AVREF

1.0

µs µs

V V

mA

Operation mode

4930 mV

160/fADC

12/fADC

4970

∗3

VDD – 0.5

0

0.6

SLEEP mode STOP mode

10 µA

32kHz operation mode

Fig. 5. Definition of A/D converter terms

FFH FEH

Digital conversion value

01H 00H

Linearity error

Analog input

FTVZT

V

∗

1

VZT : Value at which the digital transfer value changes from

00H to 01H and vice versa.

∗

2

VFT : Value at which the digital transfer value changes from

FEH to FFH and vice versa.

∗

3

fADC indicates the below values due to the contents of bit 6 (CKS) of A/D control resistor (address : 00F9H) and bits 6, 7 (PCK0, 1) of clock control resistor (address : 00FFH).

CKS

PCK 1, 0 00 (φ = fEX/2) 01 (φ = fEX/4) 11 (φ = fEX/16)

0 (φ/2 selection)

fADC = fC/2 fADC = fC/4 fADC = fC/16

1 (φ selection)

fADC = fC fADC = fC/2 fADC = fC/8

– 15 –

(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Max. Unit

INT0

External interruption High, Low level width

tIH tIL

INT1 INT2 INT3

1

µs

NMI

CXP84412/84416

Reset input Low level width

Fig 6. Interruption input timing

INT0 INT1 INT2 INT3 NMI (NMI specifies only for the falling edge)

Fig. 7. RST input timing

tRSL

RST

tIH tIL

0.8VDD

tIL tIH

tRSL

32/fc

µs

0.2VDD

RST

0.2VDD

– 16 –

Appendix

A

Fig. 8. Recommended oscillation circuit

CXP84412/84416

(i) Main clock

EXTAL

AA

C1

Manufacturer

MURATA MFG CO., LTD.

FUJI SANGYO CO., LTD.

KINSEKI LTD.

XTAL

Rd

2

C

Model

CSA4.19MG CSA8.00MTZ CSA10.0MTZ CST4.19MGW CST8.00MTW CST10.0MTW

HC-49/U03

HC-49/U (-S)

P3

(ii) Main clock

∗ ∗ ∗

EXTAL

AA

C

1 C2

fc (MHz)

4.19

8.00

10.00

4.19

8.00

10.00

4.19

8.00

10.00

4.19

8.00

10.00

32.768kHz

(iii) Sub clock

EXTAL

XTAL

Rd

C1 (pF) C2 (pF)

30

12

27

20 20 50 22 1M (iii)

30

12

27

TEX

AAA

C

1

Rd (Ω)

0

XTAL

TX

Rd

C2

Circuit

example

(i)

(ii)

(i)

Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2).

Mask option table

Item

Reset pin pull-up resistance

Content

No Yes

– 17 –

Characteristics Curve

CXP84412/84416

IDD vs. V DD

(fc = 10M Hz, Ta = 25° C , Typical)

20.0

10.0

5.0

1.0

0.5

– Supply current [mA]

DD

I

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

3

45

VDD – Supply voltage [V]

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

SLEEP mode

32kHz mode (instruction)

32kHz SLEEP mode

72

6

– Supply current [mA]

DD

I

IDD vs. fc

(V

DD = 5V, Ta = 25°C , Typical)

20

15

10

5

0

5101

fc – S yst em clock [MHz]

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode SLEEP mode

5

– 18 –

Package Outline Unit: mm

CXP84412/84416

80PIN QFP (PLASTIC)

23.9 ± 0.4 + 0.4

20.0 – 0.1

64

65

41

40

+ 0.4

17.9 ± 0.4

14.0 – 0.1

+ 0.1

0.15 – 0.05

0.15

16.3

A

80

1

0.8

0.12

M

24

0.35 – 0.1

25

+ 0.15

+ 0.35

2.75 – 0.15

+ 0.2

0.1 – 0.05

0.8 ± 0.2

SONY CODE EIAJ CODE JEDEC CODE

0° to 10°

DETAIL A

QFP-80P-L01

∗QFP080-P-1420-A

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT

EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY

1.6g

– 19 –