Page 1
Description
CXP84332M/84340M is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, capture timer/counter, remote control reception
circuit, PWM output, and 32kHz timer/counter besides
the basic configurations of 8-bit CPU, ROM, RAM,
and I/O port.
The CXP84332M/84340M also provides a sleep/stop
function that enables lower power consumption.
Features
• Wide-range instruction system (213 instructions) to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle 200ns at 20MHz operation
122µs at 32kHz operation
• Incorporated ROM capacity 32K bytes (CXP84332M)
40K bytes (CXP84340M)
• Incorporated RAM capacity 1120 bytes
• Peripheral functions
— A/D converter 8 bits, 8 channels, successive approximation method
(Conversion time of 16µs/20MHz)
— Serial interface 8-bit, 8-stage FIFO incorporated
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock synchronization, 1 channel
— Timers 8-bit timer
8-bit timer/counter
19-bit time base timer
16-bit capture timer/counter
32kHz timer/counter
— Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO
— PWM output 14 bits, 1 channel
• Interruption 15 factors, 15 vectors, multi-interruption possible
• Standby mode SLEEP/STOP
• Package 80-pin plastic QFP
• Piggyback/evaluation chip CXP84300 80-pin ceramic QFP
Structure
Silicon gate CMOS IC
– 1 –
CXP84332M/84340M
E95X06-ST
CMOS 8-bit Single Chip Microcomputer
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
80 pin QFP (Plastic)
Page 2
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CXP84332M/84340M
8
2
AN0 to AN7
PWM
RMC
CS0
SI0
SO0
SCK0
SI1
SO1
SCK1
TO
CINT
EC1
EC0
A/D CONVERTER
AVss
AV
REF
14 BIT PWM GENERATOR
REMOCON
FIFO
SERIAL
INTERFACE
UNIT 0
FIFO
SERIAL INTERFACE UNIT 1
8 BIT TIMER/COUNTER 0
8 BIT TIMER 1
16 BIT CAPTURE
TIMER/COUNTER2
INTERRUPT CONTROLLER
INT0
INT1
INT2
INT3
NMI
SPC700
CPU CORE
ROM
32K/40K BYTES
CLOCK
GENERATOR/
SYSTEM CONTROL
RAM
1120 BYTES
PRESCALER/
TIME BASE TIMER
EXTAL
XTAL
V
DD
Vss
PORT A
7
8
8
4
2
8
PA0 to PA7
PB0 to PB6
PB7
PC0 to PC7
PD0 to PD7
PE0 to PE3
PE4 to PE5
PF0 to PF7
PG0 to PG7
PI0 to PI7
RST
8
8
8
PORT B
PORT C
PORT D
PORT E
PORT F
PORT G
PORT I
TEX
TX
PH0 to PH7
8
PORT H
32kHz
TIMER/COUNTER
ADJ
2
2
Block Diagram
Page 3
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CXP84332M/84340M
Pin Assignment (Top View)
PF3
PF4
PF5
PF6
PF7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PH0
PH1
PH2
PI4
PI3/INT3
PI2/INT2
PI1/INT1
PI0/INT0
PE5/TO/ADJ
PE4/PWM
PE3/NMI
PE2/RMC
PE1/EC1
PE0/EC0
PB7/SO1
PB6/SI1
PB5/SCK1
PB4/SO0
PB3/SI0
PB2/SCK0
PB1/CS0
PB0/CINT
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
PH3
PH4
PH5
PH6
PH7
RST
EXTAL
XTAL
V
SS
TX
TEX
AV
SS
AV
REF
PA0/AN0
PA1/AN1
PA2/AN2
PF2
PF1
PF0
PG7
PG6
PG5
PG4
NC
V
DD
PG3
PG2
PG1
PG0
PI7
PI6
PI5
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
73
74
75
76
77
78
79
80
1
Note) NC (Pin 73) must be connected to VDD.
Page 4
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CXP84332M/84340M
Pin Description
Pin code I/O Functions
I/O/Analog input
PA0/AN0
to
PA7/AN7
(Port A)
8-bit I/O port. I/O can be
set in a unit of single bits.
Incorporation of the
pull-up resistance can be
set through the software
in a unit of 4 bits.
(8 pins)
Analog inputs to A/D converter.
(8 pins)
I/OPC0 to PC7
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving
12mA sync current. Incorporation of pull-up resistor can be set through
the software in a unit of 4 bits.
(8 pins)
I/OPD0 to PD7
(Port D)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits.
(8 pins)
I/OPF0 to PF7
(Port F)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of
pull-up resistor can be set through the software in a unit of 4 bits.
(8 pins)
Input/Input
Input/Input
Input/Input
Input/Input
Output/Output
Output/Output/
Output
PE0/EC0
PE1/EC1
PE2/RMC
PE3/NMI
PE4/PWM
PE5/TO/ADJ
(Port E)
6-bit port. Lower 4 bits
are for inputs; upper
2 bits are for outputs.
(6 pins)
External event inputs for timer/counter.
(2 pins)
Remote control reception circuit input.
Non-maskable interruption request input.
14-bit PWM output.
Rectangular wave output for 16-bit
timer/counter and output for 32kHz
oscillation frequency demultiplication.
I/O/Input
I/O/Input
I/O/I/O
I/O/Input
I/O/Output
I/O/I/O
I/O/Input
Output/Output
PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
(Port B)
Lower 7-bit I/O port in
which I/O can be set in a
unit of single bits. Also,
an uppermost bit (PB7)
exclusively for output.
Incorporation of pull-up
resistor can be set
through the software in a
unit of 4 bits.
(8 pins)
External capture input to 16-bit timer/counter.
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
Page 5
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CXP84332M/84340M
Pin code I/O Functions
I/OPG0 to PG7
(Port G)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits.
(8 pins)
I/OPH0 to PH7
(Port H)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits.
(8 pins)
I/O/Input
PI0/INT0
to
PI3/INT3
I/O
PI4 to PI7
Input
Crystal connectors for system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to XTAL.
EXTAL
Output
XTAL
Input
Crystal connectors for 32kHz timer/counter clock oscillaton circuit.
For usage as event counter, input to TEX, and open TX.
TEX
Output
TX
Input Low-level active, system reset.
RST
NC. Under normal operating conditions, connect to VDD.
NC
Input Reference voltage input for A/D converter.
AVREF
A/D converter GND.
AVss
Vcc supply.
VDD
GND
Vss
(Port I)
8-bit I/O ports. I/O can be set in a unit of single
bits. Incorporation of pull-up resistor can be set
through the software in a unit of 4 bits.
(8 pins)
External interruption
request inputs.
(4 pins)
Page 6
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CXP84332M/84340M
Port B
Data bus
RD (Port B)
Port B direction
IP
Port B data
Pull-up resistance
"0" when reset
"0" when reset
∗
Pull-up transistors
approx. 10kΩ
∗
Schmitt input
CINT
CS0
SI0
SI1
8 pins
Hi-Z
Hi-Z
When reset
PA0/AN0
to
PA7/AN7
PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1
Port B
Data bus
RD (Port B)
IP
Port B output
selection
"0" when reset
∗
Pull-up transistors
approx. 10kΩ
∗
Schmitt input
SCK in
Port B data
Port B direction
"0" when reset
Pull-up resistance
"0" when reset
SCK OUT
Output enable
4 pins
2 pins
Hi-Z
PB2/SCK0
PB5/SCK1
Data bus
RD (Port A)
Port A direction
IP
Port A data
Pull-up resistance
Port A input selection
Input protection
circuit
"0" when reset
"0" when reset
"0" when reset
Input multiplexer
A/D converter
∗
Pull-up transistors
approx. 10kΩ
∗
I/O Circuit Format for Pins
Port A
Pin
Circuit format
Page 7
– 7 –
CXP84332M/84340M
1 pin
Hi-Z
Hi-Z
Pin
When reset
Circuit format
PB4/SO0
PC0 to PC7
8 pins
4 pins
Hi-Z
PE0/EC0
PE1/EC1
PE2/RMC
PE3/NMI
IP
Schmitt input
RD (Port E)
Data bus
EC0
EC1
RMC/NMI
Data bus
RD (Port C)
Port C direction
IP
Port C data
Pull-up resistance
"0" when reset
"0" when reset
∗
1 Large current 12mA
∗
2 Pull-up transistors
approx. 10kΩ
∗
2
∗
1
Data bus
RD (Port B)
IP
Port B output
selection
"0" when reset
∗
Pull-up transistors
approx. 10kΩ
∗
Port B data
Port B direction
"0" when reset
Pull-up resistance
SO
Output enable
"0" when reset
Port E
Port C
Port B
1 pin
High level
with approx.
200kΩ
resistor
when reset
PB7/SO1
Data bus
RD (Port B)
"1" when reset
∗
Pull-up transistors
approx. 200kΩ
Port B output
selection
Port B data
Output enable
SO
Internal reset signal
∗
Port B
( )
Page 8
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CXP84332M/84340M
1 pin
High level
Pin
When reset
Circuit format
PE5/TO/ADJ
Data bus
Port E output
selection
"0" when reset
Port E data
"1" when reset
∗
ADJ signals are frequency dividing outputs
for 32kHz oscillation frequency adjustment
ADJ2K provides usage as buzzer output.
Port E output
selection
"00" when reset
Port E output
selection
Output enable
TO
ADJ16K
ADJ2K
MPX
RD (Port E)
Port E
1 pin
High level
PE4/PWM
Data bus
Port E output
selection
PWM
Port E data
"0" when reset
"1" when reset
RD (Port E)
Port E
36 pins
Hi-Z
PD0 to PD7
PF0 to PF7
PG0 to PG7
PH0 to PH7
PI4 to PI7
IP
A
Ports D, F, G, H, I data
"0" when reset
∗
Pull-up transistors
approx. 10kΩ
∗
Ports D, F, G, H, I directon
Pull-up resistance
"0" when reset
RD (Ports D, F, G, H, I)
Data bus
Port D
Port F
Port G
Port H
Port I
Page 9
– 9 –
CXP84332M/84340M
2 pins
Oscillation
Pin
When reset
Circuit format
EXTAL
XTAL
IP
EXTAL
XTAL
• Diagram shows
circuit composition
during oscillation.
• Feedback resistor
is removed during stop.
IP
2 pins
Oscillation
TEX
TX
IP
TEX
• Diagram shows
circuit composition
during oscillation.
IP
• When the operation of the oscillation
circuit is stopped by the software, the
feedback resistor is removed, and TEX
and TX become “Low” level and “High”
level respectively.
TX
1 pin
Low level
RST
Schmitt input
Pull-up resistance
Mask option
OP
IP
4 pins
Hi-Z
Data bus
IP
A
Port I data
"0" when reset
∗
Pull-up transistors
approx. 10kΩ
∗
Port I direction
Pull-up resistance
"0" when reset
INT0
INT1
INT2
INT3
RD (Port I)
Schmitt input
Port I
PI0/INT0
to
PI3/INT3
Page 10
– 10 –
CXP84332M/84340M
Input voltage
Output voltage
High level output current
High level total output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
∗
1) VIN and VOUT must not exceed VDD + 0.3V.
∗
2) The large current drive transistor is the N-ch transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
VDD
AVSS
VIN
VOUT
IOH
∑IOH
IOL
IOLC
∑IOL
Topr
Tstg
PD
Low level output current
Supply voltage
–0.3 to +7.0
–0.3 to +0.3
–0.3 to +7.0
∗
1
–0.3 to +7.0
∗
1
–5
–50
15
20
100
–20 to +75
–55 to +150
600
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
mW
Output per pin
Total for all output pins
Value per pin, excluding large current outputs
Value per pin
∗
2
for large current outputs
Total for all output pins
Item Symbol Ratings Unit Remarks
Absolute Maximum Ratings (Vss = 0V reference)
High level input
voltage
Low level input
voltage
Operating temperature
Supply voltage
5.5
5.5
5.5
5.5
VDD
VDD
VDD + 0.3
0.3VDD
0.2VDD
0.4
+75
V
V
V
V
V
V
°C
V
Item
Symbol Min. Max. Unit Remarks
4.5
3.5
2.7
2.5
0.7VDD
0.8VDD
VDD – 0.4
0
0
–0.3
–20
VIH
VIHS
VIHEX
VIL
VILS
VILEX
Topr
Guaranteed operation range for high speed
mode
∗
1
Guaranteed operation range for low speed
mode
∗
1
Guaranteed operation range with TEX clock
Guaranteed data hold range during STOP
∗
2
Hysteresis input
∗
3
EXTAL
∗
4
∗
2
Hysteresis input
∗
3
EXTAL
∗
4
VDD
Recommended Operating Conditions (Vss = 0V reference)
∗
1) High speed mode is 1/2 frequency dividing clock selection; low-speed mode is 1/16 frequency dividing
clock selection.
∗
2) Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PD, PF to PH, PI4 to PI7).
∗
3) Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0, EC1, RMC, NMI, INT0, INT1, INT2,
INT3.
∗
4) Specifies only during external clock input.
Page 11
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CXP84332M/84340M
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 5.5V
High level
output current
4.0
3.5
0.5
–0.5
0.1
–0.1
–1.5
–10
V
V
V
V
V
µA
µA
µA
µA
µA
mA
µA
µA
PC
PA to PD,
PE4, PE5,
PF to PI
EXTAL
TEX
RST
∗1
Item Symbol Pins Conditions Min.
Clock 1MHz
0V for all pins excluding measured
pins
VDD
IDD1
IIL
IIZ
IDD2
IDDS1
IDDS2
IDDS3
CIN
VOH
VOL
IIHE
IILE
IIHT
IILT
IILR
Low level
output current
Input current
Typ.
0.4
0.6
1.5
40
–40
10
–10
–400
–2.0
±10
Max.
Unit
DC Characteristics
Electrical Characteristics
(Ta = –20 to +75°C, Vss = 0V reference)
∗
1) RST specifies the input current when pull-up resistance has been selected; leakage current when no
resistance has been selected.
∗
2) PA to PD, and PF to PI pins specifie the input current when pull-up resistance has been selected; leakage
current when no resistance has been selected. (Excludes output PB7)
∗
3) When all pins are open.
VDD = 5.5V, 20MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
VDD = 5.5V, 20MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
VDD = 5.5V, termination of 20MHz
and 32kHz crystal oscillation
Power supply
current
∗
3
Input capacity
VDD = 5.5V,
VIL = 0.4V
VDD = 4.5V, VIL = 4.0V
VDD = 5.5V,
VI = 0, 5.5V
High-speed mode operation
(1/2 frequency dividing clock)
SLEEP mode
STOP mode
I/O leakage
current
PA to PD∗2,
PF to PI
∗2
PE0 to PE3,
RST
∗1
52
100
10
10
30
32
38
1.4
9
mA
µA
mA
µA
pF2010
µA
PA,
PB0 to PB6,
PC, PD,
PE0 to PE3,
PF to PI,
EXTAL,
XTAL, TEX,
TX, RST
Page 12
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CXP84332M/84340M
EXTAL
t
XH tXLtCF tCR
0.4V
V
DD – 0.4V
1/fc
A
A
Crystal oscillation
Ceramic oscillation
EXTAL
XTAL
External clock
EXTAL
XTAL
74HC04
C
1 C2
A
32kHz clock applied condition
Crystal oscillation
TEX
TX
C
1 C2
TEX
EC0
EC1
t
EH tELtEF tER
0.2VDD
0.8VDD
tTH tTLtTF tTR
Fig. 2. Clock applied conditions
Fig. 1. Clock timing
Fig. 3. Event count clock timing
AC Characteristics
(1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
∗
1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the control
clock register (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
System clock frequency
System clock input pulse
width
System clock input
rise time, fall time
Event count input clock
pulse width
Event count input clock
rise time, fall time
System clock frequency
Event count input clock
input pulse width
Event count input clock
rise time, fall time
fC
tXL,
tXH
tCR,
tCF
tEH,
tEL
tER,
tEF
fC
tTL,
tTH
tTR,
tTF
XTAL
EXTAL
EXTAL
EXTAL
EC0
EC1
EC0
EC1
TEX
TX
TEX
TEX
MHz
ns
ns
ns
ms
kHz
µs
ms
Item Symbol Pin Conditions Min. Unit
Fig. 1, Fig. 2
Fig. 1, Fig. 2
External clock drive
Fig. 1, Fig. 2
External clock drive
Fig. 3
Fig. 3
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
Fig. 3
Fig. 3
1
23.0
tsys + 50
∗
1
10
Typ.
32.768
Max.
20
200
20
20
AAA
AA
AA
Page 13
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CXP84332M/84340M
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss reference)
Item
CS0 ↓ → SCK0
delay time
CS0 ↑ → SCK0
float delay time
CS0 ↓ → SO0
delay time
CS0 ↑ → SO0
float delay time
CS0 High level width
SCK0 cycle time
SCK0
High, Low level width
SI0 input set-up time
(for SCK0 ↑)
SI0 input hold time
(for SCK0 ↑)
SCK0 ↓ → SO0
delay time
tDCSK
tDCSKF
tDCSO
tDCSOF
tWHCS
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK0
SCK0
SO0
SO0
CS0
SCK0
SCK0
SI0
SI0
SO0
Input mode
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
ns
ns
ns
ns
ns
Symbol Pin Min.
tsys + 200
tsys + 200
tsys + 200
tsys + 200
tsys + 200
2tsys + 200
16000/fc
tsys + 100
8000/fc – 50
100
200
tsys + 200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsys+200
100
Max. UnitCondition
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the
control clock register (address: 00FEH).
tsys (ns) = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
Page 14
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CXP84332M/84340M
Fig. 4. Serial transfer CH0 timing
CS0
SCK0
0.2V
DD
0.8VDD
tWHCS
tDCSK tDCSKF
0.8VDD
0.2VDD
0.8VDD
tKCY
tKL tKH
0.8VDD
0.2VDD
SI0
t
SIK
Input
data
tDCSO tKSO tDCSOF
Output data
0.8V
DD
0.2VDD
SO0
tKSI
Page 15
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CXP84332M/84340M
Fig. 5. Serial transfer CH1 timing
SCK1
SI1
SO1
t
KCY
tKL tKH
0.2VDD
0.8VDD
tSIK tKSI
tKSO
Input data
Output data
0.2V
DD
0.8VDD
0.2VDD
0.8VDD
Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pin Min. Max. UnitCondition
SCK1 cycle time
SCK1 High, Low level width
SI1 input set-up time
(for SCK1 ↑)
SI1 input hold time
(for SCK1 ↑)
SCK1 ↓ → SO1 delay time
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK1
SCK1
SI1
SI1
SO1
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
1000
16000/fc
400
8000/fc – 50
100
200
200
100
200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
Page 16
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CXP84332M/84340M
Fig. 6. Definition of A/D converter terms
Analog input
Linearity error
V
FTVZT
00H
01H
FEH
FFH
Digital conversion value
∗
1) VZT : Value at which the digital transfer value changes
from 00H to 01H and vice versa.
∗
2) VFT : Value at which the digital transfer value changes
from FEH to FFH and vice versa.
∗
3) fADC indicates the values below due to the contents of
bit 6 (CKS) of the A/D control register (ADC: 00F9H)
and bits 7 (PCK1) and 6 (PCK0) of the clock control register
(CLC: 00FEH).
00 (φ = fEX/2)
01 (φ = fEX/4)
11 (φ = fEX/16)
fADC = fC/2
fADC = fC/4
fADC = fC/16
0 (φ/2 selection)
CKS
PCK1, 0
fADC = fC
fADC = fC/2
fADC = fC/8
1 (φ selection)
Conversion time
Sampling time
Reference input voltage
Analog input voltage
tCONV
tSAMP
VREF
VIAN
VZT
∗
1
VFT
∗
2
IREF
AVREF
AN0 to AN7
Ta = 25°C
VDD = AVREF = 5.0V
VSS = AVSS = 0V
Operation mode
SLEEP mode
STOP mode
32kHz operation mode
Linearity error
Zero transition voltage
Full-scale transition
voltage
Resolution
AVREF current
AVREF
IREFS
µs
µs
V
V
VDD
AVREF
1.0
mA
10 µA
0.6
160/fADC
∗
3
12/fADC
∗
3
VDD – 0.5
0
Item Symbol Pin Condition Min. Typ. Max. Unit
Bits
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to VDD, Vss = AVSS = 0V reference)
8
LSB
110 mV
5070
10
4970
–10
4870 mV
±5
Page 17
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CXP84332M/84340M
(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
0.2VDD
0.8VDD
tIH tIL
INT0
INT1
INT2
INT3
NMI
(NMI specifies only for
the falling edge.)
tIL tIH
Fig 7. Interruption input timing
tRSL
0.2VDD
RST
External interruption
High, Low level width
Reset input Low level width
INT0
INT1
INT2
INT3
NMI
RST
1
32/fc
µs
µs
Item Symbol Pin Condition Min. Max. Unit
tIH
tIL
tRSL
Fig. 8. RST input timing
Page 18
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CXP84332M/84340M
Appendix
Fig. 9. Recommended oscillation circuit
A
EXTAL
XTAL
Rd
A
EXTAL
XTAL
(i) Main clock
A
EXTAL
XTALXTAL
(ii) Main clock
A
EXTAL
XTAL
C
1 C2
Rd
A
TEX
TX
(iii) Sub clock
C1
Rd
C2
Item
Content
Reset pin pull-up resistance Non-existent Existent
Mask option table
Products List
Manufacturer
MURATA MFG CO., LTD.
RIVER ELETEC CO., LTD.
KINSEKI LTD.
Model
CSA16.00MXZ072
CSA20.00MXZ046
HC-49/U03
P3
16.00
20.00
16.00
20.00
32.768kHz
0
8
6
50
0
8
6
22
(i)
(ii)
(iii)
fc (MHz) C1 (pF) C2 (pF)
0
0
1M
Rd (Ω)
Circuit
example
AA
AA
AA
AA
AA
Page 19
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CXP84332M/84340M
Example of Representative Characteristics
VDD – Supply voltage [V]
IDD vs. VDD
(fc = 20MHz, Ta = 25°C, Typical)
1/2 dividing mode
1/4 dividing mode
1/16 dividing mode
SLEEP mode
20
10
02 10 20
3 4 65 7
1/2 dividing mode
1/4 dividing mode
1/16 dividing mode
SLEEP mode
32kHz mode
(instruction)
32kHz
SLEEP mode
I
DD
– Supply curren [mA]
50
30
20
10
5
1
0.5
(500µA)
0.1
(100µA)
1.05
(50µA)
0.01
(10µA)
IDD vs. fc
(VDD = 5V, Ta = 25°C, Typical)
50 1
Frequency [MHz]
15
30
I
DD
– Supply current [mA]
Page 20
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CXP84332M/84340M
Package Outline Unit: mm
PACKAGE STRUCTURE
SONY CODE
EIAJ CODE
JEDEC CODE
QFP-80P-L01
QFP080-P-1420
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
1.6g
23.9 ± 0.4
20.0 – 0.1
+ 0.4
1
80
65
64
41
40
25
24
0.8
0.35 – 0.1
+ 0.15
14.0 – 0.1
+ 0.4
17.9 ± 0.4
16.3
0.1 – 0.05
+ 0.2
2.75 – 0.15
+ 0.35
0.8 ± 0.2
0.15 – 0.05
+ 0.1
80PIN QFP (PLASTIC)
M
0.2
0.15
0° to 10°
DETAIL A
A
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