Page 1
CMOS 8-bit Single Chip Microcomputer
CXP83408/83412/83416
CXP83409/83413/83417
Description
The CXP83408/83412/83416 and CXP83409/83413/
83417 are a CMOS 8-bit microcomputer which consists of
A/D converter, serial interface, timer/counter, time
base timer, 32kHz timer/counter, LCD controller/
driver, remote control receiving circuit and PWM
output, as well as basic configurations like 8-bit CPU,
ROM, RAM and I/O port. They are integrated into a
single chip.
Also CXP83408/83412/83416 and CXP83409/83413/
83417 sleep/ stop function which enables to lower power
consumption.
Features
• A wide instruction set (213 instructions) which
covers various types of data
–16-bit arithmetic/multiplication and division/
Boolean bit operation instructions
• Minimum instruction cycle 400ns at 10MHz operation (4.5 to 5.5V)
122µs at 32kHz operation (2.7 to 5.5V)
• Incorporated ROM capacity 8K bytes (CXP83408, 83409)
12K bytes (CXP83412, 83413)
16K bytes (CXP83416, 83417)
• Incorporated RAM capacity 448 bytes (LCD display data area included)
• Peripheral functions
– A/D converter 8 bits, 8 channels, successive approximation system
(Conversion time: 32µs/10MHz)
– Serial interface Incorporated 8-bit and 8-stage FIFO
(1 to 8 bytes auto transfer), 1 circuit 2 channels
– Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter
– LCD controller/driver Maximum 128 segments display possible (During 1/4 duty)
4 common outputs, 32 segment outputs
Display method: Static, 1/2, 1/3 and 1/4 duty
Bias method: 1/2 and 1/3 bias
– Remote control receiving circuit 8-bit pulse measurement counter, 6-stage FIFO
– PWM output 14 bits 1 channel, 8 bits 1 channel
• Interruption 12 factors, 12 vectors, multi-interruption possible
• Standby mode SLEEP/STOP
• Package 80-pin plastic QFP/LQFP
• Piggyback/evaluator CXP83400 (CXP83408, 83412, 83416)
CXP83401 (CXP83409, 83413, 83417)
80 pin QFP (Plastic) 80 pin LQFP (Plastic)
CXP83408/83412/83416
CXP83409/83413/83417
80 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E93Z15C72-PS
Page 2
CXP83408/83412/83416, CXP83409/83413/83417
Vss
V
DD
RST
XTAL
EXTAL
TX
TEX
PA0 to PA7
8
PORT A
CLOCK GENERATOR/
SPC700
PB0 to PB7
8
PORT B
SYSTEM CONTROL
CPU CORE
PC0 to PC7
8
PORT C
PD0 to PD7
8
RAM
448 BYTES
ROM
8K/12K/16K BYTES
PORT D
PE0 to PE4
PE5 to PE6
5
2
PORT E
32kHz
TIMER/COUNTER
PRESCALER/
TIME BASE TIMER
PF0 to PF7
8
PORT F
PH0
1
PORT H
2
NMI/INT3
INT2
INT1
INT0
LCD
A/D CONVERTER
8
4
32
DRIVER
CONTROLLER/
VL
VLC1
VLC2
VLC3
INTERRUPT CONTROLLER
2
FIFO
REMOCON
8BIT PWM GENERATOR
14BIT PWM GENERATOR
CS0
PWM1
RMC
PWM0
SI0
SERIAL
SO0
FIFO
INTERFACE
SCK0
UNIT 0
SI1
CS1
8BIT TIMER 1
8BIT TIMER/COUNTER 0
TO
SO1
EC
SCK1
ADJ
2
Block Diagram
AN0 to AN7
SEG0 to SEG31
COM0 to COM3
– 2 –
Page 3
Pin Assignment (Top View) CXP83408/83412/83416 (QFP package)
CXP83408/83412/83416, CXP83409/83413/83417
PE3/INT3/NMI
PE4/RMC
PE5/PWM0
PE6/TO/ADJ
PB0/CS1
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PH0/PWM1
PA0/AN0
PA1/AN1
PA2/AN2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PE2/INT2
80
79
PE0/INT0/EC
PE1/INT1
78
77
NC
PF6/SEG30
PF7/SEG31
75
76
74
TEX
73
TX
72
DD
V
PF5/SEG29
70
71
PF2/SEG26
PF3/SEG27
PF4/SEG28
69
68
67
1
2
3
4
5
6
7
8
9
PD7/SEG23
PF0/SEG24
PF1/SEG25
65
66
60
59
58
64
63
62
57
56
55
54
53
49
48
47
46
45
44
41
61
52
51
50
43
42
PD6/SEG22
PD5/SEG21
PD4/SEG20
PD3/SEG19
PD2/SEG18
PD1/SEG17
PD0/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM3
26
25
PA3/AN3
27 28
PA5/AN5
PA4/AN4
30
29
PA7/AN7
PA6/AN6
31
RST
32
XTAL
EXTAL
33
SS
V
34
35
L
V
LC3
V
36
LC2
V
37
LC1
V
Note) NC (Pin 75) is always connected to VDD.
– 3 –
38
39
COM1
COM0
40
COM2
Page 4
Pin Assignment (Top View) CXP83408/83412/83416 (LQFP package)
CXP83408/83412/83416, CXP83409/83413/83417
PE5/PWM0
PE6/TO/ADJ
PB0/CS1
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PH0/PWM1
PA0/AN0
10
11
12
13
14
15
16
17
18
19
20
PE4/RMC
80
79
PE1/INT1
PE2/INT2
PE3/INT3/NMI
78
76
77
PF6/SEG30
PF7/SEG31
PE0/INT0/EC
75
73
74
NC
72
TEX
71
TX
70
DD
V
PF4/SEG28
PF5/SEG29
69
68
PF3/SEG27
66
67
PF0/SEG24
PF1/SEG25
PF2/SEG26
65
64
63
1
2
3
4
5
6
7
8
9
PD5/SEG21
PD6/SEG22
PD7/SEG23
62
61
59
60
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PD4/SEG20
PD3/SEG19
PD2/SEG18
PD1/SEG17
PD0/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
21
22
PA1/AN1
23
24
PA3/AN3
PA2/AN2
26 27
25
PA5/AN5
PA4/AN4
28
PA7/AN7
PA6/AN6
29
RST
30
XTAL
EXTAL
31
32
L
SS
V
V
33
LC3
V
34
LC2
V
35
Note) NC (Pin 73) is always connected to VDD.
– 4 –
LC1
V
36
37
COM1
COM0
38
39
COM2
40
COM3
SEG0
Page 5
Pin Assignment (Top View) CXP83409/83413/83417 (QFP package)
CXP83408/83412/83416, CXP83409/83413/83417
PE5/PWM0
PE6/TO/ADJ
PB0/CS1
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PH0/PWM1
PA0/AN0
10
11
12
13
14
15
16
17
18
19
20
PE4/RMC
80
79
PE1/INT1
PE2/INT2
PE3/INT3/NMI
78
76
77
PF6/SEG30
PF7/SEG31
PE0/INT0/EC
75
73
74
NC
72
TEX
71
TX
70
DD
V
PF4/SEG28
PF5/SEG29
69
68
PF3/SEG27
66
67
PF0/SEG24
PF1/SEG25
PF2/SEG26
65
64
63
1
2
3
4
5
6
7
8
9
PD5/SEG21
PD6/SEG22
PD7/SEG23
62
61
59
60
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PD4/SEG20
PD3/SEG19
PD2/SEG18
PD1/SEG17
PD0/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
21
22
PA1/AN1
23
24
PA3/AN3
PA2/AN2
26 27
25
PA5/AN5
PA4/AN4
28
PA7/AN7
PA6/AN6
29
RST
30
XTAL
EXTAL
31
32
L
SS
V
V
33
LC3
V
34
LC2
V
35
Note) NC (Pin 73) is always connected to VDD.
– 5 –
LC1
V
36
37
COM0
38
COM2
COM1
39
COM3
40
SEG0
Page 6
Pin Description
Symbol I/O Functions
(Port A)
8-bit I/O port. I/O can be
PA0/AN0
to
PA7/AN7
I/O/Analog input
set in a unit of single bits.
Incorporation of pull-up
resistor can be set
through the software in a
Analog inputs to A/D converter.
(8 pins)
unit of 4 bits.
(8 pins)
CXP83408/83412/83416, CXP83409/83413/83417
PB0/CS1
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PE0/INT0/EC
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5/PWM0
PE6/TO/ADJ
I/O/Input
I/O/Input
I/O/I/O
I/O/Input
I/O/Output
I/O/I/O
I/O/Input
I/O/Output
I/OPC0 to PC7
Input/Input/Input
Input/Input
Input/Input
Input/Input/Input
Input/Input
Output/Output
Output/Output/
Output
Chip select input for serial interface (CH1).
(Port B)
8-bit I/O port. I/O can be
set in a unit of single bits.
Incorporation of pull-up
resistor can be set
through the software in a
unit of 4 bits.
(8 pins)
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving
12mA sync current. Incorporation of pull-up resistor can be set through
the software in a unit of 4 bits.
(8 pins)
External event inputs
for timer/counter.
External interruption
request input. (4 pins)
(Port E)
7-bit port. Lower 5 bits
are for inputs; upper
2 bits are for outputs.
(7 pins)
Remote control receiving circuit input.
Non-maskable intrruption
request input.
14-bit PWM output.
Rectangular wave output for 8-bit timer/
counter and 32kHz oscillation frequency
divider output.
PH0/PWM1
I/O/Output
(Port H)
1-bit I/O port. Incorporation
of pull-up resistor can be
set through the software.
(1 pin)
– 6 –
8-bit PWM output.
Page 7
CXP83408/83412/83416, CXP83409/83413/83417
Symbol I/O Functions
PD0/SEG16
to
PD7/SEG23
PF0/SEG24
to
PF7/SEG31
SEG0 to SEG15
COM0 to COM3
VLC1 to VLC3
VL
EXTAL
TEX
RST
NC
VDD
Output/Output
Output/Output
Output
Output
Output
Input
OutputXTAL
Input
OutputTX
Input
(Port D)
8-bit output port.
(8 pins)
(Port F)
LCD segment signal output.
(16 pins)
8-bit output port.
(8 pins)
LCD segment signal output.
LCD common signal output.
LCD bias power supply.
Control pin to cutt off the current flowing to external LCD bias resistor
during standby.
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
Crystal connectors for 32kHz timer/counter clock generation circuit.
For usage as event counter, connect clock oscillation source to TEX,
and leave TX open.
Low-level active, system reset.
NC. Under normal operating conditions, connect to VDD.
Positive power supply.
Vss
GND.
– 7 –
Page 8
I/O Circuit Format for Pins
CXP83408/83412/83416, CXP83409/83413/83417
Pin
PA0/AN0
to
PA7/AN7
8 pins
PB0/CS1
PB1/CS0
PB3/SI0
PB6/SI1
Port A
Port B
Data bus
Data bus
Circuit format
Pull-up resistor
“0” when reset
Port A data
Port A direction
“0” when reset
RD (Port A)
Port A input selection
“0” when reset
A/D converter
Pull-up resistor
“0” when reset
Port B data
Port B direction
“0” when reset
Input multiplexer
Schmitt input
∗
Input protection
IP
circuit
∗
Pull-up resistors
approx. 100kΩ
∗
IP
When reset
Hi-Z
Hi-Z
4 pins
PB2/SCK0
PB5/SCK1
2 pins
Port B
Data bus
Pull-up resistor
“0” when reset
Output enable
Port B output
selection
“0” when reset
Port B data
Port B direction
“0” when reset
RD (Port B)
RD (Port B)
SCK OUT
SCK in
CS1
CS0
SI0
SI1
∗
Pull-up transistors
approx. 100kΩ
Schmitt input
∗
Pull-up transistors
approx. 100kΩ
∗
Hi-Z
IP
– 8 –
Page 9
CXP83408/83412/83416, CXP83409/83413/83417
Pin
PB4/SO0
PB7/SO1
2 pins
Port B
Data bus
Port C
Pull-up resistor
“0” when reset
Output enable
Port B output
selection
“0” when reset
Port B data
Port B direction
“0” when reset
RD (Port B)
Pull-up resistor
“0” when reset
SO
Port C data
Circuit format
∗
Pull-up transistors
approx. 100kΩ
∗
2
When reset
∗
Hi-Z
IP
PC0 to PC7
8 pins
PE0/INT0/EC
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
5 pins
Port E
Data bus
Port C direction
“0” when reset
RD (Port C)
IP
Schmitt input
RD (Port E)
∗1
∗
1
Large current 12mA
∗
2
Pull-up transistors
approx. 100kΩ
INT0/EC
INT1
INT2
INT3/NMI
RMC
Data bus
IP
Hi-Z
Hi-Z
– 9 –
Page 10
CXP83408/83412/83416, CXP83409/83413/83417
Pin
PE5/PWM0
1 pin
PE6/TO/ADJ
1 pin
Port E
Port E output selection
Data bus
Port E
Port E data
“1” when reset
ADJ16K
2
∗
ADJ2K
Port E output selection (upper)
Port E output selection (lower)
TO Output enable
“0” when reset
Port E data
RD (Port E)
TO
Circuit format
PWM0
“1” when reset
Internal reset signal
MPX
∗1
Pull-up transistors approx. 150kΩ.
∗2
ADJ signals are frequency divider outputs
for 32kHz oscillation frequency adjustment.
ADJ2K provides usage as buzzer output.
When reset
High level
∗1
High level
with pull-up
transistor ON
resistor when
()
reset
PH0/PWM1
1 pin
Port H
Pull-up resistor
“0” when reset
Port H output selection
“0” when reset
Port H data
Port H direction
“0” when reset
Data bus
RD (Port H)
PWM1
∗
Pull-up transistors
approx. 100kΩ
∗
Hi-Z
IP
– 10 –
Page 11
CXP83408/83412/83416, CXP83409/83413/83417
Pin
PD0 to PD7
PF0 to PF7
24 pins
SEG0 to SEG15
16 pins
Port D
Port F
PD7 to PD4
PD3 to PD0
PF7 to PF0
Segment
by a bit unit
by 4-bit unit
VCH
VCL
Circuit format
Port data
Port/segment output
selection
“0” when reset
Segment data
When reset
Segment
output
(VDD level)
Segment
driver
VDD level
COM0 to COM3
4 pins
VL
1 pin
Common
VDD
VLC1
VLC2
VLC3
LCD control
(DSP bit)
“0” when reset
VDD level
Hi-Z
– 11 –
Page 12
CXP83408/83412/83416, CXP83409/83413/83417
Pin
EXTAL
XTAL
2 pins
TEX
TX
2 pins
RST
EXTAL
XTAL
TEX
TX
Mask option
Circuit format
• Diagram shows circuit
composition during oscillation.
IPIP
• Feedback resistor is removed
during stop, and XTAL
becomes “High” level.
• Diagram shows circuit
composition during oscillation.
IPIP
• When the operation of the oscillation circuit is
stopped by the software, the feedback
resistor is removed and TEX and TX become
“Low” level and “High” level respectively.
Pull-up resistor
OP
IP
When reset
Oscillation
Oscillation
Low level
1 pin
Schmitt input
– 12 –
Page 13
CXP83408/83412/83416, CXP83409/83413/83417
Absolute Maximum Ratings (Vss = 0V reference)
Item Symbol Rating Unit Remarks
Supply voltage
LCD bias voltage
Input voltage
Output voltage
High level output current
High level total output current
VDD
VLC1, VLC2,
VLC3
VIN
VOUT
IOH
∑IOH
IOL
–0.3 to +7.0
–0.3 to +7.0
–0.3 to +7.0
–0.3 to +7.0
–5
–50
15
Low level output current
20
100
–20 to +75
–55 to +150
Low level total output current
Operating temperature
Storage temperature
IOLC
∑IOL
Topr
Tstg
600
Allowable power dissipation
PD
380
380
∗1
VIN and VOUT must not exceed VDD + 0.3V.
∗2
The large current drive transistor is the N-ch transistor of Port C (PC).
∗1
∗1
∗1
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
mW
mW
mW
Output (value per pin)
Total for all output pins
All pins excluding large current output
(value per pin)
Large current outputs (value per pin∗2)
Total for all output pins
QFP-80P-L01
LQFP-80P-L01
QFP-80P-L03
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
– 13 –
Page 14
CXP83408/83412/83416, CXP83409/83413/83417
Recommended Operating Conditions (Vss = 0V reference)
Item Symbol Min. Max. Unit Remarks
During 1/2 and 1/4 frequency division
operating modes guaranteed operation range
During 1/16 frequency division operating mode
V
or sleep mode quaranteed operation range
Guaranteed operation range with TEX clock
Guaranteed data hold range during STOP
Supply voltage
VDD
4.5
3.5
2.7
2.5
5.5
5.5
5.5
5.5
VLC1
LCD bias voltage
VLC2
Vss
VDD
LCD power supply range
V
∗4
VLC3
VIH
High level input voltage
VIHS
VIHEX
VIL
Low level input voltage
VILS
VILEX
Operating temperature
∗1
Value for each pin of normal input ports (PA, PB4, PB7, PC and PH0).
∗2
Value of the following pins: RST, CS0, CS1, SI0, SI1, SCK0, SCK1, EC/INT0, INT1, INT2, NMI/INT3, and RMC.
∗3
Specifies only during external clock input.
∗4
Optimal values are determined by LCD used.
Topr
0.7VDD
0.8VDD
VDD – 0.4
0
0
–0.3
–20
VDD
VDD
VDD + 0.3
0.3VDD
0.2VDD
0.4
+75
∗1
V
Hysteresis input
V
EXTAL
V
∗1
V
Hysteresis input
V
EXTAL
V
°C
∗2
∗3
∗2
∗3
– 14 –
Page 15
Electrical Characteristics
DC Characteristics
CXP83408/83412/83416, CXP83409/83413/83417
(Ta = –20 to +75°C, Vss = 0V reference)
Item Symbol Pins Conditions Min.
High level
output current
VOH
PA, PB,
PC, PD∗1,
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
PE5, PE6,
Low level
output current
VOL
IIHE
PF, PH0,
VL (VoL only)
PC
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
EXTAL
Input current
I/O leakage
current
Common
output
impedance
Segment
output
impedance
IILE
IIHT
IILT
IILR
IIL
IIH
IIZ
RCOM
RSEG
TEX
∗2
RST
PA to PC∗3,
PH∗3,
PE0 to PE4,
∗2
RST
COM0
to
COM3
SEG0 to SEG15,
SEG16 to
∗1
SEG31
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V,
VIL = 0.4V
VDD = 4.5V, VIH = 4.0V
VDD = 5.5V,
VI = 0, 5.5V
VDD = 5V,
VLC1 = 3.75V
VLC2 = 2.5V
VLC3 = 1.25V
4.0
3.5
0.5
–0.5
0.1
–0.1
–1.5
–2.78
Typ.
3
5
Max. Unit
V
V
0.4
0.6
1.5
40
–40
10
–10
–400
–45
V
V
V
V
µA
µA
µA
mA
µA
µA
±10
15
µA
kΩ
5
kΩ
Supply
current
∗4
IDD1
IDD2
IDDS1
IDDS2
IDDS3
VDD
High-speed mode operation
(1/2 frequency divider clock)
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
SLEEP mode
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
(C1 = C2 = 47pF)
STOP mode
VDD = 5.5V termination of 10MHz
and 32kHz crystal oscillation
18
35
1.1
9
40
100
8
30
10
mA
µA
mA
µA
µA
– 15 –
Page 16
CXP83408/83412/83416, CXP83409/83413/83417
Item Symbol Pins Conditions Min.
PA to PC,
Input capacity
CIN
PE1 to PE4,
EXTAL, TEX,
RST
∗1
Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24, PF7/SEG31, PD and PF are the case when the
Clock 1MHz
0V for all pins excluding
measured pins
Typ. Max. Unit
10
common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output.
∗2
RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.
∗3
PA to PC, and PH0 specify the input current when pull-up resistor has been selected; leakage current when
no resistor has been selected. (PE0 to PE4 specify the leakage current.)
∗4
When all output pins are left open.
pF20
– 16 –
Page 17
A
A
A
AC Characteristics
(1) Clock timing
CXP83408/83412/83416, CXP83409/83413/83417
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pin Conditions Min. Unit
System clock frequency
System clock input
pulse width
System clock input
rise and fall time
Event count input clock
pulse width
Event count input clock
rise and fall time
System clock frequency
Event count input clock
input pulse width
Event count input clock
rise and fall time
∗
1
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control registor (CLC: 00FEH).
fC
tXL,
tXH
tCR,
tCF
tEH,
tEL
tER,
tEF
fC
tTL,
tTH
tTR,
tTF
XTAL
EXTAL
EXTAL
EXTAL
EC
EC
TEX
TX
TEX
TEX
Fig. 1, Fig. 2
Fig. 1, Fig. 2
External clock drive
Fig. 1, Fig. 2
External clock drive
Fig. 3
Fig. 3
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
Fig. 3
Fig. 3
1
37.5
tsys + 50
10
∗
1
Typ.
32.768
Max.
10
200
20
20
tsys (ns) = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
MHz
ns
ns
ns
ms
kHz
µs
ms
Fig. 1. Clock timing
EXTAL
Fig. 2. Clock applied conditions
Crystal oscillation
Ceramic oscillation
EXTAL
AA
C
1 C2
Fig. 3. Event count clock timing
TEX
EC
XTAL
1/fc
XH tXLtCF tCR
t
32kHz clock applied condition
External clock
EXTAL
AA
74HC04
XTAL
Crystal oscillation
TEX
AA
C1 C2
TX
DD – 0.4V
V
0.4V
0.8VDD
0.2VDD
EH tELtEF tER
t
tTH tTLtTF tTR
– 17 –
Page 18
CXP83408/83412/83416, CXP83409/83413/83417
(2) Serial transfer
Item
CS0 ↓ → SCK0 (CS1 ↓ → SCK1)
delay time
CS0 ↑ → SCK0 (CS1 ↑ → SCK1)
floating delay time
CS0 ↓ → SO0 (CS1 ↓ → SO1)
delay time
CS0 ↑ → SO0 (CS1 ↑ → SO1)
floating delay time
CS0 (CS1) high level width
SCK0 (SCK1) cycle time
SCK0 (SCK1)
high and low level widths
SI0 (SI1) input setup time
(for SCK0↑ (SCK1↑) )
SI0 (SI1) input hold time
(for SCK0↑ (SCK1↑) )
SCK0 ↓ → SO0 (SCK1 ↓ → SO1)
delay time
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol Pin Min.
tDCSK
tDCSKF
tDCSO
tDCSOF
tWHCS
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK0
(SCK1)
SCK0
(SCK1)
SO0
(SO1)
SO0
(SO1)
CS0
(CS1)
SCK0
(SCK1)
SCK0
(SCK1)
SI0
(SI1)
SI0
(SI1)
SO0
(SO1)
Chip select transfer mode
(SCK0 (SCK1) = output mode)
Chip select transfer mode
(SCK0 (SCK1) = output mode)
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
Input mode
Output mode
Input mode
Output mode
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode
SCK0 (SCK1) input mode
SCK0 (SCK1) output mode
Conditions
tsys + 200
2tsys + 200
16000/fc
tsys + 100
8000/fc – 50
100
200
tsys + 200
100
Max. Unit
tsys + 200
tsys + 200
tsys + 200
tsys + 200
tsys + 200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEH).
tsys (ns) = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL.
– 18 –
Page 19
Fig. 4. Serial transfer CH0 timing
CXP83408/83412/83416, CXP83409/83413/83417
tWHCS
CS0
(CS1)
SCK0
(SCK1)
0.2V
DD
tKCY
tDCSK tDCSKF
tKL tKH
0.8VDD
0.2VDD
SIK tKSI
t
0.8VDD
0.8VDD
SI0
(SI1)
SO0
(SO1)
0.8VDD
Input
data
0.2VDD
DCSO tKSO tDCSOF
t
Output data
DD
0.8V
0.2VDD
– 19 –
Page 20
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = 0V reference)
CXP83408/83412/83416, CXP83409/83413/83417
Item
Symbol Pin Conditions Min. Typ. Max. Unit
Resolution
Linearity error
∗1
Zero transition voltage
Full-scale transition
voltage
Conversion time
Sampling time
Analog input voltage
VZT
∗2
VFT
tCONV
tSAMP
VIAN
AN0 to AN7
Fig. 5. Definition of A/D converter terms
FFH
FEH
Digital conversion value
01H
00H
Linearity error
Analog input
V
FTVZT
8
±3 LSB
Ta = 25°C
VDD = 5.0V
–10
10
70 mV
VSS = 0V
4910 mV
160/fADC
12/fADC
∗3
4970
∗3
5030
0
∗1
VZT: Value atwhich the digital conversion value changes
from 00H to 01H and vice versa.
∗2
VFT: Value at which the digital conversion value changes
from FEH to FFH and vice versa.
∗3
fADC indicates the below values due to the contents of bit 6
(CK3) of the A/D control registor (ADC: 00F9H) and bit 7
(PCK1) and bit 6 (PCK0) of the clock control resistor (CLC:
00FEH).
CKS
0 (φ/2 selection)
0 (φ selection)
PCK1, PCK0
00 (φ = fEX/2)
fADC = fc/2
fADC = fc
Bits
µs
µs
VVDD + 0.3
01 (φ = fEX/4)
11 (φ = fEX/16)
– 20 –
fADC = fc/4
fADC = fc/16
fADC = fc/2
fADC = fc/8
Page 21
CXP83408/83412/83416, CXP83409/83413/83417
(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pin
External interruption
high and low level widths
Reset input low level width
Fig 6. Interruption input timing
INT0
INT1
INT2
NMI/INT3
(NMI is specified only for
the falling edge)
tIH
tIL
tRSL
Conditions
INT0
INT1
INT2
NMI/INT3
RST
tIH tIL
0.8VDD
tIL tIH
Min. Max. Unit
1
32/fc
µs
µs
0.2VDD
Fig. 7. RST input timing
RST
tRSL
0.2VDD
– 21 –
Page 22
Appendix
A
A
A
A
A
Fig. 8. SPC700 Series recommended oscillation circuit
CXP83408/83412/83416, CXP83409/83413/83417
(i) Main clock
EXTAL
EXTAL
AA
AA
C1
Manufacturer
MURATA
MFG
CO., LTD.
RIVER
ELETEC
CO., LTD.
KINSEKI
LTD.
Models with an asterisk (
XTAL
XTAL
Rd
Rd
C
2
CSA4.19MG
CSA8.00MG
CSA10.0MT
CST4.19MGW
CST8.00MTW
CST10.00MTW
HC-49/U03
HC-49/U (-S)
(ii) Main clock
EXTAL
Model
∗
1
) have the built-in ground capacitance (C1, C2).
∗
∗
1
1
∗
1
fc (MHz)
10.00
10.00
10.00
10.00
XTAL
XTAL
AA
C1 C2
4.19
8.00
4.19
8.00
4.19
8.00
4.19
8.00
Rd
C1 (pF) C2 (pF)
30
15
22
18 18
30
15
22
(iii) Sub clock
EXTAL
TEX
AAA
AAA
1 C2
C
Rd (Ω)
2.2k
470
560
XTAL
TX
example
0
0
Rd
Circuit
(i)
(ii)
(i)
Mask Option Table
Item
Reset pin pull-up resistor
Package Table
Product name
CXP83408/83412/83416
CXP83409/83413/83417
Content
Non-existent Existent
Package
80-pin plastic QFP/LQFP
80-pin plastic QFP (0.65mm pitch)
– 22 –
Page 23
Characteristic Curves
CXP83408/83412/83416, CXP83409/83413/83417
(fc = 10MHz, Ta = 25°C, Typical)
20.0
10.0
5.0
1.0
0.5
– Supply current [mA]
DD
I
0.1
(100µA)
0.05
(50µA)
0.01
(10µA)
V
DD – Supply voltage [V]
IDD vs. VDD
3
45
1/2 dividing mode
SLEEP mode
32kHz mode
(instruction)
32kHz
SLEEP mode
6
72
(V
DD = 5V, Ta = 25°C, typical)
20
15
– Supply current [mA]
DD
10
I
5
0
fc – System clock [MHz]
IDD vs. fc
5
1/2 dividing mode
SLEEP mode
10
16
Package Outline Unit : mm
CXP83408/83412/83416
64
65
80
1
SONY CODE
EIAJ CODE
JEDEC CODE
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.4
20.0 – 0.1
41
40
+ 0.4
17.9 ± 0.4
14.0 – 0.1
25
24
0.8
0° to 10°
DETAIL A
0.12
QFP-80P-L01
∗QFP080-P-1420-A
M
+ 0.15
0.35 – 0.1
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
2.75 – 0.15
+ 0.1
0.15 – 0.05
+ 0.35
EPOXY RESIN
SOLDER PLATING
COPPER / 42 ALLOY
1.6g
A
+ 0.2
0.1 – 0.05
0.15
16.3
0.8 ± 0.2
– 23 –
Page 24
CXP83408/83412/83416
CXP83408/83412/83416, CXP83409/83413/83417
80PIN LQFP (PLASTIC)
14.0 ± 0.2
∗ 12.0 ± 0.1
60
61
41
40
0.5 ± 0.08
SONY CODE
EIAJ CODE
JEDEC CODE
CXP83409/83413/83417
60
61
80
1
0.1 ± 0.1
0° to 10°
DETAIL A
+ 0.08
0.18 – 0.03
0.5 ± 0.2
LQFP-80P-L01
∗QFP080-P-1212-A
16.0 ± 0.4
+ 0.4
14.0 – 0.1
A
21
(0.22)
20
1.5 – 0.1
NOTE: Dimension “∗” does not include mold protrusion.
+ 0.2
0.127 – 0.02
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
80PIN QFP (PLASTIC)
41
40
(13.0)
0.5 ± 0.2
+ 0.05
0.1
EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY
0.5g
+ 0.35
1.5 – 0.15
+ 0.1
0.127 – 0.05
0.1
80
1
0.65
SONY CODE
EIAJ CODE
JEDEC CODE
+ 0.15
0.3 – 0.1
QFP-80P-L03
LQFP080-P-1414
21
20
± 0.12
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
– 24 –
+ 0.15
0.1 – 0.1
0° to 10°
EPOXY RESIN
SOLDER PLATING
COPPER / 42 ALLOY
0.6g
(15.0)
0.5 ± 0.2
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