Datasheet CXP82960, CXP82952, CXP82948, CXP82940 Datasheet (Sony)

Page 1

CXP82940/82948/82952/82960

CMOS 8-bit Single Chip Microcomputer

Description

The CXP82940/82948/82952/82960 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, fluorescent display panel controller/driver, I2C bus interface, remote control transmission circuit, remote control reception circuit, and 32kHz timer/counter besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port.

80 pin QFP (Plastic)

Features1

• Wide-range instruction system (213 instructions)

to cover various types of data

— 16-bit arithmetic/multiplication and division/boolean bit operation instructions

• Minimum instruction cycle 250ns at 16MHz operation

(122µs at 32kHz operation)

• Incorporated ROM capacity 40K bytes (CXP82940)

48K bytes (CXP82948) 52K bytes (CXP82952) 60K bytes (CXP82960)

• Incorporated RAM capacity 2048 bytes (including fluorescent display area)

• Periphera; functions

— A/D converter 8-bit, 8-channel, successive approximation method

(Conversion time of 20µs/16MHz)

— Serial interface Buffer RAM incorporated (Auto transfer for 1 to 32 bytes), 1 channel

8-bit, 8-stage FIFO incorporated (Auto transfer for 1 to 8 bytes), 1 channel

— Timers 8-bit timer, 8-bit timer/counter, 19-bit time base timer

32kHz timer/counter

—

Fluorescent display panel controller/driver

— I2C bus interface

— Remote control transmission circuit Auto transmission for 1 to 32 bytes,

— Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO

• Interruption 16 factors, 15 vectors, multi-interruption possible

• Standby mode SLEEP/STOP

• Package 80-pin plastic QFP

• Piggyback/evaluation chip CXP82900 80-pin ceramic QFP

Maximum of 196 segments display possible 1 to 16-digit dynamic display Dimmer function High voltage drive output (40V) Incorporated pull-down resistor (Mask option) Hardware key scan function Maximum of 12 × 8 key matrix supportable

restart function, carrier output function

Structure

Silicon gate CMOS IC

Perchase of Sony’s I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E95130-PK

Page 2

CXP82940/82948/82952/82960

RST

XTAL EXTAL

TEX

PA0 to PA7 8

PB0 to PB7 8

PORT A

CLOCK

GENERATOR

SYSTEM CONTROL

SPC 700

CPU CORE

PORT B

PC0 to PC7 8

PD0 to PD7 8

PORT C

RAM

2048 BYTES

ROM

BYTES

40K/48K/52K/60K

PE0 to PE5 6

PORT D

PE6 to PE7

PF0 to PF3 4

PORT E

PG0 to PG3

PORT F

PORT G

32KHz

TIMER/COUNTER

PRESCALER/

TIME BASE TIMER

Block Diagram

INT3/NMI INT2 INT1 INT0

REF

A/D CONVERTER

AN0 to AN7

RAM

FDP

DRIVER

CONTROLLER/

FDP

T0 to T7

S0 to S11

T8/S19 to T15/S12

RAM

RAMKEY SCAN

BUFFER

REMOCON OUT

RMCO

KR0 to KR7

INTERRUPT CONTROLLER

FIFO

RAM

BUFFER

SERIAL

REMOCON IN

RMC

INTERFACE

SI0

CS0

SO0

UNIT (CH0)

SCK0

FIFO

SERIAL

UNIT (CH1)

INTERFACE

SI1

SO1

SCK1

C BUS

8 BIT TIMER 1

INTERFACE UNIT

8 BIT TIMER/COUNTER 0

SCL0

SCL1

SDA0

SDA1

ADJ

– 2 –

Page 3

Pin Assignment (Top View)

CXP82940/82948/82952/82960

PE1/INT1 PE2/INT2

PE3/INT3/NMI

PE4/RMC

PE5

PE6/RMCO

PE7/TO/ADJ

PB0

PB1/CS0

PB2/SCK0

PB3/SI0

PB4/SO0

PB5/SCK1

PB6/SI1 PB7/SO1 PA0/AN0 PA1/AN1

PA2/AN2

PA3/AN3

PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7

10 11

12 13 14 15 16 17 18 19 20

22 23

2 3 4

5 6 7 8 9

PE0/EC/INT0

PG3

PG2

PG1

PG0

TEX

64 63 62 61 60

58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

43 42 41

T7 T8/S19 T9/S18 T10/S17 T11/S16 T12/S15 T13/S14 T14/S13 T15/S12 S11 S10 S9 S8 PD7/S7 PD6/S6 PD5/S5 PD4/S4 PD3/S3 PD2/S2 PD1/S1 PD0/S0

FDP

V PC7/KR7 PC6/KR6

REF

PF0/SCL0

PF1/SCL1

PF2/SDA0

PF3/SDA1

XTAL

EXTAL

RST

PC1/KR1

PC0/KR0

Note) NC (Pin 75) must be connected to VDD.

– 3 –

PC2/KR2

PC3/KR3

PC4/KR4

PC5/KR5

Page 4

Pin Description

CXP82940/82948/82952/82960

Pin code

PA0/AN0

PA7/AN7

PB0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1

PC0/KR0

PC7/KR7

I/O

I/O/ Analog input

I/O I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output

I/O/Input

(Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins)

(Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins)

(Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins)

Functions

Analog inputs to A/D converter. (8 pins)

Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1).

Serves as key return inputs when operating key scan with fluorescent display panel (FDP) segment signal (8 pins).

PE0/INT0/EC PE1/INT1

PE2/INT2 PE3/INT3/

NMI PE4/RMC PE5

PE6/RMCO

PE7/TO/ADJ

PF0/SCL0 PF1/SCL1

PF2/SDA0 PF3/SDA1

Input/Input/Input Input/Input

Input/Input Input/Input/Input Input/Input

Input Output/Output Output/Output/

Output

Output/I/O

(Port E) 8-bit port. Lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins)

(Port F) 4-bit output port, operating as N-ch open drain output for large current (12mA). (4 pins)

External event inputs for

Inputs for

timer/counter.

external interruption request. (4 pins)

Non-maskable interruption request input.

Remote control reception circuit input.

Carrier output of remote control transmission circuit.

Output for the timer/counter rectangular waves, and 32kHz oscillation dividing frequency.

Transfer clock I/Os for I2C bus interface.

Transfer data I/Os for I2C bus interface.

– 4 –

Page 5

Pin code I/O Functions

(Port G) 8-bit I/O port. I/O can be set in a unit of single bits.

I/OPG0 to PG3

Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (4 pins)

CXP82940/82948/82952/82960

PD0/S0

PD7/S7

T8/S12

T15/S19 T0 to T7 VFDP

EXTAL XTAL TEX TX

RST NC AVDD

AVREF

(Port D)

Output/Output

8-bit output ports. (8 pins)

OutputS8 to S11 FDP segment signal outputs. (4 pins)

Output/Output

Output

Outputs for FDP timing signals/segment signals. (8 pins)

FDP timing signal outputs. FDP voltage supply when incorporated resistor is set by mask option.

Input

Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be

Output Input

input to XTAL. Crystal connectors for 32kHz timer/counter clock oscillation. Set 32kHz

crystal oscillator between TEX and TX. For usage as event input, attach

Output Input

clock source to TEX, and open TX. Low-level active, system reset. NC. Under normal operation, connect to VDD. Positive power supply for A/D converter.

Input

Reference voltage input for A/D converter.

FDP segment signal outputs. (8 pins)

AVSS VDD VSS

A/D converter GND. Positive power supply. GND.

– 5 –

Page 6

Data bus

RD (Port B)

Port B direction

Port B data

Pull-up resistor

"0" when reset

∗

Pull-up transistor approx. 100kΩ

∗

Schmitt input

CS0 SI0 SI1

Not Schmitt input for SI0 and SI1.

Data bus

RD (Port B)

Port B output selection

"0" when reset

∗

Pull-up transistor approx. 100kΩ

∗

Schmitt input

SCK in

Port B data

Port B direction

"0" when reset

Pull-up resistor "0" when reset

SCK OUT

Output enable

I/O Circuit Format for Pins

CXP82940/82948/82952/82960

PA0/AN0

PA7/AN7

8 pins

Port A

Port B

Data bus

Pull-up resistor

"0" when reset

Port A data

Port A direction

"0" when reset

RD (Port A)

Port A input selection

"0" when reset

Circuit format

A/D converter

∗

Input

protection circuit

Input multiplexer

∗

Pull-up transistor approx. 100kΩ

When reset

Hi-Z

PB1/CS0 PB3/SI0 PB6/SI1

3 pins

PB2/SCK0 PB5/SCK1

2 pins

Port B

– 6 –

Hi-Z

Page 7

CXP82940/82948/82952/82960

PB4/SO0 PB7/SO1

2 pins

PC0/KR0

PC7/KR7

Port B

Data bus

Port C

Pull-up resistor "0" when reset

"0" when reset

Port B direction “0” when reset

RD (Port B)

Pull-up resistor

"0" when reset

Port C direction

"0" when reset

Data bus

Output enable

Port B output selection

Port B data

Port C data

Circuit format

∗

Pull-up transistor approx. 100kΩ

∗

∗1

When resetPin

Hi-Z

8 pins

PE0/EC/INT0 PE1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC

5 pins

PE5

1 pin

PE6/RMCO

Port E

Port E output selection

"0" when reset

Reset E data

"1" when reset

RD (Port C)

Key input signal

Schmitt input

Remote control transmission circuit

Output enable

∗

Large current 12mA

∗

Pull-up transistor approx. 100kΩ

EC/INT0 INT1 INT2 INT3/NMI RMC

Data bus

RD (Port E)

Data bus

RD (Port E)

Hi-Z

High level

1 pin

Data bus

RD (Port E)

– 7 –

Page 8

CXP82940/82948/82952/82960

PE7/TO/ADJ

1 pin

PF0/SCL0 PF1/SCL1 PF2/SDA0 PF3/SDA1

4 pins

Port E

Port E data

"1" when reset

ADJ16K

ADJ2K

Port E output selection (upper)

Port E output selection (lower)

"00" when reset

00 01

∗

TO output enable

Port F

SCL, SDA

C output enable

("0" when reset)

Port F data

"1" when reset

SCL, SDA (I2C circuit)

Circuit format

Internal reset signal

MPX

Schmitt input

∗

1

ADJ signal is a frequency dividing output for  32kHz oscillation frequency adjustment.  ADJ2 can be used for buzzer output.

∗

Pull-up transistor approx. 150k Ω.

Large current 12mA

BUS SW

To internal I2C pin (to SCL1 for SCL0)

When resetPin

High level (

with approx. 150kΩ resistor when reset)

Hi-Z

PB0 PG0 to PG3

5 pins

Port B

Port G

Port B data or Port G data

Port B direction or Port G direction

"0" when reset

Data bus

RD (Port B or Port G)

Pull-up resistor

"0" when reset

∗

Pull-up transistor approx. 100kΩ

Hi-Z

– 8 –

Page 9

CXP82940/82948/82952/82960

PD0/S0

PD7/S7

8 pins

S8 to S11 T15/S12

to T8/S19 T0 to T7

20 pins

Port D

Segment output data

Output selection control signal ("0" when reset)

Port D data

Data bus

RD (Port D)

Segment output data Timing output data

Output selection control signal ("0" when reset)

Circuit format

∗

High voltage drive transistor

∗

Pull-down resistor

∗

High voltage drive transistor

∗

Mask option

Pull-down transistor

Mask option

VFDP

When reset

Hi-Z or Low level (when PD resistor is connected)

FDP

Hi-Z or Low level (when PD resistor is connected)

EXTAL XTAL

2 pins

TEX TX

2 pins

RST

1 pin

EXTAL

XTAL

TEX

Pull-up resistor

Mask option

•Diagram shows circuit  composition during oscillation.

•Feedback resistor is removed  during stop, and XTAL  becomes High.

•Diagram shows circuit  composition during oscillation.

•When the operation of the oscillation  circuit is stopped by the software,  the feedback resistor is removed,  and TEX becomes Low level and TX  becomes High level.

Schmitt input

Oscillation

Low level

– 9 –

Page 10

CXP82940/82948/82952/82960

Absolute Maximum Ratings (Vss = 0V reference)

Item Symbol Rating Unit Remarks Supply voltage Input voltage Output voltage

Display output voltage

High level output current

High level total output current

Low level output current

Low level total output current Operating temperature Storage temperature Allowable power dissipation

VDD VIN VOUT

VOD IOH

IODH1 IODH2

∑IOH ∑IODH

IOL IOLC ∑IOL Topr Tstg PD

–0.3 to +7.0 –0.3 to +7.0 –0.3 to +7.0

∗1 ∗1

VDD – 40 to VDD + 0.3

–5

–15 –35 –40

–100

15 20

100

–20 to +75

–55 to +150

600

V V V

mA mA

mA mA mA mA

°C °C

As P channel transistor is open drain, VDD is reference.

All pins excluding outputs∗2(value per pin) Display outputs S0 to S11 (value per pin) Display outputs T0 to T7, and T8/S19 to

T15/S12 (value per pin) Total for all pins excluding display outputs Total for all display outputs Port (value per pin) Large current Port (value per pin)

∗3

Total for all output pins

∗1

VIN and VOUT must not exceed VDD + 0.3V.

∗2

Specifies output current of general-purpose I/O ports.

∗3

The large current drive transistor is the N-CH transistor of Port C (PC) and Port F (PF).

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be

conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.

– 10 –

Page 11

CXP82940/82948/82952/82960

Recommended Operating Conditions (Vss = 0V reference)

Item Symbol Min. Max. Unit Remarks

Guaranteed operation range for high-speed

4.5

5.5

mode (1/2, 1/4 frequency dividing clock) Guaranteed operation range for low-speed

mode (1/16 frequency dividing clock) or

Supply voltage

High level input voltage

Low level input voltage

VDD

VIH VIHS VIHEX VIL VILS VILEX

3.5

2.7

2.5

0.7VDD

0.8VDD

VDD – 0.4

0 0

–0.3

5.5

5.5 VDD VDD

VDD + 0.3

0.3VDD

0.2VDD

0.4

SLEEP mode Guaranteed operation range with TEX

clock Guaranteed data hold range during STOP

∗1

Hysteresis input

EXTAL

∗1

Hysteresis input

EXTAL

∗3

∗2

Operating temperature

∗1

Value for each pin of normal input port (PA, PB0, PB3, PB4, PB6, PB7, PC, PE5, PG).

∗2

Value of the following pins: RST, CS0, SCK0, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC, SCL0, SCL1,

Topr

–20

+75

°C

SDA0, SDA1.

∗3

Specifies only during external clock input.

– 11 –

Page 12

Electrical Characteristics

CXP82940/82948/82952/82960

DC Characteristics

Item Symbol Pins Conditions Min.

High level output current

VOH

PA, PB,

VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA

PC, PE6, PE7, PG

VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA

Low level output current

VOL

PC, PF PF

VDD = 4.5V, IOL = 12.0mA VDD = 4.5V, IOL = 3.0mA

(SCL0, SCL1, SDA0, SDA1)

IIHE

VDD = 4.5V, IOL = 4.0mA VDD = 5.5V, VIH = 5.5V

EXTAL

IILE IIHT

VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 5.5V

TEX

Input current

IILT IILR

RST

VDD = 5.5V, VIL = 0.4V

∗1

VDD = 5.5V, VIL = 0.4V

IIL

PA to PC∗2,

∗2

VDD = 4.5V, VIL = 4.0V

(Ta = –20 to +75°C, Vss = 0V reference)

Typ. Max. Unit

4.0

3.5

0.5

–0.5

0.1 –0.1 –1.5

–3.3

0.4

0.6

1.5

0.4

0.6 40

–40

–10

–400

–50

V V V V V

V V

µA µA µA µA µA µA µA

Display output current

Open drain output leakage current (P-CH Tr off state)

Pull-down resistance

∗3

I/O leakage current

Open drain output leakage current (N-ch Tr off state)

I2C bus switch connection impedance (Output Tr off state)

IOH

ILOL

IIZ

ILOH

RBS

S0 to S11 S12/T15 to

S19/T8, T0 to T7

S0 to S11, S12/T15 to S19/T8, T0 to T7

PA to PC∗2, PG∗2,

∗1

RST

SCL0: SCL1 SDA0: SDA1

VDD = 4.5V VOH = VDD – 2.5V

VDD = 5.5V VOL = VDD – 35V VFDP = VDD – 35V

VDD = 5V VOD – VFDP = 30V

VDD = 5.5V VI = 0, 5.5V

VDD = 5.5V, VOH = 5.5V

VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V

–8

–20

100

–20

270

±10

120

µA

kΩ

µA

Ω

– 12 –

Page 13

CXP82940/82948/82952/82960

Item

Power supply current

Input capacity

∗4

Symbol Pins Conditions Min. Typ. Max. Unit

High speed mode operation

IDD1

IDD2

IDDS1

IDDS2

IDDS3

CIN

VDD

PA to PC, PE0 to PE5, PF, PG, EXTAL, XTAL, TEX, TX, RST

(1/2 frequency dividing clock)

VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF)

VDD = 3V, 32MHz crystal oscillation (C1 = C2 = 47pF)

SLEEP mode

VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF)

VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF)

STOP mode VDD = 5.5V, termination of 16MHz and 32kHz crystal oscillation

Clock 1MHz 0V for all pins excluding measured pins

31 50 mA

40 100 µA

2.5 10 mA

830µA

10 µA

20 pF

∗1

RST specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected.

∗2

PA to PC and PG specify the input current when pull-up resistance has been selected, leakage current when no resistance has been selected.

∗3

When incorporated pull-down resistance has been selected through mask option.

∗4

When all pins are open.

– 13 –

Page 14

AC Characteristics (1) Clock timing

CXP82940/82948/82952/82960

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

System clock frequency

System clock input pulse width System clock input rise time,

fall time Event count input clock

pulse width Event count input clock

rise time, fall time

System clock frequency

Event count input pulse width

Event count input rise time, fall time

∗

tsys indicates the three values below according to the upper two bits (CPU clock selected) of the control

clock registor (address: 00FEH).

Symbol

tXL tXH

tCR tCF

tEH tEL

tER tEF

tTL tTH

tTR tTF

Pin Conditions

XTAL EXTAL

EXTAL

TEX TX

TEX

Fig. 1, Fig. 2 Fig. 1, Fig. 2

External clock drive Fig. 1, Fig. 2

External clock drive Fig. 3

Fig. 3 VDD = 2.7 to 5.5V

Fig. 2 (32kHz clock applied condition)

Fig. 3

Min. Unit

4tsys

∗

Typ.

32.768

Max.

200

MHz

kHz

µs

tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

Fig. 1. Clock timing

EXTAL

Fig. 2. Clock applied conditions

Crystal oscillation Ceramic oscillation

EXTAL

Fig. 3. Event count clock timing

TEX EC

XTAL

1/fc

XH tXLtCF tCR

32kHz clock applied condition Crystal oscillation

External clock

EXTAL

74HC04

XTAL

DD – 0.4V

0.4V

TEX

1 C2

0.8VDD

0.2VDD

EH tELtEF tER

t tTH tTLtTF tTR

– 14 –

Page 15

CXP82940/82948/82952/82960

(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

CS ↓ → SCK delay time

CS ↑ → SCK float delay time

CS ↓ → SO delay time

CS ↑ → SO float delay time

CS High level width

SCK cycle time

SCK High, Low level width

SI input setup time (for SCK ↑)

SI input hold time (for SCK ↑)

SCK ↓ → SO delay time

Symbol Pin

tDCSK

tDCSKF

tDCSO

tDCSOF tWHCS

tKCY

tKH tKL

tSIK

tKSI

tKSO

SCK0

SO0

SO0 CS0

SCK0

SI0

SO0

Chip select transfer mode (SCK = output mode)

Chip select transfer mode

Chip select transfer mode Chip select transfer mode

Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode

Min.

tsys + 200

2tsys + 200

8000/fc

tsys + 100

8000/fc – 100

–tsys + 100

200

2tsys + 100

100

Max. UnitCondition

1.5tsys + 200

2tsys + 200

100

ns ns

ns ns ns ns ns ns ns ns ns ns

Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the

control clock registor (address: 00FEH).

tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

Note 2) CS, SCK, SI and SO correspond to each pin of CS0, SCK0, SI0 and SO0. Note 3) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL.

– 15 –

Page 16

Fig. 4. Serial transfer CH0 timing (CH0)

CXP82940/82948/82952/82960

tWHCS

CSO

SCK0

0.2V

tDCSK

tKCY

tKL tKH

SIK

tKSI

0.8VDD

0.2VDD

0.8VDD

tDCSKF

0.8VDD

SI0

SO0

DCSO tKSO

Input data

Output data

0.8VDD

0.2VDD

tDCSOF

0.8V

0.2VDD

– 16 –

Page 17

CXP82940/82948/82952/82960

Serial transfer (CH1) (SIO mode) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

SCK1 cycle time

SCK1 High, Low level width

SI1 input setup time (for SCK1 ↑)

SI1 input hold time (for SCK1 ↑)

SCK1 ↓→SO1 delay time

Symbol Pin Condition Min. Max. Unit

ns ns ns ns ns ns ns ns ns ns

tKCY

tKH tKL

tSIK

tKSI

tKSO

SCK1

SI1

SO1

Input mode Ouput mode Input mode Ouput mode SCK1 input mode SCK1 ouput mode SCK1 input mode SCK1 ouput mode SCK1 input mode SCK1 ouput mode

2tsys + 200

16000/fc

tsys + 100

8000/fc – 50

100 200

tsys + 200

100

tsys + 200

100

Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the

control clock registor (address: 00FEH).

tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

Note 2) The load condition for the SCK1output mode, SO1 output delay time is 50pF + 1TTL.

Fig. 5. Serial transfer CH1 timing (SIO mode)

SCK1

SI1

tKSO

KCY

tKL tKH

tSIK tKSI

0.8VDD

Input data

0.2V

0.8VDD

0.2VDD

SO1

0.8VDD Output data

0.2VDD

– 17 –

Page 18

CXP82940/82948/82952/82960

Serial transfer (CH1) (Special mode) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Typ. Max. Unit SO1 cycle time SI1 data setup time

SI1 data hold time

∗

tLCY is specified only when the lower two bits (SO1 clock selected) of the serial mode register (CH1) (SIOM1:

tLCY tLSU

tLHD

∗

SO1 SI1

SI1 SI1

104 µs

2 2

µs µs

address 01E2H) is set to 104µs.

Note) The load condition for SO1 is 50pF + 1TTL.

Fig. 6. Serial transfer CH1 timing (Special mode)

SO1

tLCY

Start bit Output data bit

tLCY/2

LCY

0.5VDD

SI1

tLSU tLHD

0.8VDD

Input

data bit

0.2VDD

– 18 –

Page 19

(3) A/D converter characteristics

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)

Item Symbol Pin Condition Min. Typ. Max. Unit

CXP82940/82948/82952/82960

Resolution Linearity error Zero transition

voltage Full-scale

transition voltage Conversion time Sampling time Reference input voltage Analog input voltage

VZT

VFT

tCONV tSAMP

VREF VIAN

∗1

∗2

AVREF AN0 to AN7

IREF

AVREF current

AVREF

IREFS

Fig. 7. Definition of A/D converter terms

Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V

VDD = AVDD = 4.5 to 5.5V

Operation mode SLEEP mode

STOP mode 32kHz operation mode

±3 LSB

–10

4910 mV

160/fADC

12/fADC

4970

∗3

AVDD – 0.5

0.6

70 mV

5030

AVDD

AVREF

1.0

10 µA

Bits

µs µs

V V

FFH FEH

Digital conversion value

01H 00H

Linearity error

Analog input

∗1

VZT: Value at which the digital conversion value change

from 00H to 01H and vice versa.

∗2

VFT: Value at which the digital conversion value changes

from FEH to FFH and vice versa.

∗3

fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (address: 00F9H) and bits 7 (PCK1) and 6 (PCK0) of the clock control register (address: 00FEH).

CKS

FTVZT

PCK1, PCK0

00 (φ = fEX/2) 01 (φ = fEX/4) 11 (φ = fEX/16)

0 (φ /2 selection) fADC = fC/2

fADC = fC/4 fADC = fC/16

1 (φ selection)

fADC = fC fADC = fC/2 fADC = fC/8

– 19 –

Page 20

CXP82940/82948/82952/82960

(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol

External interruption High, Low level width

Reset input Low level width

Fig. 8. Interruption input timing

INT0 INT1 INT2 INT3 NMI (NMI specifies only the falling edge.)

tIH tIL

tRSL

Pin Condition

INT0 INT1 INT2 INT3 NMI

RST

tIH

0.8VDD

tIL

Min. Max.

32/fc

tIL

tIH

Unit

µs

0.2VDD

Fig. 9. RST input timing

RST

tRSL

0.2VDD

– 20 –

Page 21

CXP82940/82948/82952/82960

(5) I2C bus timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item SCL clock frequency Bus-free time before starting transfer Hold time for starting transfer Clock Low level width Clock High level width Setup time for repetitive transfers Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion

∗

The data hold time must exceed 300ns because the SCL rise time (300ns max.) is not taken into consideration.

Symbol Pin Condition Min. Max. Unit

fSLC

tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO

SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL

4.7

4.0

4.7

4.0

4.7 0

250

4.7

100

∗

300

kHz

µs µs µs µs µs µs ns µs ns µs

Fig.10. I2C bus transfer timing

SDA

SCL

BUF

tHD ; STA

tLOW

tFtR

tSU ; DATtHIGHtHD ; DAT

tHD ; STA

tSU ; STA

SU ; STO

PSt

Fig.11. Recommended circuit example for I2C device

I2C

device

SDA0 (or SDA1)

SCL0 (or SCL1)

I2C

device

RS RS RS RS RP RP

• Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).

• Serial resistance (Rs = 300Ω or less) of SDA0 (or SDA1) and SCL0 (SCL1) reduces spike noise caused by

CRT flash-over.

– 21 –

Page 22

Appendix

Fig. 12.Recommended oscillation circuit

CXP82940/82948/82952/82960

Manufacturer

RIVER ELETEC CO., LTD.

KINSEKI LTD.

(i)

EXTAL

AAA

1 C2

HC-49/U03

HC-49/U (-S)

XTAL

Model

fc (MHz)

8.00

10.00

12.00

16.00

8.00

10.00

12.00

16.00

32.768kHz

(ii)

TEX

AAA

C1 (pF) C2 (pF) Rd (Ω)

16 (12) 16 (12) 16 (12)

12 12 12 12 0

30 18

16 (12)

470k

Circuit

example

(i)

(ii)

Mask Option Table

Item Reset pin pull-up resistance Non-existent High voltage drive output port pull-down resistance

Non-existent

Content

Existent

Existent (Selectable for each pin)

– 22 –

Page 23

Characteristics Curve

CXP82940/82948/82952/82960

(fc = 16MHz, Ta = 25°C, Typical)

50 30

20 10

0.5

(500µA)

– Supply current [mA]

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

IDD vs. VDD

34 657

VDD – Supply voltage [ V ]

1/2 dividing mode 1/4 dividing mode

1/16 dividing mode SLEEP mode

32kHz mode (instruction)

32kHz SLEEP mode

IDD vs. fc

(VDD = 5V, Ta = 25°C, Typical)

– Supply current [mA]

02 10 15

501

Frequency [MHz]

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

SLEEP mode

– 23 –

Page 24

Package Outline Unit: mm

CXP82940/82948/82952/82960

80PIN QFP (PLASTIC)

23.9 ± 0.4 + 0.4

+ 0.1

0.15 – 0.05

20.0 – 0.1

0.15

+ 0.4

16.3

17.9 ± 0.4

14.0 – 0.1

0.8

0.12

0.35 – 0.1

+ 0.15

+ 0.35

2.75 – 0.15

+ 0.2

0.1 – 0.05

0.8 ± 0.2

SONY CODE

EIAJ CODE

JEDEC CODE

0° to 10°

DETAIL A

∗QFP080-P-1420-A

QFP-80P-L01

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT

– 24 –

EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY

1.6g