Datasheet CXP82860, CXP82852, CXP82840, CXP82832 Datasheet (Sony)

CXP82832/82840/82852/82860

CMOS 8-bit Single Chip Microcomputer

Description

The CXP82832/82840/82852/82860 is a CMOS 8­bit single chip microcomputer integrating on a single
chip an A/D converter, serial interface, timer/counter,
time base timer, capture timer/counter, fluorescent
display panel controller/driver, remote control
reception circuit, and PWM output besides the basic
configurations of 8-bit CPU, ROM, RAM, and I/O port.

The CXP82832/82840/82852/82860 also provides
sleep/stop function that enables lower power
consumption.

Features

• Wide-range instruction system (213 instructions) to cover various types of data

— 16-bit arithmetic/multiplication and division/boolean bit operation instructions

• Minimum instruction cycle 400ns at 10MHz operation

(122µs at 32kHz operation)

• Incorporated ROM capacity 32K bytes (CXP82832)

40K bytes (CXP82840)
52K bytes (CXP82852)
60K bytes (CXP82860)

• Incorporated RAM capacity 1536 bytes (including fluorescent display area)

• Peripheral functions

— A/D converter 8 bits, 8 channels, successive approximation method

(Conversion time of 32µs/10MHz)

— Serial interface 8-bit, 8-stage FIFO incorporated

(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock synchronized type, 1 channel

— Timers 8-bit timer, 8-bit timer/counter, 19-bit time base timer

16-bit capture timer/counter, 32kHz timer/counter

— Fluorescent display panel controller/driver Supports the universal grid fluorescent display panel.

High voltage drive output port of 56 pins (40V)
Maximum of 640 segments display possible
Display timing number of 1 to 20
Dimmer function
Incorporated pull-down resistor (Mask option)
Hardware key scan function (Maximum of 16 × 8 key matrix

supportable)
— Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO
— PWM output 14 bits, 1 channel

• Interruption 16 factors, 15 vectors, multi-interruption possible

• Standby mode SLEEP/STOP

• Package 100-pin plastic QFP

• Piggyback/evaluation chip CXP82800 100-pin ceramic QFP

Structure

Silicon gate CMOS IC

100 pin QFP (Plastic)

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E94Y08B74

CXP82832/82840/82852/82860

SS
DD

V
V

RST
XTAL

EXTAL

TX
TEX

PA0 to PA7
8

CL OCK GENERAT OR

SPC 700

PORT A

/SYSTEM CONTROL

CPU CORE

PB0 to PB7
8

PC0 to PC7
8

PORT B

RAM

PD0 to PD7
8

PORT C

PORT D

PE0 to PE5
6

PE6 to PE7
2

PF0 to PF7
8

PORT E

PG0 to PG7
8

PORT F

PH0 to PH7
8

PORT G

PORT H

32KHz

1536 BYTES

TIMER/COUNTER

ROM

BYTES

/52K/60K

32K/40K

PRESCALER/

TIME BASE TIMER

SS

2

INT3/NMI

INT2

INT1

INTERRUP T CONTROLLER

INT0

2

REF

AV

RAM

RAMKEY SCAN

FIFOREMOCON

FIFO

2

2

AV

A/D CONVERT ER

8

AN0 to AN7

FDP

DRIVER

CONTROLLER/

8

16

32

FDP

V

A16 to A23

A24 to A55

1 4 B IT PWM G ENERATO R

8

RMC

PWM

KR0 to KR7

UNIT 0

SERIAL

INTERFACE

SERIAL INTERFACE UNIT 1

SI0

CS0

SI1

SO0

SCK0

SO1

SCK1

8 BIT TI ME R 1

16 BIT CAPTURE

TIMER/COUNTER 2

8 BIT T IMER/ COUNTE R 0

EC0

TO

CINT

EC1

ADJ

G0/A0 to G1 5 /A 1 5

Block Diagram

– 2 –

Pin Assignment (Top View)

CXP82832/82840/82852/82860

G1/A1
G0/A0

NC

PE0/EC0/INT0
PE1/EC1/INT1

PE2/INT2

PE3/INT3/NMI

PE4/RMC

PE5

PE6/PWM

PE7/TO/ADJ

PC0/KR0
PC1/KR1
PC2/KR2
PC3/KR3
PC4/KR4
PC5/KR5
PC6/KR6
PC7/KR7

PB0/CINT

PB1/CS0

PB2/SCK0

PB3/SI0

PB4/SO0

PB5/SCK1

PB6/SI1

PB7/SO1

AVREF
PA0/AN0
PA1/AN1

10
11
12
13
14
15
16
17
18
19
20

23

26

29
30

21
22

24
25

27
28

DD

V

G12/A12

G11/A11

G10/A10

G9/A9

G8/A8

G7/A7

G6/A6

G5/A5

G4/A4

G3/A3

G2/A2

99

100

1
2
3
4
5
6
7
8
9

98

97

96

95

94

93

92

91

90

89

88

G14/A14

G13/A13

86

87

G15/A15

85

A16

84

A17

83

A18

82

A19

81

A20

80
79
78
77
76
75
74

73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A21
A22
A23
PH7/A24
PH6/A25
PH5/A26
PH4/A27
PH3/A28
PH2/A29
PH1/A30
PH0/A31
PG7/A32
PG6/A33
PG5/A34
PG4/A35
PG3/A36
PG2/A37
PG1/A38
PG0/A39
PF7/A40
PF6/A41
PF5/A42
PF4/A43
PF3/A44
PF2/A45
PF1/A46
PF0/A47
PD7/A48
PD6/A49
PD5/A50

32

31

PA2/AN2

33

34

PA4/AN4

PA3/AN3

35

PA5/AN5

37

36

PA7/AN7

PA6/AN6

SS

AV

38

39

RST

40

XTAL

EXTAL

41

Vss

42

TX

43

44

TEX

Note) 1. NC (Pin 3) must be connected to VDD.

2. VDD (Pins 44 and 89) must be connected to VDD.

– 3 –

DD

V

45

FDP

V

46

48

47

PD1/A54

PD0/A55

49

50

PD3/A52

PD2/A53

PD4/A51

Pin Description

Pin code I/O Functions

(Port A)
8-bit I/O port. I/O can be set in a

PA0/AN0

to

PA7/AN7

I/O/
Analog input

unit of single bits. Incorporation
of the pull-up resistor can be set
through the software in a unit of
4 bits.
(8pins)

CXP82832/82840/82852/82860

Analog inputs to A/D converter.
(8 pins)

PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1

PC0/KR0

to

PC7/KR7

PD0/A55

to

PD7/A48
PE0/INT0/

EC0
PE1/INT1/

EC1
PE2/INT2
PE3/INT3/

NMI
PE4/RMC
PE5

I/O/Input
I/O/Input
I/O/I/O
I/O/Input
I/O/Output
I/O/I/O
I/O/Input
I/O/Output

I/O/Input

Output/Output

Input/Input/Input

Input/Input/Input
Input/Input
Input/Input/Input
Input/Input

Input

(Port B)
8-bit I/O port. I/O can be set in a
unit of single bits. Incorporation
of the pull-up resistor can be set
through the software in a unit of
4 bits.
(8 pins)

(Port C)
8-bit I/O port. I/O can be set in a
unit of single bits. Can drive
12mA sync current.
Incorporation of the pull-up
resistor can be set through the
software in a unit of 4 bits.
(8 pins)

(Port D)
8-bit output port.
(8 pins)

(Port E)
8-bit port. Lower 6 bits are for
inputs; upper 2 bits are for
outputs.
(8 pins)

Capture input to 16-bit timer/counter.
Chip select input for serial interface (CH0).
Serial clock I/O (CH0).
Serial data input (CH0).
Serial data output (CH0).
Serial clock I/O (CH1).
Serial data input (CH1).
Serial data output (CH1).

Serves as key return inputs when
operating key scan with fluorescent
display panel (FDP) segment signal.

(8 pins)

FDP segment signal (anode
connection) outputs.

External event inputs
Inputs for
external

for timer/counter.

(2 pins)
interruption
request.
(4 pins)

Non-maskable
interruption request input.

Remote control reception circuit input.

PE6/PWM

PE7/TO/ADJ

PF0/A47

to

PF7/A40

Output/Output
Output/Output/

Output

Output/Output

(Port F)
8-bit output port.
(8pins)

14-bit PWM output.
Output for the 16-bit timer/counter

rectangular waves, and 32kHz
oscillation frequency division.

FDP segment signal (anode
connection) outputs.

– 4 –

Pin code I/O Functions

CXP82832/82840/82852/82860

PG0/A39

to

PG7/A32
PH0/A31

to

PH7/A24

G0/A0

to

G15/A15
VFDP

EXTAL
XTAL
TEX
TX
RST

NC

Output/Output

Output/Output

OutputA16 to A23

Output/Output

Input
Output
Input
Output

Input

(Port G)
8-bit output port.
(8 pins)

(Port H)
8-bit output port.
(8 pins)

FDP segment signal (anode
connection) outputs.

(8 pins)
FDP segment signal (anode

connection) outputs.
(8 pins)

FDP segment signal (anode connection) outputs.

(8 pins)

Outputs for FDP timing signals (grid connection)/segment signals (anode
connection).
(16 pins)

FDP voltage supply when incorporated pull-down (PD) resistor is set by
mask option.

Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.

Crystal connectors for 32kHz timer/counter clock oscillation. For usage
as event input, input to TEX, and open TX.

Low-level active, system reset

NC. Under normal operation, connect to VDD.
AVREF
AVSS
VDD

VSS

Input

Reference voltage input for A/D converter.

A/D converter GND.

VCC supply.

GND.

– 5 –

I/O Circuit Format for Pins

CXP82832/82840/82852/82860

Pin

PA0/AN0

to

PA7/AN7

8 pins

PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1

Port A

Port B

Data bus

Data bus

Pull-up resistor
"0" when reset

Port A data

Port A direction

"0" when reset

RD (Port A)

Port A input selection

"0" when reset

A/D converter

Pull-up resistor
"0" when reset

Port B data

Port B direction

"0" when reset

Circuit format

Input multiplexer

∗

IP

Input protection circuit

∗

Pull-up transistor approx. 100kΩ

∗

IP

Schmitt input

When reset

Hi-Z

Hi-Z

4 pins

PB2/SCK0
PB5/SCK1

2 pins

Port B

Pull-up resistor
"0" when reset

Serial clock output enable

Port B output selection

"0" when reset

Port B data

Port B direction

"0" when reset

Data

bus

RD (Port B)

RD (Port B)

SCK OUT

SCK in

CINT

CS0

SI0
SI1

∗

Pull-up transistor approx. 100kΩ

Schmitt input

∗

Pull-up transistor approx. 100kΩ

∗

Hi-Z

IP

– 6 –

CXP82832/82840/82852/82860

Pin

PB4/SO0
PB7/SO1

2 pins

PC0/KR0

to

PC7/KR7

Port B

Pull-up resistor
"0" when reset

Serial data output enable

Port B output selection

"0" when reset

Port B data

Port B direction

"0" when reset

Data

bus

RD (Port B)

Port C

Pull-up resistor

"0" when reset

Port C data

Port C direction

"0" when reset

SO

Circuit format

∗

IP

∗

Pull-up transistor approx. 100kΩ

∗

2

∗

1

IP

When reset

Hi-Z

Hi-Z

8 pins

PE0/EC0/INT0
PE1/EC1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC

5 pins

PE5

1 pin

Data bus

Port E

Port E

RD (Port C)

Key input signal

IP

IP

Schmitt input

∗

1

Large current 12mA

∗

2

Pull-up transistor approx. 100kΩ

EC0/INT0
EC1/INT1
INT2
INT3/NM1
RMC

Data bus

RD (Port E)

Data bus

RD (Port E)

Hi-Z

Hi-Z

– 7 –

CXP82832/82840/82852/82860

Pin

PE6/PWM

1 pin

PE7/TO/ADJ

Port E

PWM

Port E output selection

"0" when reset

Port E data

"1" when reset

Data bus

RD (Port E)

Port E

Port E data

"1" when reset

Port E output selection (upper)
Port E output selection (lower)

"00" when reset

TO

∗

1

ADJ16K

∗

2

ADJ2K

TO output enable

Circuit format

Output enable

Internal reset signal

00
01

MPX

10
11

∗

2

∗

1

ADJ signal is a frequency dividing
output for 32kHz oscillation frequency adjustment.
ADJ2 can be used for buzzer output.

∗

2

Pull-up transistor approx. 150kΩ

When reset

High level

High level
(with approx.
150kΩ
resistor when
reset)

1 pin

PD0/A55

to
PD7/A48
PF0/A47

to
PF7/A40

PG0/A39

to

PG7/A32

PH0/A31

to
PH7/A24

32 pins

Port D

Port F
Port G
Port H

Segment output data

Output selection control signal

("0" when reset)

Port D, F, G and H data

"0" when reset

Data bus

RD (Ports D, F, G and H)

OP

Pull-down resistor

∗

High voltage drive transistor

∗

Mask
option

FDP

V

Hi-Z or Low
level (when
PD resistor is
connected)

– 8 –

CXP82832/82840/82852/82860

Pin

A16 to A23

8 pins

G0/A0

to

G15/A15

Segment output data

Output selection control signal

("0" when reset)

Segment output data

Timing output data

Output selection control signal

("0" when reset)

Circuit format

Mask option

Pull-down resistor

Mask option

Pull-down resistor

∗

OP

V

FDP

∗

High voltage drive transistor

∗

OP

V

FDP

When reset

Hi-Z or
Low level
(when PD
resistor is
connected)

Hi-Z or
Low level
(when PD
resistor is
connected)

16 pins

EXTAL

XTAL

2 pins

TEX

TX

2 pins

EXTAL

XTAL

TEX

TX

∗

High voltage drive transistor

• Diagram shows circuit
composition during

IP

IP

IP

IP

oscillation.

• Feedback resistor is
removed and XTAL
becomes High level
during stop.

• Diagram shows circuit
composition during
oscillation.

• When the operation of the
oscillation circuit is
stopped by the software,
the feedback resistor is
removed, and TEX and
TX become Low level and
High level respectively.

Oscillation

Oscillation

RST

1 pin

Mask option

Pull-up resistor

OP

OP

– 9 –

Low level

IP

Schmitt input

CXP82832/82840/82852/82860

Absolute Maximum Ratings (Vss = 0V reference)

Item Symbol Rating Unit Remarks
Supply voltage
A/D converter GND voltage
A/D converter reference

voltage
FDP display supply voltage
Input voltage
Output voltage
Display output voltage

High level output current

High level total output
current

Low level output current

Low level total output current

VDD
AVSS

AVREF
VFDP

VIN
VOUT
VOD
IOH
IODH1

IODH2

∑IOH
∑IODH

IOL
IOLC
∑IOL

–0.3 to +7.0
–0.3 to +0.3

–0.3 to +7.0

–40∗2to +7.0

–0.3 to +7.0
–0.3 to +7.0

–40∗2to +7.0

–5

–15
–50
–30

–120

15
20

100

∗1

∗1
∗1

∗1

∗1

V
V

V
V

V
V
V

All pins excluding outputs∗3(value per pin)

mA

Display outputs A20 to A55 (value per pin)

mA

Display outputs G0/A0 to G15/A15, and

mA

A16 to A19 (value per pin)
Total for all pins excluding display outputs

mA

Total for all display outputs

mA

Port (value per pin)

mA

Large current port (value per pin)

mA

Total for all output pins

mA

∗4

Operating temperature
Storage temperature
Allowable power dissipation

∗1

VIN, VOUT, VOD and AVREF must not exceed VDD + 0.3V.

∗2

VFDP and VOD must not exceed VDD – 40V.

∗3

Specifies output current of general-purpose I/O ports.

∗4

The large current drive transistor is the N-CH transistor of Port C (PC).

Topr
Tstg
PD

–20 to +75

–55 to +150

600

°C
°C

mW

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be

conducted under the recommended operating conditions. Exceeding these conditions may adversely affect
the reliability of the LSI.

– 10 –

CXP82832/82840/82852/82860

Recommended Operating Conditions (Vss = 0V reference)

Item Symbol Min. Max. Unit Remarks

Guaranteed operation range during
high-speed mode

4.5

5.5

V

(1/2 and 1/4 frequency dividing clock)
Guaranteed operation range low-speed

mode or SLEEP mode

Supply voltage

VDD

3.5

5.5

V

(1/16 frequency dividing clock)
Guaranteed operation range with TEX

V

clock
Guaranteed data hold range during STOP

V

∗1

V

Hysteresis input

V

EXTAL

V

∗1

V

Hysteresis input

V

EXTAL

V

∗3

∗3

∗2

∗2

High level input
voltage

Low level input
voltage

VIH
VIHS
VIHEX
VIL
VILS
VILEX

2.7

2.5

0.7VDD

0.8VDD

VDD – 0.4

0
0

–0.3

5.5

5.5
VDD
VDD

VDD + 0.3

0.3VDD

0.2VDD

0.4

Operating temperature

∗1

Value for each pin of normal input port (PA, PB4, PB7, PC).

∗2

Value of the following pins: RST, CINT, CS0, SCK0, SCK1, SI0, SI1, EC0/INT0, EC1/INT1, INT2,

Topr

–20

+75

°C

INT3/NMI, RMC.

∗3

Specifies only during external clock input.

– 11 –

Electrical Characteristics

CXP82832/82840/82852/82860

DC Characteristics

Item Symbol Pins Conditions Min.

High level
output current

Low level
output current

VOH

PA, PB, PC,
PE6, PE7

VOL

PC

IIHE

VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V

EXTAL

IILE
IIHT

VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 5.5V

TEX

Input current

IILT
IILR

IIL

∗1

RST

PA to PC

VDD = 5.5V, VIL = 0.4V

VDD = 5.5V, VIL = 0.4V

∗2

VDD = 4.5V, VIL = 4.0V

A20 to A55

Display output
current

IOH

G0/A0 to
G15/A15

VDD = 4.5V
VOH = VDD –2.5V

A16 to A19

(Ta = –20 to +75°C, VSS = 0V reference)

Typ.

4.0

3.5

0.5

–0.5

0.1
–0.1
–1.5

–3.3

–8

–30

Max. Unit

V
V

0.4

0.6

1.5
40

–40

10

–10

–400

–50

V
V

V
µA
µA
µA
µA
µA
µA
µA

mA

mA

Open drain
output leakage
current (P-CH
Tr off state)

Pull-down
resistor

∗3

I/O leakage
current

ILOL

RL

IIZ

G0/A0 to
G15/A15
A16 to A55

G0/A0 to
G15/A15
A16 to A55

PA to PC

∗2

PE0 to PE5

∗1

RST

VDD = 5.5V
VOL = VDD – 35V
VFDP = VDD – 35V

VDD = 5V
VOD – VFDP = 30V

VDD = 5.5V
VI = 0, 5.5V

60

100

–20

270

±10

µA

kΩ

µA

– 12 –

CXP82832/82840/82852/82860

Item Symbol Pins Conditions Min. Typ. Max. Unit

High speed mode operation

IDD1

(1/2 frequency dividing clock)

VDD = 5.5V, 10MHz crystal

23

(19)

50

(40)

mA

oscillation (C1 = C2 = 15pF)

44

(37)

2.3

(2.1)

100 µA

8mA

Power supply
current

∗4

IDD2

IDDS1

VDD

VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)

SLEEP mode

VDD = 5.5V, 10MHz crystal
oscillation (C1 = C2 = 15pF)

IDDS2

IDDS3

VDD = 3V, 32kHz crystal
oscillation (C1 = C2 = 47pF)

STOP mode
V

DD = 5.5V, termination of 10MHz

and 32kHz crystal oscillation

10 30 µA

10 µA

PA to PC,

Input
capacity

CIN

PE0 to 5,
XTAL,
EXTAL,

Clock 1MHz
0V for all pins excluding
measured pins

10

20

TEX,RST

∗1

RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.

∗2

PA to PC pins specify the input current when pull-up resistor has been selected; leakage current when no
resistor has been selected.

∗3

When incorporated pull-down resistor has been selected through mask option.

∗4

When all pins are open.

Note) The values in paren thesis are for the CXP82832 and CXP82840.

pF

– 13 –

A

A

A

AC Characteristics
(1) Clock timing

CXP82832/82840/82852/82860

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Conditions Min. Unit

System clock frequency

System clock input pulse width
System clock input rise time,

fall time
Event count input clock

pulse width
Event count input clock

rise time, fall time

System clock frequency

Event count input
pulse width

Event count input rise time,
fall time

∗1

tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control

clock registor (CLC: 00FEH).

fC

tXL
tXH

tCR
tCF

tEH
tEL

tER
tEF

fC

tTL
tTH

tTR
tTF

XTAL
EXTAL

EXTAL

EXTAL
EC0,

EC1
EC0,

EC1
TEX

TX

TEX

TEX

Fig. 1, Fig. 2
Fig. 1, Fig. 2

External clock drive
Fig. 1, Fig. 2

External clock drive
Fig. 3

Fig. 3
VDD = 2.7 to 5.5V

Fig. 2 (32kHz clock
applied condition)

Fig. 3

Fig. 3

1

37.5

tsys + 50

10

∗

1

Typ.

32.768

Max.

10

200

20

20

tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

MHz

ns

ns

ns

ms

kHz

µs

ms

Fig. 1. Clock timing

EXTAL

Fig. 2. Clock applied conditions

Crystal oscillation
Ceramic oscillation

EXTAL

AA

1 C2

C

Fig. 3. Event count clock timing

TEX
EC0
EC1

XTAL

1/fc

t

XH tXLtCF tCR

32kHz clock applied condition

External clock

EXTAL

AA

74HC04

XTAL

Crystal oscillation

TEX

AA

C

1

TX

DD – 0.4V

V

0.4V

C2

0.8VDD

0.2VDD

EH tELtEF tER

t
tTH tTLtTF tTR

– 14 –

CXP82832/82840/82852/82860

(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

CS0 ↓→SCK0
delay time

CS0 ↑→SCK0
float delay time

CS0 ↓→SO0
delay time

CS0 ↑→SO0
float delay time

CS0 High level width

SCK0 cycle time

SCK0
High, Low level width

SI0 input set-up time
(for SCK0 ↑)

SI0 input hold time
(for SCK0 ↑)

SCK0 ↓→SO0
delay time

Symbol Pin Min.

tDCSK

tDCSKF

tDCSO

tDCSOF
tWHCS

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK0

SCK0

SO0

SO0
CS0

SCK0

SCK0

SI0

SI0

SO0

Chip select transfer mode
(SCK0 = output mode)

Chip select transfer mode
(SCK0 = output mode)

Chip select transfer mode

Chip select transfer mode
Chip select transfer mode

Input mode
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode

tsys + 200

2tsys + 200

16000/fc

tsys + 100

8000/fc – 50

100
200

tsys + 200

100

Max. UnitCondition

tsys + 200

tsys + 200

tsys + 200

tsys + 200

tsys + 200

100

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the

control clock registor (CLC: 00FEH).

tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.

– 15 –

Fig. 4. Serial transfer CH0 timing

CS0

DD

0.2V

CXP82832/82840/82852/82860

tWHCS

0.8VDD

tKCY

SCK0

SI0

tDCSK

tKL tKH

t

SIK tKSI

Input data

0.8VDD

0.2VDD

0.8VDD

0.2VDD

tDCSKF

0.8VDD

SO0

t

DCSO tKSO tDCSOF

Output data

– 16 –

0.8V

DD

0.2VDD

CXP82832/82840/82852/82860

Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

SCK1 cycle time

SCK1
High, Low level width

SI1 input set-up time
(for SCK1 ↑)

SI1 input hold time
(for SCK1 ↑)

Symbol Pin Condition Min. Max. Unit

tKCY

tKH
tKL

tSIK

tKSI

SCK1

Input mode
Ouput mode
Input mode

SCK1

Ouput mode
SCK1 input mode

SI1

SCK1 ouput mode
SCK1 input mode

SI1

SCK1 ouput mode

1000

16000/fc

400

8000/fc – 50

100
200
200
100

SCK1 input mode

SCK1 ↓→SO1 delay time

tKSO

SO1

SCK1 ouput mode

Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.

Fig. 5. Serial transfer CH1 timing

tKCY

200
100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

SCK1

SI1

SO1

tKL tKH

tSIK

Input data

tKSO

0.8VDD

0.2VDD

0.8VDD

0.2VDD

tKSI

0.8VDD

0.2VDD

Output data

– 17 –

(3) A/D converter characteristics

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to VDD, Vss = AVSS = 0V reference)

Item Symbol Pin Condition Min. Typ. Max. Unit

CXP82832/82840/82852/82860

Resolution
Linearity error

Zero transition
voltage

Full-scale
transition voltage

Conversion time
Sampling time
Reference input voltage
Analog input voltage

∗1

VZT

∗2

VFT

tCONV
tSAMP

VREF
VIAN

AVREF

AN0 to AN7

IREF

AVREF current

AVREF

IREFS

Fig. 6. Definition of A/D converter terms

Ta = 25°C
VDD = AVREF = 5.0V
VSS = AVSS = 0V

Operation mode
SLEEP mode

STOP mode
32kHz operation mode

8

±3 LSB

–10

4910 mV

160/fADC

12/fADC

∗3

∗3

10

4970

VDD – 0.5

0

0.6

70 mV

5030

VDD

AVREF

1.0

10 µA

Bits

µs
µs

V
V

mA

FFH
FEH

Digital conversion value

01H
00H

Linearity error

Analog input

∗

1

VZT: Value at which the digital conversion value changes

  from 00 H to 01H and vice versa.

∗

2

VFT: Value at which the digital conversion value changes

  from FE H to FFH and vice versa.

∗

3

fADC indicates the below values due to the contents of bit 6
(CKS) of A/Dcontrol register (ADC: 00F9H) and bits 7 (PCK1)
and 6 (PCK0) of clock control register (CLC: 00FEH).

VFTVZT

PCK1, PCK0

00 (φ = fEX/2)
01 (φ = fEX/4)
11 (φ = fEX/16)

CKS

0 (φ/2 selection)

fADC = fC/2
fADC = fC/4
fADC = fC/16

1 (φ selection)

fADC = fC
fADC = fC/2
fADC = fC/8

– 18 –

CXP82832/82840/82852/82860

(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Max. Unit

INT0
External interruption
High, Low level width

tIH
tIL

INT1

INT2

1

µs

NMI/INT3
Reset input Low level width

Fig. 7. Interruption input timing

INT0
INT1
INT2
NMI/INT3
(NMI specifies only for the
falling edge)

Fig. 8. RST input timing

tRSL

RST

tIH tIL

0.8VDD

tIL tIH

tRSL

32/fc

µs

0.2VDD

RST

0.2VDD

– 19 –

A

A

A

A

A

Appendix

Fig. 9. Recommended oscillation circuit

CXP82832/82840/82852/82860

(i) Main clock

EXTAL

EXTAL

1

C

Manufacturer

MURATA
MFG
CO., LTD.

RIVER
ELETEC
CO., LTD

KINSEKI
LTD.

XTAL

AA

AA

XTAL

CSA4.19MG
CSA8.00MTZ
CSA10.0MTZ
CST4.19MGW
CST8.00MTW
CST10.0MTW

HC-49/U03

HC-49/U (-S)

Rd

C

2

Model

(ii) Main clock

EXTAL

fc (MHz)

4.19

8.00

10.00

∗
∗
∗

4.19

8.00

10.00

4.19

8.00

10.00

4.19

8.00

10.00

XTAL

AA

Rd

1 C2

C

C1 (pF) C2 (pF) Rd (Ω)

30

12

27

20 20

30

12

27

(iii) Sub clock

TEX

EXTAL

AAA

AAA

C

1

Circuit

example

0

0

0

(i)

(ii)

(i)

TX

XTAL

Rd

C2

P3

Models marked with an asterisk (∗) have the built-in ground capacitance (C1, C2).

Mask option table

Item
Reset pin pull-up resistor Non-existent
High voltage drive output port pull-down resistor

32.768kHz

50 22

Non-existent

– 20 –

1M

Content

(iii)

Existent
Existent

Characteristics Curve

CXP82832/82840

(fc = 10MHz, Ta = 25°C, Typical)

20.0

10.0

5.0

1.0

0.5

IDD vs. VDD

CXP82832/82840/82852/82860

IDD vs. fc

(VDD = 5V, Ta = 25°C, Typical)

1/2 dividing mode

1/4 dividing mode

20

1/2 dividing mode

1/16 dividing mode
SLEEP mode

15

– Supply current [mA]

DD

I

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

CXP82852/82860

20.0

10.0

5.0

1.0

32kHz mode
(instruction)

32kHz
SLEEP mode

3

45

DD – Supply voltage [V]

V

6

IDD vs. VDD

(fc = 10MHz, Ta = 25°C, Typical)

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode
SLEEP mode

10

– Supply current [mA]

DD

I

5

72

0

51015

fc – System clock [MHz]

1/4 dividing mode

1/16 dividing mode

SLEEP mode

IDD vs. fc

(VDD = 5V, Ta = 25°C, Typical)

20

15

1/2 dividing mode

0.5

– Supply current [mA]

DD

I

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

V

DD – Supply voltage [V]

3

45

32kHz mode
(instruction)

32kHz
SLEEP mode

72

6

– 21 –

10

– Supply current [mA]

DD

I

5

0

51015

fc – System clock [MHz]

1/4 dividing mode

1/16 dividing mode

SLEEP mode

Package Outline Unit: mm

100PIN QFP (PLASTIC)

23.9 ± 0.4
+ 0.4

20.0 – 0.1

+ 0.4

17.9 ± 0.4

14.0 – 0.01

+ 0.1

0.15 – 0.05

15.8 ± 0.4

CXP82832/82840/82852/82860

A

0.65

SONY CODE
EIAJ CODE

JEDEC CODE

0° to 15°

±0.12

DETAIL A

QFP-100P-L01
∗QFP100-P-1420-A

M

0.15

(16.3)

0.8 ± 0.2

2.75 – 0.15

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE WEIGHT

EPOXY RESIN
SOLDER PLATING

COPPER / 42 ALLOY

1.4g

+ 0.35

– 22 –