Datasheet CXP81960, CXP81952 Datasheet (Sony)

CXP81952/81960

CMOS 8-bit Single Chip Microcomputer

Description

The CXP81952/81960 is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit, PWM generator, PWM for tuner, 32kHz timer/event counter, remote control receiving circuit, general purpose prescaler, and external signal, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip.

Also the CXP81952/81960 provides sleep/stop function which enables to lower power consumption and ultra-low speed instruction mode in 32kHz operation.

100 pin QFP (PIastic) 100 pin LQFP (PIastic)

Structure

Silicon gate CMOS IC

Features

• A wide instruction set (213 instructions) which cover various types of data

— 16-bit operation/multiplication and division/boolean bit operation instructions

• Minimum instruction cycle 250ns at 16MHz operation

122µs at 32kHz operation

• Incorporated ROM capacity 52K bytes (CXP81952), 60K bytes (CXP81960)

• Incorporated RAM capacity 2048 bytes

• Peripheral functions

— A/D converter 8-bit, 12-channel, successive approximation system

(Conversion time 20.0µs/16MHz)

— Serial Interface Incorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel

Incorporated 8-bit and 8-stage FIFO for data (1 to 8 bytes auto transfer) 1-channel

— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer,

32kHz timer/counter

— High precision timing pattern generator PPG 19-pin 32-stage programmable

RTG 5-pin 2-channel

— PWM/DA gate output PWM 12-bit, 2-channel (Repetitive frequency 62kHz/16MHz)

DA gate pulse output 13-bit, 4-channel — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14-bit, 1-channel — Remote control receiving circuit 8-bit pulse measurement counter with on-chip, 6-stage FIFO — General purpose prescaler 7-bit (PG5 input frequency divided, FRC capture possible)

• Interruption 20 factors, 15 vectors, multi-interruption possible

• Standby mode SLEEP/STOP

• Package 100-pin plastic QFP/LQFP

• Piggyback/evaluation chip CXP81900 100-pin ceramic QFP/LQFP

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E95110-ST

CXP81952/81960

Vss V

DD

MP RST XTAL EXTAL TX TEX

PE1/INT2 PI4/INT1/NMI

PE0/INT0

PA0 to PA7

8

PORT A

CLOCK

GENERATOR/

SYSTEM CONTROL

SPC700

CPU CORE

NMI

2

PB0 to PB7

PC0 to PC7

8

PORT B8PORT C

PD0 to PD7

PE0 to PE1

PE2 to PE7

2

8

PORT D

6

PORT E

RAM

2048 BYTES

ROM

52K/60K BYTES

INTERRUPT CONTROLLER

PF4 to PF7

PF0 to PF3

4

PG0 to PG7

PH0 to PH7

4

PORT F8PORT G8PORT H7PORT I

32kHz

PRESCALER/

TIME BASE TIMER

TIMER/COUNTER

FIFO

FRC

CAPTURE UNIT

PI1 to PI7

REALTIME

2

PJ0 to PJ7

8

PORT J

1

CH

5

PULSE

CH0

GENERATOR

RAM

19

PATTERN

GENERATOR

PROGRAMMABLE

PC7/RTO7

to

PC3/RTO3

PC2/PPO18

to

PA0/PPO0

AVss

AV

REF

AV

DD

Block Diagram

A/D CONVERTER

12

PF0/AN4

PF7/AN11

AN0 to AN3

to

RAM

(CH0)

SERIAL

INTERFACE UNIT

SI0

CS0

SO0

SCK0

2

FIFO

(CH1)

SERIAL

INTERFACE UNIT

PI7/SI1

PI6/SO1

PI5/SCK1

2

FIFO

8 BIT TIMER 1

8 BIT TIMER/COUNTER 0

PI3/TO

PE1/EC

PG6/EXI0

REMOCON INPUT

PI1/RMC

PG7/EXI1

– 2 –

2

14 BIT PWM GENERATOR

PI2/PWM

12 BIT PWM GENERATOR CH0

PE4/DAA0

PE2/PWM0

4

12 BIT PWM GENERATOR CH1

PE7/DAB1

PE5/DAA1

PE6/DAB0

PE3/PWM1

PROGRAMMABLE PRESCALER

PG5/PCK

Pin Configuration 1 (Top View) 100-pin QFP package

PA6/PPO6

PA5/PPO5

PA4/PPO4

PA3/PPO3

PA2/PPO2

PA1/PPO1

PA0/PPO0

PB7/PPO15

PB6/PPO14

DD

V

NC

PA7/PPO7

CXP81952/81960

SS

TX

V

TEX

PI2/PWM

PI1/RMC

PI5/SCK1

PI4/INT1/NMI

PI3/TO/ADJ

PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10

PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4

PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16

PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1

PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

10

12 13 14 15 16 17

19

29 30

11

18

20 21 22 23 24 25 26 27 28

100

99

98 1 2 3 4 5 6

7 8 9

32

31

33

97

34

96

35

95

36

94

37

93

38

92

39

91

40

90

41

89

42

88

43

87

44

86

45

85

46

84

47

83

48

82

49

81

50

80 79 78 77 76 75

71

69 68 67 66 65 64 63 62

60 59 58 57

74 73 72

70

61

56 55 54 53 52 51

PI6/SO1 PI7/SI1 PE0/INT0 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0 PG1 PG2 PG3 PG4 PG5/PCK PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AV

DD

AVREF AVSS PF4/AN8

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

MP

RST

SS

V

XTAL

CS0

EXTAL

SI0

SO0

Note) 1. NC (Pin 90) is always connected to VDD.

2. Vss (Pins 41 and 88) are both connected to GND.

– 3 –

SCK0

PF7/AN11

PF5/AN9

PF6/AN10

Pin Configuration 2 (Top View) 100-pin LQFP package

PA7/PPO7

PA6/PPO6

PA5/PPO5

PA4/PPO4

PA3/PPO3

PA2/PPO2

PA1/PPO1

PA0/PPO0

PB7/PPO15

PB6/PPO14

PB5/PPO13

PB4/PPO12

NC

CXP81952/81960

SS

DD

V

TX

V

TEX

PI2/PWM

PI1/RMC

PI5/SCK1

PI4/INT1/NMI

PI3/TO/ADJ

PI7/SI1

PI6/SO1

PE0/INT0

PB3/PPO11 PB2/PPO10

PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4

PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16

PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1

PJ0 PD7 PD6 PD5 PD4 PD3

10 11 12 13 14 15 16 17 18 19

21 22

25

20

23 24

100

99

98

1

2 3 4

5 6 7 8 9

27

28

26

97

29

96

30

95

31

94

32

93

33

92

34

91

35

90

36

89

37

88

38

87

39

86

40

85

41

84

42

83

43

82

44

81

45

80

46

79

47

78

48

77

49

76

50

69

67

65 64 63 62 61

56 55

53 52 51

75 74 73 72 71 70

68

66

60 59 58 57

54

PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0 PG1 PG2 PG3 PG4 PG5/PCK PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF

SS

MP

PD2

PD1

PD0

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

RST

V

XTAL

EXTAL

Note) 1. NC (Pin 88) is always connected to VDD.

2. Vss (Pins 39 and 86) are both connected to GND.

– 4 –

CS0

SI0

SO0

SCK0

PF7/AN11

PF5/AN9

PF6/AN10

SS

AV

PF4/AN8

Pin Description

Symbol I/O Description

(Port A)

PA0/PPO0

to

PA7/PPO7

Output/ Real time output

8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins)

(Port B)

PB0/PPO8

to

PB7/PPO15

Output/ Real time output

8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins)

CXP81952/81960

Programmable pattern generator (PPG) output. Functions as high precision real time pulse output port. (19 pins)

PC0/PPO16

to

PC2/PPO18 PC3/RTO3

to

PC7/RTO7

PD0 to PD7

PE0/INT0

PE1/EC/INT2

PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0

I/O/ Real time output

I/O

Input/Input

Input/Input/Input

Output/Output Output/Output Output/Output Output/Output Output/Output

(Port C) 8-bit I/O port, enables to specify I/O by bit unit. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins)

Real time pulse generator (RTG) output. Functions as high precision real time pulse output port. (5 pins)

(Port D) 8-bit I/O port. Enable to specify I/O by 4-bit unit. Enables to drive 12mA sink current. (8 pins)

Input pin to request external interruption. Active when falling edge.

(Port E) 8-bit port. Lower 2 bits are input pins and upper 6 bits are output

External event input pin for timer/counter.

PWM output pins. (2 pins)

Input pin to request external interruption. Active when falling edge.

pins. (8 pins)

DA gate pulse output pins.

(4 pins) PE7/DAB1 AN0 to AN3 PF0/AN4

to

PF3/AN7 PF4/AN8

to

PF7/AN11 SCK0 SO0 SI0 CS0

Output/Output Input

Input/Input

Output/Input

I/O Ouput Input Input

Analog input pins to A/D converter. (12 pins)

(Port F) Lower 4 bits are input port and upper 4 bits are output port. Lower 4 bits also serve as standby release input pin. (8 pins)

Serial clock (CH0) I/O pin. Serial data (CH0) output pin. Serial data (CH0) input pin. Serial chip select (CH0) input pin.

– 5 –

Symbol I/O Description

PG0 to PG4 PG5/PCK PG6/EXI0

Input

(Port G) 8-bit input port. (8 pins)

7 bit general purpose prescaler input pin. External input pin to FRC capture unit.

PG7/EXI1

(Port H)

PH0 to PH7

Output

8-bit output port ; Medium withstand voltage (12V) and high current (12mA), N-ch open drain output. (8 pins)

CXP81952/81960

PI1/RMC PI2/PWM

PI3/TO/ADJ PI4/INT1/

NMI PI5/SCK1 PI6/SO1 PI7/SI1

PJ0 to PJ7

EXTAL XTAL TEX TX

RST MP AVDD AVREF AVss VDD Vss

I/O/Input I/O/Output

I/O/Output/Output

I/O/Input/Input I/O/I/O

I/O/Output I/O/Input

I/O

Input Output Input Output

Input Input

Input

Remote control receiving circuit input pin. 14-bit PWM output pin.

(Port I) 7-bit I/O port. I/O port can be specified by bit unit. (7 pins)

Timer/counter, 32kHz oscillation adjustment output pin.

Input pin to request external interruption and non-maskable interruption. Active when falling edge.

Serial clock (CH1) I/O pin. Serial data (CH1) output pin. Serial data (CH1) input pin.

(Port J) 8-bit I/O port. Function as standby release input can be specified by bit unit. I/O can be specified by bit unit.

Connecting pin of crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin.

Connecting pin of crystal oscillator for 32kHz timer clock. When used as event counter, input to TEX pin and leave TX pin open. (Feedback resistor is not removed.)

System reset pin of active "L" level. Microprocessor mode input pin. Always connect to GND. Positive power supply pin of A/D converter. Reference voltage input pin of A/D converter. GND pin of A/D converter. Positive power supply pin. GND pin. Connect both Vss pins to GND.

– 6 –

Input/Output Circuit Formats for Pins

CXP81952/81960

PA0/PPO0

to

PA7/PPO7 PB0/PPO8

to

PB7/PPO15

16 pins

PC0/PPO16

to

PC2/PPO18 PC3/RTO3

to

PC7/RTO7

Port A Port B

Data bus

Port C

PPO data

Port A or Port B

RD

PPO, RTO data

Port C data

Port C direction

Circuit format

Output becomes active from high impedance by data writing to port register.

(Every bit)

IP

Input protection circuit

When reset

Hi-Z

8 pins

PD0 to PD7

8 pins

Data bus

Port D

Data bus

RD (Port C)

Port D data

Port D direction

RD (Port D)

(Every 4 bits)

PD0 to 3 PD4 to 7

IP

High current 12mA

Hi-Z

– 7 –

CXP81952/81960

A

PE0/INT0

1 pin

PE1/EC/INT2

1 pin

PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1

Port E

Data bus

Port E

Data bus

Interruption circuit/ event counter

Port E

DA gate output or PWM output

Hi-Z control

RD

Port E data

Circuit format

Interruption circuit

RD (Port E)

MPX

IP

Input protection circuit

IP

Input protection circuit

When reset

Hi-Z

4 pins

PE6/DAB0 PE7/DAB1

2 pins

Data bus

Port E

Data bus

Port/DA output select

RD (Port E)

DA gate output

Hi-Z control

Port E data

Port/DA output select

RD (Port E)

MPX

A

H level

– 8 –

CXP81952/81960

AAA

AN0 to AN3

4 pins

PF0/AN4

to

PF3/AN7

4 pins

PF4/AN8

to

PF7/AN11

4 pins

Port F

Data bus

Port F data

RD (Port F)

Circuit format

Input multiplexer

IP

Input multiplexer

IP

Port/AD select

RD (Port F)

A/D converter

Data bus

IP

Input multiplexer

A/D converter

When reset

Hi-Z

PG0 to PG4 PG5/PCK

6 pins

PG6/EXI0 PG7/EXI1

2 pins

PH0 to PH7

8 pins

Port G

Port H

Data bus

Port H data

RD (Port H)

Schmitt input

IP

Schmitt input

IP

RD (Port G)

Data bus

PG5: To general purpose prescaler

FRC capture unit

Data bus

Medium withstand voltage 12V

Large current 12mA

Hi-Z

– 9 –

CXP81952/81960

A

PI2/PWM PI3/TO/ADJ

2 pins

PI1/RMC PI4/INT1/NMI PI7/SI1

Port I

PI2: From 14-bit PWM PI3: From timer/counter, 32kHz timer

Port I direction

Data bus

RD (Port I)

Port I

Data bus

Port I function select

Port I data

Port I direction

Circuit format

A

MPX

A

When reset

Hi-Z

IP

Hi-Z

3 pins

PI5/SCK1 PI6/SO1

2 pins

PI1: To remote control circuit PI4: To interruption circuit PI7: To serial CH1

Port I

Port I function select

From serial CH1

Port I data

Port I direction

Data bus

RD (Port I)

MPX

A

Schmitt input

MPX

Note) PI5 is schmitt input PI6 is inverter input

To serial CH1

Hi-Z

IP

– 10 –

CXP81952/81960

PJ0 to PJ7

8 pins

CS0 SI0

2 pins

Port J

Port J direction

Data bus

Standby release

Data bus

Port J data

RD (Port J)

RD

Circuit format

Edge detection

Schmitt input

IP

To SIO

When reset

IP

Hi-Z

SO0

1 pin

SCK0

1 pin

EXTAL XTAL

2 pins

EXTAL

XTAL

SO0 from SIO

SO0 output enable

Internal serial clock from SIO

SCK0 output enable

External serial clock to SIO

IP

Schmitt input

IP

• Shows the circuit composition during oscillation.

• Feedback resistor is removed during stop.

Hi-Z

Oscillation

– 11 –

CXP81952/81960

TEX TX

2 pins

RST

1 pin

MP

1 pin

TEX

TX

Mask option

Circuit format

IP

OP

IP

32kHz timer counter

Pull-up resistor

Schmitt input

IP

CPU mode

• Shows the circuit composition during oscillation.

• Feedback resistor is removed during 32kHz oscillation circuit stop by software. At this time TEX pin outputs "L" level and TX pin outputs "H" level.

When reset

Oscillation

L level

Hi-Z

– 12 –

CXP81952/81960

Absolute Maximum Ratings (Vss = 0V)

Item Symbol Rating Unit Remarks

–0.3 to +7.0

AVss to +7.0

–0.3 to +0.3 –0.3 to +7.0 –0.3 to +7.0

–0.3 to +15.0

–5

–50

15

∗1

∗2 ∗2

Supply voltage

Input voltage Output voltage Medium withstand output voltage High level output current High level total output current

VDD AVDD AVSS VIN VOUT VOUTP IOH ∑IOH

IOL

Low level output current

20

130

–20 to +75

–55 to +150

Low level total output current Operating temperature Storage temperature

IOLC ∑IOL Topr Tstg

600

Allowable power dissipation

∗1

AVDD and VDD should be set to a same voltage.

∗2

VIN and VOUT should not exceed VDD + 0.3V.

∗3

The large current operation transistors are the N-CH transistors of the PD and PH ports.

PD

380

V V V V V

V mA mA

mA mA

mA

°C °C

mW

PH pin

Total of output pins Other than large current output

pins: per pin Large current port pin∗3: per pin Total of output pins

QFP package type LQFP package type

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI.

– 13 –

CXP81952/81960

Recommended Operating Conditions (Vss = 0V)

Item Symbol Min. Max. Unit Remarks

Supply voltage

Analog power supply

High level input voltage

Low level input voltage

VDD

AVDD VIH

VIHS

VIHEX

VIL

VILS

VILEX

3.0

2.7

2.0

3.0

0.7VDD

0.8VDD

VDD – 0.4 VDD – 0.2

0 0

0 –0.3 –0.3

5.5

5.5 VDD VDD

5.5

VDD + 0.3 VDD + 0.2

0.3VDD

0.2VDD

0.4

0.2

Guaranteed range during high speed mode

V

(1/2 dividing clock) operation Guaranteed range during low speed mode

V

(1/16 dividing clock) operation Guaranteed operation range by TEX clock

V

Guaranteed data hold operation range

V

during STOP

∗1

V

∗2

V

CMOS schmitt input∗3and PE0/INT0 pin

V

CMOS schmitt input

V

EXTAL pin

V

EXTAL pin

V

∗2, ∗7

V

∗2, ∗8

V

CMOS schmitt input∗3and PE0/INT0 pin

V

EXTAL pin

V

EXTAL pin

V

∗4, ∗7 ∗4, ∗8

∗6

and TEX pin and TEX pin

∗5, ∗7 ∗5, ∗8

Operating temperature

∗1

AVDD and VDD should be set to a same voltage.

∗2

Normal input port (each pin of PC, PD, PF0 to PF3, PG, PI and PJ), MP pin.

∗3

Each pin of SCK0, RST, PE1/EC/INT2, PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1.

∗4

It specifies only when the external clock is input.

∗5

It specifies only when the external event count clock is input.

∗6

Each pin of CS0, SI0, and PG.

∗7

In case of 4.5 to 5.5V supply voltage (VDD).

∗8

In case of 3.0 to 3.6V supply voltage (VDD).

Topr

–20

+75

°C

– 14 –

Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V)

CXP81952/81960

(Ta = –20 to +75°C, Vss = 0V)

Item Symbol Pins Conditions Min.

High level output voltage

Low level output voltage

VOH

VOL

IIHE

PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0

PD, PH

VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V

EXTAL

Input current

IILE IIHT

VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V

TEX

IILT IILR

RST

∗1

VDD = 5.5V, VIL = 0.4V

PA to PG,

I/O leakage current

IIZ

PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST

VDD = 5.5V, VI = 0, 5.5V

∗1

Open drain output leakage current (N-CH

ILOH

PH

VDD = 5.5V VOH = 12V

Tr OFF in state)

4.0

3.5

0.5

–0.5

0.1 –0.1 –1.5

Typ.

Max. Unit

V V

0.4

0.6

1.5 40

–40

10

–10

–400

±10

50

V V

V µA µA µA µA µA

µA

IDD1

VDD = 5V ± 0.5V

∗3

31

50

SLEEP mode

16MHz crystal oscillation (C1 = C2 = 15pF)

IDDS1

2.0

8

VDD = 5V ± 0.5V

32kHz crystal oscillation (C1 = C2 = 47pF)

Supply current

∗2

IDD2

VDD

VDD = 3V ± 0.3V

46

110

SLEEP mode

IDDS2

9

35

VDD = 3V ± 0.3V

STOP mode

IDDS3

(EXTAL and TEX pins oscillation stop)

10

VDD = 5V ± 0.5V

Other than VDD, Vss, AV

Input capacity

∗1

RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current

CIN

DD

AVss

Clock 1MHz

, and

0V other than the measured pins

10

20

when non-resistor is selected.

∗2

When entire output pins are open.

∗3

When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock).

mA

µA

pF

– 15 –

CXP81952/81960

DC Characteristics (VDD = 3.0 to 3.6V) (Ta = –20 to +75°C, Vss = 0V)

Item Symbol Pins Conditions Min.

High level output voltage

Low level output voltage

VOH

VOL

IIHE

PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0

PD, PH

VDD = 3.0V, IOH = –0.15mA VDD = 3.0V, IOH = 0.5mA VDD = 3.0V, IOL = 1.2mA VDD = 3.0V, IOL = 1.6mA VDD = 3.0V, IOL = 5mA VDD = 3.6V, VIH = 3.6V

EXTAL

Input current

IILE IIHT

VDD = 3.6V, VIL = 0.3V VDD = 3.6V, VIH = 3.6V

TEX

IILT IILR

RST

∗1

VDD = 3.6V, VIL = 0.3V

PA to PG,

I/O leakage current

Open drain output leakage current

IIZ

ILOH

PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST

PH

VDD = 3.6V, VI = 0, 3.6V

∗1

VDD = 3.6V, VOH = 12V

2.7

2.3

0.3

–0.3

0.1 –0.1 –0.9

Typ.

Max. Unit

V V

0.3

0.5

1.0 20

–20

10

–10

–200

±10

50

V V

V µA µA µA µA µA

µA

IDD1

VDD = 3.3V ± 0.3V

∗3

15

30

SLEEP mode

12MHz crystal oscillation (C1 = C2 = 15pF)

Supply current

IDDS1

∗2

VDD

VDD = 3.3V ± 0.3V

0.8

2.5

STOP mode

IDDS3

(EXTAL and TEX pins oscillation stop)

10

VDD = 3.3V ± 0.3V

Other than VDD, Vss, AV

Input capacity

∗1

RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current

CIN

DD

AVss

Clock 1MHz

, and

0V other than the measured pins

10

20

when non-resistor is selected.

∗2

When entire output pins are open.

∗3

When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock).

mA

µA

pF

– 16 –

A

AC Characteristics (1) Clock timing

CXP81952/81960

(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)

Item Symbol Pins Conditions UnitMin.

System clock frequency

System clock input pulse width

System clock input rise and fall times

Event count clock input pulse width

Event count clock input rise and fall times

System clock frequency Event count clock input

pulse width Event count clock input

rise and fall times

∗

tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2

bits (CPU clock selection).

fC

tXL, tXH

tCR, tCF

tEH, tEL

tER, tEF

fC

tTL, tTH

tTR, tTF

XTAL EXTAL

EC

EC TEX

TX TEX

TEX

Fig. 1, Fig. 2 Fig. 1, Fig. 2 (External clock drive) Fig. 1, Fig. 2

(External clock drive) Fig. 3

Fig. 3 Fig. 2 VDD = 2.7 to 5.5V

(32kHz clock applied condition) Fig. 3

Fig. 3

VDD = 4.5 to 5.5V

1 1

28

37.5

tsys × 4

32.768

10

Max.

16 12

200

∗

20

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

MHz

ns

kHz

µs

ms

Fig. 1. Clock timing

EXTAL

Fig. 2. Clock applied condition

Crystal oscillation Ceramic oscillation

EXTAL

AA

C

1 C2

Fig. 3. Event count clock timing

TEX EC

XTAL

1/fc

t

XH tXLtCF tCR

32kHz clock applied condition

External clock

EXTAL

AA

74HC04

XTAL

crystal oscillation

TEX

AA

1

C

DD – 0.4V

V

0.4V

TX

C2

0.8VDD

0.2VDD

t

EH tELtEF tER

tTH tTLtTF tTR

– 17 –

CXP81952/81960

(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item

CS ↓→SCK delay time

CS ↑→SCK floating delay time

CS ↓→SO delay time

CS ↓→SO floating delay time

CS high level width

SCK cycle time

SCK high and low level widths

SI input setup time (against SCK ↑)

SI input hold time (against SCK ↑)

SCK ↓→SO delay time

Symbol Pin Min.

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH tKL

tSIK

tKSI

tKSO

SCK0

SO0

CS0

SCK0

SI0

SO0

Chip select transfer mode (SCK = output mode)

Chip select transfer mode

Chip select transfer mode Input mode

Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode

tsys + 200

2tsys + 200

8000/fc

tsys + 100

8000/fc – 100

–tsys + 100

200

2tsys + 100

100

Max. UnitCondition

tsys + 200

2tsys + 200

100

ns

ns ns

ns ns ns ns ns ns ns ns ns

Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI →SI0, and SO → SO0 respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.

– 18 –

CXP81952/81960

Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)

Item

CS ↓→SCK delay time

CS ↑→SCK floating delay time

CS ↓→SO delay time

CS ↓→SO floating delay time

CS high level width

SCK cycle time

SCK high and low level widths

SI input setup time (against SCK ↑)

SI input hold time (against SCK ↑)

SCK ↓→SO delay time

Symbol Pin Min.

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH tKL

tSIK

tKSI

tKSO

SCK0

SO0

CS0

SCK0

SI0

SO0

Chip select transfer mode (SCK = output mode)

Chip select transfer mode

Chip select transfer mode Input mode

Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode

tsys + 200

2tsys + 200

8000/fc

tsys + 100

8000/fc – 150

–tsys+100

200

2tsys+100

100

Max. UnitCondition

tsys + 250

tsys + 200

tsys + 250

tsys + 200

2tsys + 250

125

ns

ns ns

ns ns ns ns ns ns ns ns ns

Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) CS, SCK, SI and SO means each pin of CS → CS0, SCK → SCK0, SI → SI0, and SO → SO0 respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF.

– 19 –

Fig. 4. Serial transfer timing (CH0)

CXP81952/81960

tWHCS

CS0

SCK0

DD

0.2V

tKCY

tDCSK tDCSKF

tKL tKH

0.8VDD

0.2VDD

SIK

tKSI

t

0.8VDD

SI0

SO0

0.8VDD

Input

data

0.2VDD

tDCSO tKSO tDCSOF

Output

data

0.8V

DD

0.2VDD

– 20 –

CXP81952/81960

Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pin Min. Max. UnitCondition

SCK1 cycle time

SCK1 high and low level widths

SI1 input setup time (against SCK1 ↑)

SI1 input hold time (against SCK1 ↑)

SCK1 ↓→SO1 delay

time

Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tKCY

tKH tKL

tSIK

tKSI

tKSO

SCK1

SI1

SO1

Input mode Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode

2tsys + 200

8000/fc

tsys + 100

4000/fc – 100

100 200

tsys + 200

100

tsys + 200

100

ns ns ns ns ns ns ns ns ns ns

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.

Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V)

Item Symbol Pin Min. Max. UnitCondition

SCK1 cycle time

SCK1 high and low level widths

SI1 input setup time (against SCK1 ↑)

SI1 input hold time (against SCK1 ↑)

SCK1 ↓→SO1 delay time

Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tKCY

tKH tKL

tSIK

tKSI

tKSO

SCK1

SI1

SO1

Input mode Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode

2tsys + 200

8000/fc

tsys + 100

4000/fc – 150

100 200

tsys + 200

100

tsys + 250

125

ns ns ns ns ns ns ns ns ns ns

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")

Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF.

– 21 –

Fig. 5. Serial transfer CH1 timing

t

KCY

tKL tKH

CXP81952/81960

SCK1

SI1

SO1

tKSO

tSIK tKSI

Input data

0.8VDD

0.2VDD

Output data

0.8VDD

0.2V

DD

0.8VDD

0.2VDD

(3) General purpose prescaler (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pin Condition Min. Typ. Max. Unit External clock input frequency External clock input pulse width External clock input

rise and fall times

fPCK

tWH, tWL tR,

tF

PCK PCK

PCK

33

12

200

MHz

ns ns

Fig. 6. General purpose prescaler timing

1/fPCK

PCK

tWH

0.5VDD

0.2VDD

tF

0.8VDD

tWL

tR

– 22 –

CXP81952/81960

(4) A/D converter characteristics

Item Symbol Pins Conditions Min. Typ. Max. Unit

Resolution Linearity error Absolute error Conversion time Sampling time Reference input voltage Analog input voltage

tCONV tSAMP

VREF VIAN IREF

AVREF current

IREFS

(Ta = –20 to +75°C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V)

Item Symbol Pins Resolution Linearity error Absolute error Conversion time Sampling time Reference input voltage Analog input voltage

tCONV tSAMP

VREF VIAN

IREF

AVREF current

IREFS

(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V)

8

Ta = 25°C

±1±2LSB

VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V

∗

AVDD

0

0.6

1.0

10 µA

AVREF

AN0 to AN11

AVREF

VDD = AVDD = 4.5 to 5.5V

Operating mode SLEEP mode

STOP mode

160/fADC

12/fADC

AVDD – 0.5

32kHz operating mode

Conditions

Min.

Typ. Max. Unit

8

Ta = 25°C

±1±2LSB

VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V

∗

0

0.4

0.7

10

AVREF

AN0 to AN11

AVREF

VDD = AVDD = 3.0 to 3.6V

Operating mode

SLEEP mode STOP mode

160/fADC

12/fADC

AVDD – 0.3

32kHz operating mode

Bits

LSB

µs µs

V V

mA

Bits

LSB

µs µs

VAVDD

mA

µA

Fig. 7. Definitions of A/D converter terms

FFH FEH

Digital conversion value

01H 00H

Linearity error

Analog input

V

FTVZT

∗

The value of fADC is as follows by selecting ADC operation clock (MSC: Address 01FFH bit 0). When PS2 is selected, fADC = fc/2 When PS1 is selected, fADC = fc

– 23 –

(5) Interruption, reset input (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)

Item Symbol Pins Conditions Min. Max. Unit

INT0

External interruption high and low level widths

tIH tIL

INT1 INT2 NMI

1

µs

PJ0 to PJ7

CXP81952/81960

Reset input low level width

Fig. 8. Interruption input timing

INT0 INT1 INT2 NMI PJ0 to PJ7 (During standby release input) (Falling edge)

Fig. 9. Reset input timing

RST

tRSL

RST

tIH tIL

0.8VDD

tRSL

0.2VDD

32/fc

µs

0.2VDD

(6) Others

Item

EXI input high and low level widths

Symbol Pins Min.

tEIH tEIL

EXI0 EXI1

Conditions

tsys = 2000/fc

(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V)

Max. Unit

tFRC × 8 + 200 + tsys

ns

Note) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") tFRC = 1000/fc [ns]

Fig. 10. Other timings

tEIH tEIL

EXI0 EXI1

0.8VDD

0.2VDD

– 24 –

Supplement

A

Fig. 11. Recommended oscillation circuit

CXP81952/81960

(i)

Manufacturer

RIVER ELETEC CO., LTD.

KINSEKI LTD.

EXTAL

AAA

C

1 C2

XTAL

Model

HC-49/U03

HC-49/U (-S)

Rd

fc (MHz)

8.00

10.00

12.00

16.00

8.00

10.00

12.00

(ii)

TEX

AAA

C

1

C1 (pF) C2 (pF)

10

5

16 (12) 16 (12)

12

10

5

16 (12) 16 (12)

12

TX

Rd

C2

Rd (Ω)

0

Circuit

example

(i)

P3

Mask option table

Item

Reset pin pull-up resistor

16.00

32.768kHz

Content

Non-existent Existent

12 30

12 18

470K

(ii)

– 25 –

Characteristics Curve

CXP81952/81960

IDD vs. VDD

(fc = 16MHz, Ta = 25°C, Typical)

20.0

10.0

5.0

1.0

0.5

– Supply current [mA]

DD

I

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

3

45

V

DD – Supply voltage [V]

1/2 dividing mode 1/4 dividing mode

1/16 dividing mode

SLEEP mode

32kHz mode (instruction)

32kHz SLEEP mode

6

(VDD = 5V, Ta = 25°C, Typical)

40

30

20

– Supply current [mA]

DD

I

10

0

510 16

Frequency [MHz]

IDD vs. fc

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

SLEEP mode

IDD vs. VDD

(fc = 12MHz, Ta = 25°C, Typical)

20.0

10.0

5.0

1.0

0.5

– Supply current [mA]

DD

I

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

3

45

V

DD – Supply voltage [V]

1/2 dividing mode 1/4 dividing mode

1/16 dividing mode

SLEEP mode

6

(VDD = 3.3V, Ta = 25°C, Typical)

40

30

20

– Supply current [mA]

DD

I

10

0

1

51015

Frequency [MHz]

IDD vs. fc

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode SLEEP mode

– 26 –

Package Outline Unit: mm

100PIN QFP (PLASTIC)

23.9 ± 0.4 + 0.4

20.0 – 0.1

+ 0.4

17.9 ± 0.4

14.0 – 0.01

+ 0.1

0.15 – 0.05

15.8 ± 0.4

CXP81952/81960

A

SONY CODE EIAJ CODE

JEDEC CODE

75

76

0.65

0° to 15°

∗ 14.0 ± 0.1

±0.12

M

0.15

(16.3)

DETAIL A

QFP-100P-L01 ∗QFP100-P-1420-A

0.8 ± 0.2

100PIN LQFP (PLASTIC)

16.0 ± 0.2

51

PACKAGE STRUCTURE

PACKAGE MATERIAL LEAD TREATMENT

LEAD MATERIAL PACKAGE WEIGHT

50

+ 0.35

2.75 – 0.15

EPOXY RESIN SOLDER PLATING

COPPER / 42 ALLOY

1.4g

100

0.5 ± 0.08

SONY CODE

EIAJ CODE

JEDEC CODE

(15.0)

A

26

(0.22)

1

+ 0.08

0.18 – 0.03

25

+ 0.2

1.5 – 0.1

+ 0.05

0.127 – 0.02

0.5 ± 0.2

0.1

0.1 ± 0.1

NOTE: Dimension “∗” does not include mold protrusion.

0° to 10°

DETAIL A

LQFP-100P-L01 ∗QFP100-P-1414-A

0.5 ± 0.2

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT

EPOXY/PHENOL RESIN

SOLDER PLATING

42 ALLOY

– 27 –