Page 1
Description
The CXP80732A/80740A is a CMOS 8-bit microcomputer which consists of A/D converter, serial
interface, timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuit, PWM generator, PWM for tuner, VISS/VASS
circuit, 32kHz timer/event counter, remote control
receiving circuit, VCR vertical sync separation circuit
and the measuring circuit which measure signals of
capstan FG and drum FG/PG and other servo
systems, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port. They are integrated
into a single chip.
Also CXP80732A/80740A provides sleep/stop function
which enables to lower power consumption and ultralow speed instruction mode in 32kHz operation.
Features
• A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction
• Minimum instruction cycle During operation 250ns/16MHz (Supply voltage 4.5 to 5.5V)
During operation 122µs/32kHz
• Incorporated ROM capacity 32K bytes (CXP80732A)
40K bytes (CXP80740A)
• Incorporated RAM capacity 800 bytes
• Peripheral functions
— A/D converter 8-bit, 12-channel, successive approximation system
(Conversion time 20.0µs/16MHz)
— Serial interface Incorporated 8-bit and 8-stage FIFO, 1-channe
(1 to 8 bytes auto transfer)
8-bit serial I/O, 1-channel
— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer,
32kHz timer/counter
— High precision timing pattern generator PPG 19 pins 32-stage programmable
RTG 5-pins 2-channel
— PWM/DA gate output 12-bit, 2-channel (Repetitive frequency 62kHz/16MHz)
— Servo input control Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit Incorporated 26-bit and 8-stage FIFO
— PWM output 14-bit, 1-channel
— VISS/VASS circuit Pulse duty auto detection circuit
— Remote control receiving circuit 8-bit pulse measuring counter, 6-stage FIFO
• Interruption 21 factors, 15 vectors, multi-interruption possible
• Standby mode SLEEP/STOP
• Package 100-pin plastic QFP/LQFP
• Piggyback/evaluation chip CXP87700 100-pin ceramic QFP/LQFP
– 1 –
CXP80732A/80740A
E94Z09-ST
CMOS 8-bit Single Chip Microcomputer
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
100 pin QFP (PIastic) 100 pin LQFP (PIastic)
Structure
Silicon gate CMOS IC
Page 2
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CXP80732A/80740A
PA0 to PA7
PB0 to PB7
PC0 to PC7
PD0 to PD7
PE0 to PE1
PE2 to PE7
PF0 to PF3
PF4 to PF7
PG0 to PG7
PI1 to PI7
PJ0 to PJ7
Vss
V
DD
MP
RST
XTAL
EXTAL
CLOCK
GENERATOR/
SYSTEM CONTROL
RAM
800 BYTES
SPC700
CPU CORE
ROM
32K/40K BYTES
INTERRUPT CONTROLLER
2
2
32kHz
TIMER/COUNTER
FIFO
FRC
CAPTURE UNIT
PROGRAMMABLE
PATTERN
GENERATOR
RAM
2
5
19
AVss
AV
REF
AV
DD
2
A/D CONVERTER
SERIAL
INTERFACE UNIT
(CH0)
FIFO
8 BIT TIMER/COUNTER 0
8 BIT TIMER 1
V SYNC SEPARATOR
14 BIT PWM GENERATOR
12 BIT PWM GENERATOR CH0
SERVO INPUT
CONTROL
CAPSTAN
DRUM
CTL
2
3
2
12 BIT PWM GENERATOR CH1
4
PE7/DAB1
PE5/DAA1
PE3/PWM1
PE6/DAB0
PE4/DAA0
PE2/PWM0
PI2/PWM
PI1/RMC
PG3/PBCTL
PG2/DPG
PG1/DFG
PG0/CFG
PG7/EXI1
PG6/EXI0
PG5/SYNC1
PG4/SYNC0
PI3/TO/DDO
PE1/EC
PI5/SCK1
PI6/SO1
PI7/SI1
SCK0
SO0
SI0
CS0
AN0 to AN3
REALTIME
PULSE
GENERATOR
PE1/INT2
PE0/INT0
PI4/INT1/NMI
12
8
PORT A
8
PORT B
8
PORT C
8
PORT D
6
2
PORT E
4
4
PORT F
8
PORT G
8
PORT H
7
PORT I
PH0 to PH7
TX
TEX
NMI
PRESCALER/
TIME BASE TIMER
VISS/VASS
REMOCON INPUT
FIFO
SERIAL INTERFACE UNIT
(CH1)
CH0
CH1
8
PORT J
PI3/ADJ
PA0/PPO0
PC2/PPO18
to
PC3/RTO3
PC7/RTO7
to
PF0/AN4
PF7/AN11
to
Block Diagram
Page 3
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CXP80732A/80740A
Pin Configuration 1 (Top View) 100 pin QFP package
PB5/PPO13
PB4/PPO12
PB3/PPO11
PB2/PPO10
PB1/PPO9
PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3
PC2/PPO18
PC1/PPO17
PC0/PPO16
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PI6/SO1
PI7/SI1
PE0/INT0
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7
AV
DD
AVREF
AVSS
PF4/AN8
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
NC
V
DD
V
SS
TX
TEX
PI1/RMC
PI2/PWM
PI3/TO/DDO/ADJ
PI4/INT1/NMI
PI5/SCK1
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
MP
RST
V
SS
XTAL
EXTAL
CS0
SI0
SO0
SCK0
PF7/AN11
PF6/AN10
PF5/AN9
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
73
74
75
76
77
78
79
80
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
81
82
83
84
88
87
86
85
89
90
100
99
98
97
96
95
94
91
92
93
Note) 1. NC (Pin 90) is always connected to VDD.
2. Vss (Pins 41 and 88) are both connected to GND.
Page 4
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CXP80732A/80740A
Pin Configuration 2 (Top View) 100 pin LQFP package
PB3/PPO11
PB2/PPO10
PB1/PPO9
PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3
PC2/PPO18
PC1/PPO17
PC0/PPO16
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
PD7
PD6
PD5
PD4
PD3
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7
AV
DD
AVREF
PB4/PPO12
PB5/PPO13
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
NC
V
DD
V
SS
TX
TEX
PI1/RMC
PI2/PWM
PI3/TO/DDO/ADJ
PI4/INT1/NMI
PI5/SCK1
PI6/SO1
PI7/SI1
PE0/INT0
PD2
PD1
PD0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
MP
RST
V
SS
XTAL
EXTAL
CS0
SI0
SO0
SCK0
PF7/AN11
PF6/AN10
PF5/AN9
PF4/AN8
AV
SS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
76
77
78
79
80
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
81
82
83
84
88
87
86
85
89
90
100
99
98
97
96
95
94
91
92
93
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
73
74
75
Note) 1. NC (Pin 88) is always connected to VDD.
2. Vss (Pins 39 and 86) are both connected to GND.
Page 5
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CXP80732A/80740A
Output/
Real time
Output
Output/
Real time
Output
I/O/
Real time
Output
I/O/
Real time
Output
I/O
Input/input
Input/input/input
Output/output
Output/output
Output/output
Output/output
Output/output
Output/output
Input
Input/input
Output/input
I/O
Ouput
Input
Input
(Port A)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)
(Port B)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)
(Port C)
8-bit I/O port, enables to
specify I/O by bit unit.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)
(Port D)
8-bit I/O port. Enable to specify I/O by 4-bit unit.
Enables to drive 12mA sink current.
(8 pins)
(Port E)
8-bit port. Lower 2 bits are
input pins and upper 6 bits
are output pins.
(8 pins)
Analog input pins to A/D converter. (12 pins)
(Port F)
Lower 4 bits are input port and upper 4 bits are output port.
Lower 4 bits also serve as standby release input pin.
(8 pins)
Serial clock (CH0) I/O pin.
Serial data (CH0) output pin.
Serial data (CH0) input pin.
Serial chip select (CH0) input pin.
External event
input pin for
timer/counter.
Input pin to request
external interruption.
Active when falling edge.
Input pin to request external interruption.
Active when falling edge.
PWM output pins.
(2 pins)
DA gate pulse output pins.
(4 pins)
Programmable pattern generator (PPG)
output.
Functions as high precision real time
pulse output port.
(19 pins)
Real time pulse generator (RTG) output.
Functions as high precision real time
pulse output port. (5 pins)
Symbol I/O Description
PA0/PPO0
to
PA7/PPO7
PB0/PPO8
to
PB7/PPO15
PC0/PPO16
to
PC2/PPO18
PC3/RTO3
to
PC7/RTO7
PD0 to PD7
PE0/INT0
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
AN0 to AN3
PF0/AN4
to
PF3/AN7
PF4/AN8
to
PF7/AN11
SCK0
SO0
SI0
CS0
Pin Description
Page 6
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CXP80732A/80740A
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
PH0 to PH7
PI1/RMC
PI2/PWM
PI3/TO/
DDO/ADJ
PI4/INT1/
NMI
PI5/SCK1
PI6/SO1
PI7/SI1
PJ0 to PJ7
EXTAL
XTAL
TEX
TX
RST
MP
AVDD
AVREF
AVss
VDD
Vss
Input/input
Input/input
Input/input
Input/input
Input/input
Input/input
Input/input
Input/input
Output
I/O/input
I/O/output
I/O/output/
output/output
I/O/input/Input
I/O/I/O
I/O/output
I/O/input
I/O
Input
Output
Input
Output
Input
Input
Input
Capstan FG input pin.
Drum FG input pin.
Drum PG input pin.
Playback CTL pulse input pin.
Composite sync signal input pin.
External input pin to FRC capture unit.
(Port G)
8-bit input port.
(8 pins)
(Port H)
8-bit output port ; Medium withstand voltage (12V) and high current
(12mA), N-ch open drain output.
(8 pins)
Remote control receiving circuit input pin.
14-bit PWM output pin.
Timer/counter, CTL duty detection,
32kHz oscillation adjustment output pin.
Input pin to request external interruption and non
maskable interruption. Active when falling edge.
Serial clock (CH1) I/O pin.
Serial data (CH1) output pin.
Serial data (CH1) input pin.
(Port I)
7-bit I/O port.
I/O port can be
specified by bit
unit.
(7 pins)
(Port J)
8-bit I/O port. Function as standby release input can be specified by bit
unit. I/O can be specified by bit unit.
Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input the external clock to EXTAL pin and input
opposite phase clock to XTAL pin.
Connecting pin of crystal oscillator for 32kHz timer clock. When used
as event counter, input to TEX pin and leave TX pin open. (Feedback
resistor is not removed.)
System reset pin of active "L" level.
Microprocessor mode input pin. Always connect to GND.
Positive power supply pin of A/D converter.
Reference voltage input pin of A/D converter.
GND pin of A/D converter.
Positive power supply pin.
GND pin. Connect both Vss pins to GND.
Symbol I/O Description
Page 7
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CXP80732A/80740A
Port C
16 pins
Hi-Z
Hi-Z
When reset
PA0/PPO0
to
PA7/PPO7
PB0/PPO8
to
PB7/PPO15
PC0/PPO16
to
PC2/PPO18
PC3/RTO3
to
PC7/RTO7
Port D
8 pins
8 pins
Hi-Z
PD0
to
PD7
PPO data
Data bus
Output becomes active from high
impedance by data writing to port register.
Port A or Port B
RD
Input/Output Circuit Formats for Pins
Port A
Port B
Pin
Circuit format
Data bus
PPO, RTO data
Port C data
Port C direction
(Every bit)
IP
Input
protection
circuit
Data bus
RD (Port C)
Port D data
Port D direction
RD (Port D)
(Every 4 bits)
PD0 to 3
PD4 to 7
IP
High
current
12mA
Page 8
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CXP80732A/80740A
2 pins
Hi-Z
Hi-Z
Pin
When reset
Circuit format
PE0/INT0
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
4 pins
2 pins
4 pins
Hi-Z
Hi-Z
H level
PE6/DAB0
PE7/DAB1
Data bus
RD (Port E)
A
DA gate output
Hi-Z control
MPX
Port E data
Port/DA output
select
Data bus
RD (Port E)
DA gate output
or PWM output
Hi-Z control
MPX
Port E data
Port/DA output
select
IP
RD (Port E)
Data bus
Schmitt input
Port E
AN0
to
AN3
IP
A/D converter
Input multiplexer
4 pins
PF0/AN4
to
PF3/AN7
Port F
Port E
Port E
AA
IP
Input multiplexer
A/D converter
Data bus
RD (Port F)
Page 9
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CXP80732A/80740A
4 pins
Hi-Z
Pin
When reset
Circuit format
PF4/AN8
to
PF7/AN11
A/D
converter
Data bus
RD
(Port F)
Port/AD select
IP
Port F data
Input multiplexer
Port F
8 pins
Hi-Z
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
IP
RD (Port G)
Data bus
Schmitt input
Servo input
Note) For PG4/SYNC0, PG5/SYNC1, CMOS schmitt input and TTL schmitt
input can be selected with the mask option.
Port G
8 pins
Hi-Z
PH0
to
PH7
Data bus
RD (Port H)
Port H data
High current
12mA
Medium withstand
voltage 12V
Port H
2 pins
Hi-Z
PI2/PWM
PI3/TO/
DDO/ADJ
PI2 … From 14-bit PWM
PI3 … From timer/counter,
CTL duty detection circuit,
32kHz timer
MPX
Port I data
IP
Data bus
RD (Port I)
Port I direction
Port I function
select
Port I
Page 10
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CXP80732A/80740A
3 pins
Hi-Z
Hi-Z
Pin
When reset
Circuit format
PI1/RMC
PI4/INT1/NMI
PI7/SI1
PI5/SCK1
PI6/SO1
2 pins
8 pins
1 pin
Hi-Z
Hi-Z
Hi-Z
PJ0
to
PJ7
Standby release
Port J data
IP
Data bus
RD
(Port J)
Port J direction
Edge detection
MPX
Port I data
IP
Data bus
RD (Port I)
Port I direction
Port I function
select
MPX
To serial CH1
Note)
PI5 is schmitt input
PI6 is inverter input
From serial CH1
Port I data
IP
Data bus
RD (Port I)
Port I direction
Schmitt input
PI1 … To remote control circuit
PI4 … To interruption circuit
PI7 … To serial CH1
Port J
CS0
SI0
IP
Schmitt input
To SIO
2 pins
SO0
Port I
Port I
SO0 from SIO
SO0 output enable
Page 11
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CXP80732A/80740A
2 pins
Oscillation
Pin
When reset
Circuit format
EXTAL
XTAL
IP
EXTAL
XTAL
• Shows the circuit
composition during
oscillation.
• Feedback resistor is
removed during stop.
XTAL becomes
"H" level.
2 pins
Oscillation
TEX
TX
IP
TEX
TX
• Shows the circuit
composition during
oscillation.
• Feedback resistor is
removed during 32kHz
oscillation circuit stop
by software.
At this time TEX pin
outputs "L" level and TX
pin outputs "H" level.
32kHz
timer counter
1 pin
Hi-Z
SCK0
SCK0 output enable
Internal serial clock
from SIO
IP
Schmitt input
External serial clock to SIO
1 pin
Hi-Z
MP
IP
CPU mode
1 pin
L level
RST
IP
Schmitt input
Pull-up resistor
Mask option
OP
Page 12
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CXP80732A/80740A
∗
1) AVDD and VDD should be set to a same voltage.
∗
2) VIN and VOUT should not exceed VDD + 0.3V.
∗
3) The high current operation transistors are the N-CH transistors of the PD and PH ports.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
Supply voltage
Input voltage
Output voltage
Medium withstand output voltage
High level output current
High level total output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation
VDD
AVDD
AVSS
VIN
VOUT
VOUTP
IOH
∑IOH
IOL
IOLC
∑IOL
Topr
Tstg
PD
Low level output current
–0.3 to +7.0
AVss to +7.0
∗
1
–0.3 to +0.3
–0.3 to +7.0
∗
2
–0.3 to +7.0
∗
2
–0.3 to +15.0
–5
–50
15
20
130
–20 to +75
–55 to +150
600
380
V
V
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
mW
PH pin
Total of output pins
Other than high current output
pins: per pin
High current port pin
∗
3
: per pin
Total of output pins
QFP package type
LQFP package type
Item Symbol Rating Unit Remarks
Absolute Maximum Ratings (Vss = 0V)
Page 13
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CXP80732A/80740A
Analog power supply
High level
input voltage
Low level
input voltage
Operating temperature
Supply voltage
5.5
5.5
5.5
5.5
5.5
VDD
VDD
VDD
VDD + 0.3
0.3VDD
0.2VDD
0.8
0.4
+75
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
Item Symbol Min. Max. Unit Remarks
4.5
3.5
2.7
2.5
4.5
0.7VDD
0.8VDD
2.2
VDD – 0.4
0
0
0
–0.3
–20
AVDD
VIH
VIHS
VIHTS
VIHEX
VIL
VILS
VILTS
VILEX
Topr
Guaranteed range during high speed mode
(1/2 dividing clock) operation
Guaranteed range during low speed mode
(1/16 dividing clock) operation
Guaranteed operation range by TEX clock
Guaranteed data hold operation range
during STOP
∗
1
∗
2
CMOS schmitt input
∗
3
TTL schmitt input
∗
4
EXTAL pin
∗
5
TEX pin
∗
6
∗
2
CMOS schmitt input
∗
3
TTL schmitt input
∗
4
EXTAL pin
∗
5
TEX pin
∗
6
VDD
∗
1) AVDD and VDD should be set to a same voltage.
∗
2) Normal input port (each pin of PC, PD, PE0 to PE1, PF0 to PF3, PG, PI and PJ), MP pin.
∗
3) Each pin of CS0, SI0, SCK0, RST, PE0/INT0, PE1/EC/INT2, PG (For PG4 and PG5, when CMOS schmitt
input is selected with mask option), PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1.
∗
4) Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option)
∗
5) It specifies only when the external clock is input.
∗
6) It specifies only when the event count clock is input.
Recommended Operating Conditions (Vss=0V)
Page 14
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CXP80732A/80740A
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIH = 5.5V
High level
output voltage
4.0
3.5
0.5
–0.5
0.1
–0.1
–1.5
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
PD, PH
PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (VOL only)
PI1 to PI7
PJ, SO0, SCK0
EXTAL
TEX
RST
∗1
Item
Symbol
Pins Conditions Min.
Other than VDD,
Vss, AV
DD
, and
AVss
Clock 1MHz
0V other than the measured pins
VDD
IDD1
IIZ
ILOH
IDDS1
IDD2
IDDS2
IDDS3
CIN
VOH
VOL
IIHE
IILE
IIHT
IILT
IILR
Low level
output voltage
Input current
Typ.
0.4
0.6
1.5
40
–40
10
–10
–400
±10
50
Max. Unit
Electrical Characteristics
DC Characteristics
(Ta = –20 to +75°C, Vss = 0V)
∗
1) RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistor is selected.
∗
2) When entire output pins are open.
∗
3) When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).
VDD = 5V ± 0.5V
∗
3
SLEEP mode
VDD = 5V ± 0.5V
VDD = 5V ± 0.5V
Supply
current
∗
2
Input capacity
VDD = 5.5V,
VIL = 0.4V
VDD = 5.5V,
VI = 0, 5.5V
VDD = 5.5V
VOH = 12V
16MHz crystal oscillation (C1=C2=15pF)
STOP mode
(EXTAL and TEX pins oscillation stop)
I/O leakage
current
Open drain
output leakage
current (N-CH
Tr OFF in state)
PA to PG,
PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST
∗
1
PH
22
1.1
33
7
10
45
8
100
30
10
20
mA
mA
µA
µA
µA
pF
VDD=3V ± 0.3V
SLEEP mode
VDD = 3V ± 0.3V
32kHz crystal oscillation (C1=C2=47pF)
Page 15
– 15 –
CXP80732A/80740A
∗
tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2-bit = “00”), 4000/fc (Upper 2-bit = “01”), 16000/fc (Upper 2-bit = “11”)
EXTAL
t
XH tXLtCF tCR
0.4V
V
DD – 0.4V
1/fc
A
External clock
EXTAL
XTAL
74HC04
A
Crystal oscillation
Ceramic oscillation
EXTAL
XTAL
C
1 C2
A
32kHz clock applying condition
crystal oscillation
TEX
TX
C
1
C2
AC Characteristics
(1) Clock timing
System clock frequency
System clock input pulse
width
System clock input
rise and fall times
Event count clock input
pulse width
Event count clock input
rise and fall times
System clock frequency
Event count clock input
pulse width
Event count clock input
rise and fall times
fC
tXL,
tXH
tCR,
tCF
tEH,
tEL
tER,
tEF
fC
tTL,
tTH
tTR,
tTF
XTAL
EXTAL
XTAL
EXTAL
XTAL
EXTAL
EC
EC
TEX
TX
TEX
TEX
MHz
ns
ns
ns
ns
kHz
µs
ms
Item Symbol Pins Conditions Unit
Fig. 1,
Fig. 2
Fig. 1,
Fig. 2 (External clock drive)
Fig. 1, Fig. 2
(External clock drive)
Fig. 3
Fig. 3
Fig. 2 VDD = 2.7 to 5.5V
(32kHz clock applied condition)
Fig. 3
Fig. 3
Min.
1
28
tsys ×4
∗
32.768
10
Max.
16
200
20
20
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Fig. 1. Clock timing
Fig. 2. Clock applied condition
TEX
EC
t
EH
tELtEF tER
0.2VDD
0.8VDD
tTH tTLtTF tTR
Fig. 3. Event count clock timing
AA
AAA
AAA
Page 16
– 16 –
CXP80732A/80740A
Input mode
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
(SCK0 = output mode)
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2-bit = “00”), 4000/fc (Upper 2-bit = “01”), 16000/fc (Upper 2-bit = “11”)
Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.
(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
CS0 ↓ → SCK0
delay time
CS0 ↑ → SCK0
floating delay time
CS0 ↓ → SO0
delay time
CS0 ↑ → SO0
floating delay time
CS0
high level width
SCK0
cycle time
SCK0
high and low level widths
SI0 input setup time
(against SCK0 ↑)
SI0 input hold time
(against SCK0 ↑)
SCK0 ↓ → SO0 delay time
tDCSK
tDCSKF
tDCSO
tDCSOF
tWHCS
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK0
SCK0
SO0
SO0
CS0
SCK0
SCK0
SI0
SI0
SO0
ns
ns
ns
ns
ns
Symbol Pin Min.
tsys + 200
tsys + 200
tsys + 200
tsys + 200
tsys + 200
2tsys + 200
16000/fc
tsys + 100
8000/fc – 50
100
200
tsys + 200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsys + 200
100
Max. UnitCondition
Page 17
– 17 –
CXP80732A/80740A
Fig. 4. Serial transfer CH0 timing
CS0
SCK0
0.2VDD
0.8VDD
tWHCS
tDCSK tDCSKF
0.8VDD
0.2VDD
0.8VDD
tKCY
tKL tKH
0.8VDD
0.2VDD
SI0
tSIK
tKSI
Input
data
t
DCSO tKSO tDCSOF
Output
data
0.8V
DD
0.2VDD
SO0
Page 18
– 18 –
CXP80732A/80740A
Fig. 5. Serial transfer CH1 timing
SCK1
SI1
SO1
t
KCY
tKL tKH
0.2VDD
0.8VDD
tSIK tKSI
tKSO
Input data
Output data
0.2V
DD
0.8VDD
0.2VDD
0.8VDD
Serial transfer (CH1) (Ta=–20 to +75°C, VDD=4.5 to 5.5V, Vss=0V)
Item Symbol Pins Min. Max. UnitConditions
SCK1 cycle time
SCK1 high and low
level widths
SI1 input setup time
(against SCK1 ↑)
SI1 input hold time
(against SCK1 ↑)
SCK1 ↓ → SO1 delay time
tKCY
tKH
tKL
tSIK
tKSI
tKSO
SCK1
SCK1
SI1
SI1
SO1
Input mode
Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
1000
16000/fc
400
8000/fc – 50
100
200
200
100
200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Page 19
– 19 –
CXP80732A/80740A
tCONV
tSAMP
VREF
VIAN
IREF
IREFS
Ta=25°C
VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V
Operating mode
SLEEP mode
STOP mode
32kHz operating mode
Resolution
Linearity error
Absolute error
Conversion time
Sampling time
Reference input
voltage
Analog input voltage
AVREF current
AVREF
160/fADC
∗
12/fADC
∗
AVDD – 0.5
0
0.6
Item Symbol Pins Conditions Min. Typ. Max. Unit
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V)
8
±1
±2
AVDD
1.0
10
Bits
LSB
LSB
µs
µs
V
V
mA
µA
Analog input
Linearity error
V
FTVZT
00H
01H
FEH
FFH
Digital conversion value
∗
The value of fADC is as follows by selecting ADC
operation clock (MSC: Address 01FFH bit 0).
When PS2 is selected, fADC = fc/2
When PS1 is selected, fADC = fc
Fig. 6. Definitions of A/D converter terms
AVREF
AN0 to AN11
Page 20
– 20 –
CXP80732A/80740A
External interruption
high and low level widths
Reset input low level width
INT0
INT1
INT2
NMI
PJ0 to PJ7
RST
1
32/fc
µs
µs
Item Symbol Pins Conditions Min. Max. Unit
tIH
tIL
tRSL
(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
0.2VDD
0.8VDD
tIH tIL
INT0
INT1
INT2
NMI
PJ0 to PJ7
(During standby release input)
(Falling edge)
Fig. 7. Interruption input timing
tRSL
0.2VDD
RST
Fig. 8. Reset input timing
(5) Others (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
CFG input
high and low level widths
DFG input
high and low level widths
DPG minimum pulse width
DPG minimum
removal time
PBCTL input
high and low level widths
EXI input
high and low level widths
tCFH
tCFL
tDFH
tDFL
tDPW
trem
tCTH
tCTL
tEIH
tEIL
CFG
DFG
DPG
DPG
PBCTL
EXI0
EXI1
ns
ns
ns
ns
ns
ns
Symbol Pins Min.
tFRC × 24 + 200
tFRC × 8 + 200
50
50
tFRC × 8 + 200 + tsys
tFRC × 8 + 200 + tsys
Max. Unit
tsys = 2000/fc
tsys = 2000/fc
Conditions
Note) tsys indicates three values according to the contents of the clock control register (address; 00FEH)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2-bit = “00”), 4000/fc (Upper 2-bit = “01”), 16000/fc (Upper 2-bit = “11”)
tFRC [ns] = 1000/fc
Page 21
– 21 –
CXP80732A/80740A
0.8VDD
CFG
tCFH tCFL
0.2VDD
0.8VDD
DFG
tDFH tDFL
0.2VDD
0.8VDD
PBCTL
tCTH tCTL
0.2VDD
0.8VDD
EXI0
EXI1
tEIH tEIL
0.2VDD
0.8VDD
trem tDPW trem
DPG
Fig. 9. Other timings
Page 22
– 22 –
CXP80732A/80740A
Supplement
Fig. 10. Recommended oscillation circuit
A
A
AAAA
EXTAL
XTAL
C
1 C2
Rd
(i) (ii)
A
TEX
TX
C1
C2
Rd
Manufacturer
RIVER
ELETEC
CO., LTD.
KINSEKI LTD.
Model
HC-49/U03
HC-49/U (-S)
P3
fc (MHz)
8.00
10.00
12.00
16.00
8.00
10.00
12.00
16.00
32.768kHz
470k
(ii)
10 10
10 10
16
16
12
12
30
12
12
12
12
18
0
0
C1 (pF)
C2 (pF) Rd (Ω)
Circuit
example
(i)
(i)
Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2).
∗
In PG4/SYNC0 pin and PG5/SYNC1 pin, the input circuit format can be selected to every pin.
Item Content
Reset pin pull-up resistor
Input circuit format
∗
Non-existent
C-MOS schmitt
Existent
TTL schmitt
Mask option table
AA
AAA
Page 23
– 23 –
CXP80732A/80740A
Characteristics Curve
(100µA)
3
4 5
6
0.1
5.0
1.0
V
DD – Supply voltage [V]
I
DD
–
Supply current [mA]
IDD vs. VDD
(fc = 16MHz, Ta = 25°C, Typical)
72
0.05
(50
µA)
0.01
(10µA)
0.5
10.0
20.0
1/2 dividing mode
1/4 dividing mode
1/16 dividing mode
SLEEP mode
0
15
10
5
fc
– System clock [MHz]
I
DD
–
Supply current [mA]
IDD vs. fc
(V
DD = 5V, Ta = 25°C, Typical)
5
10
16
20
1/16 dividing mode
1/4 dividing mode
SLEEP mode
32kHz mode
(instruction)
32kHz mode
SLEEP
1/2 dividing mode
Page 24
– 24 –
CXP80732A/80740A
Package Outline Unit : mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
PACKAGE STRUCTURE
23.9 ± 0.4
QFP-100P-L01
100PIN QFP (PLASTIC)
20.0 – 0.1
+ 0.4
0.15 – 0.05
+ 0.1
15.8 ± 0.4
17.9 ± 0.4
14.0 – 0.1
+ 0.4
2.75 – 0.15
+ 0.35
A
0.65
M
0.13
QFP100-P-1420
1.7g
1
100
81
80 51
50
31
30
0.3 – 0.1
+ 0.15
DETAIL A
0° to 10°
0.8 ± 0.2
(16.3)
0.15
0.1 – 0.05
+ 0.2
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42 ALLOY
PACKAGE STRUCTURE
DETAIL A
LQFP-100P-L01
LQFP100-P-1414
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗ 14.0 ± 0.1
75
51
50
26
25
1
76
0.5
0.18 – 0.03
+ 0.08
(0.22)
A
1.5 – 0.1
+ 0.2
0.127 – 0.02
+ 0.05
0.5 ± 0.2
(15.0)
0° to 10°
0.1 ± 0.1
0.5 ± 0.2
100
0.1
NOTE: Dimension “∗” does not include mold protrusion.
0.8g
0.13
M
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