Datasheet CXP80724A, CXP80720A, CXP80712A, CXP80716A Datasheet (Sony)

CXP80712A/80716A/80720A/80724A

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CMOS 8-bit Single Chip Microcomputer

Description

The CXP80712A/80716A/80720A/80724A is a CMOS
8-bit microcomputer which consists of A/D converter,
serial interface, timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuit, PWM generator, PWM for tuner, VISS/VASS
circuit, 32kHz timer/event counter, remote control
receiving circuit, VCR vertical sync separation circuit
and the measuring circuit which measure signals of
capstan FG and drum FG/PG and other servo systems,
as well as basic configurations like 8-bit CPU, ROM,
RAM and I/O port. They are integrated into a single chip.

Also CXP80712A/80716A/80720A/80724A provides
sleep/stop function which enables to lower power
consumption and ultra-low speed instruction mode in
32kHz operation.

Features

• A wide instruction set (213 instructions) which cover various types of data

— 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction

• Minimum instruction cycle During operation 250ns/16MHz (Supply voltage 4.5 to 5.5V)

During operation 122µs/32kHz

• Incorporated ROM capacity 12K bytes (CXP80712A)

16K bytes (CXP80716A)
20K bytes (CXP80720A)
24K bytes (CXP80724A)

• Incorporated RAM capacity 800 bytes

• Peripheral functions

— A/D converter 8-bit, 12-channel, successive approximation system

(Conversion time 20.0µs/16MHz)

— Serial Interface Incorporated 8-bit and 8-stage FIFO, 1-channel

(1 to 8 bytes auto transfer)
8-bit serial I/O, 1-channel

— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer,

32kHz timer/counter

— High precision timing pattern generator PPG 19 pins 32-stage programmable

RTG 5-pins 2-channel
— PWM/DA gate output 12-bit, 2-channel (Repetitive frequency 62kHz/16MHz)
— Servo input control Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit Incorporated 26-bit and 8-stage FIFO
— PWM output 14-bit, 1-channel
— VISS/VASS circuit Pulse duty auto detection circuit
— Remote control receiving circuit 8-bit pulse measuring counter, 6-stage FIFO

• Interruption 21 factors, 15 vectors, multi-interruption possible

• Standby mode SLEEP/STOP

• Package 100-pin plastic QFP/LQFP

• Piggyback/evaluation chip CXP87700 100-pin ceramic QFP/LQFP

100 pin QFP (PIastic) 100 pin LQFP (PIastic)

Structure

Silicon gate CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E94Z08-ST

CXP80712A/80716A/80720A/80724A

Vss
V

DD

MP
RST
XTAL

EXTAL
TX

TEX

PE1/INT2
PI4/INT1/NMI

PE0/INT0

PA0 to PA7

PB0 to PB7

8

PORT A8PORT B8PORT C

CLOCK

GENERATOR/

SYSTEM CONTROL

SPC700

CPU CORE

NMI

2

PC0 to PC7

PD0 to PD7

PE0 to PE1

8

2

PORT D

RAM

800 BYTES

ROM

BYTES

12K/16K/20K/24K

INTERRUPT CONTROLLER

2

PF0 to PF3

PE2 to PE7

4

6

PORT E

PRESCALER/

2

2

PF4 to PF7

PG0 to PG7

PH0 to PH7

PI1 to PI7

4

PORT F8PORT G8PORT H7PORT I

32kHz

TIME BASE TIMER

TIMER/COUNTER

REALTIME

2

FIFO

FRC

CAPTURE UNIT

3

PJ0 to PJ7
8

PORT J

CH1

5

PULSE

CH0

GENERATOR

RAM

19

PATTERN

GENERATOR

PROGRAMMABLE

4

2

to

to

PC7/RTO7

PC3/RTO3

PC2/PPO18

PA0/PPO0

AVss

AV

REF

AV

DD

AN0 to AN3

Block Diagram

A/D CONVERTER

SERIAL

12

SI0

CS0

to

PF0/AN4

PF7/AN11

FIFO

(CH1)

(CH0)

SERIAL INTERFACE UNIT

INTERFACE UNIT

SO0

SCK0

PI7/SI1

PI6/SO1

PI5/SCK1

8 BIT TIMER 1

8 BIT TIMER/COUNTER 0

PE1/EC

V SYNC SEPARATOR

PG5/SYNC1

PG4/SYNC0

PI3/TO/DDO

PG7/EXI1

PG6/EXI0

– 2 –

CONTROL

SERVO INPUT

CTL

DRUM

CAPSTAN

PG1/DFG

PG0/CFG

PG2/DPG

PG3/PBCTL

FIFO

VISS/VASS

REMOCON INPUT

PI1/RMC

14 BIT PWM GENERATOR

PI2/PWM

12 BIT PWM GENERATOR CH1

12 BIT PWM GENERATOR CH0

PI3/ADJ

PE5/DAA1

PE6/DAB0

PE4/DAA0

PE2/PWM0

PE7/DAB1

PE3/PWM1

Pin Configuration 1 (Top View) 100 pin QFP package

PA6/PPO6

PA5/PPO5

PA4/PPO4

PA3/PPO3

PA2/PPO2

PA1/PPO1

PA0/PPO0

PB7/PPO15

PB6/PPO14

DD

V

NC

PA7/PPO7

CXP80712A/80716A/80720A/80724A

SS

TX

V

TEX

PI2/PWM

PI1/RMC

PI5/SCK1

PI4/INT1/NMI

PI3/TO/DDO/ADJ

PB5/PPO13
PB4/PPO12
PB3/PPO11
PB2/PPO10

PB1/PPO9
PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4

PC3/RTO3
PC2/PPO18
PC1/PPO17
PC0/PPO16

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1

PJ0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0

10

12
13
14
15
16
17

19

25

29
30

11

18

20
21
22
23
24

26
27
28

100

99

98

1

2
3
4

5
6
7
8
9

32

31

33

97

34

96

35

95

36

94

37

93

38

92

39

91

40

90

41

89

42

88

43

87

44

86

45

85

46

84

47

83

48

82

49

81

50

80

78

76
75

68

64

62

60
59
58
57

55

52

79

77

74
73
72
71
70
69

67
66
65

63

61

56

54
53

51

PI6/SO1
PI7/SI1
PE0/INT0
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7

DD

AV
AVREF
AVSS
PF4/AN8

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

MP

RST

SS

V

XTAL

CS0

EXTAL

SI0

SO0

SCK0

Note) 1. NC (Pin 90) is always connected to VDD.

2. Vss (Pins 41 and 88) are both connected to GND.

– 3 –

PF5/AN9

PF6/AN10

PF7/AN11

Pin Configuration 2 (Top View) 100 pin LQFP package

PA7/PPO7

PA6/PPO6

PA5/PPO5

PA4/PPO4

PA3/PPO3

PA2/PPO2

PA1/PPO1

PA0/PPO0

PB7/PPO15

PB6/PPO14

PB5/PPO13

PB4/PPO12

NC

CXP80712A/80716A/80720A/80724A

SS

DD

V

TX

V

TEX

PI2/PWM

PI1/RMC

PI5/SCK1

PI4/INT1/NMI

PI3/TO/DDO/ADJ

PI7/SI1

PI6/SO1

PE0/INT0

PB3/PPO11
PB2/PPO10

PB1/PPO9
PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4

PC3/RTO3
PC2/PPO18
PC1/PPO17
PC0/PPO16

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1

PJ0
PD7
PD6
PD5
PD4
PD3

10
11
12
13
14
15
16
17
18
19

21
22

25

20

23
24

100

99

98

1

2
3
4

5
6
7
8
9

27

28

26

97

29

96

30

95

31

94

32

93

33

92

34

91

35

90

36

89

37

88

38

87

39

86

40

85

41

84

42

83

43

82

44

81

45

80

46

79

47

78

48

77

49

76

50

75
74
73
72

70
69
68
67

65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

71

66

PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7
AV

DD

AVREF

SS

MP

PD2

PD1

PD0

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

RST

V

XTAL

EXTAL

Note) 1. NC (Pin 88) is always connected to VDD.

2. Vss (Pins 39 and 86) are both connected to GND.

– 4 –

CS0

SI0

SO0

SCK0

PF7/AN11

PF4/AN8

PF5/AN9

PF6/AN10

SS

AV

Pin Description

Symbol I/O Description

(Port A)

PA0/PPO0

to

PA7/PPO7

Output/
Real time
Output

8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

(Port B)

PB0/PPO8

to

PB7/PPO15

Output/
Real time
Output

8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

CXP80712A/80716A/80720A/80724A

Programmable pattern generator (PPG)
output.
Functions as high precision real time
pulse output port.
(19 pins)

PC0/PPO16

to

PC2/PPO18
PC3/RTO3

to

PC7/RTO7

PD0 to PD7

PE0/INT0

PE1/EC/INT2

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0

I/O/
Real time
Output

I/O/
Real time
Output

I/O

Input/input

Input/input/input

Output/output
Output/output
Output/output
Output/output
Output/output

(Port C)
8-bit I/O port, enables to
specify I/O by bit unit.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)

Real time pulse generator (RTG) output.
Functions as high precision real time
pulse output port. (5 pins)

(Port D)
8-bit I/O port. Enable to specify I/O by 4-bit unit.
Enables to drive 12mA sink current.
(8 pins)

Input pin to request external interruption.
Active when falling edge.

External event
input pin for

(Port E)

timer/counter.
8-bit port. Lower 2 bits are
input pins and upper 6 bits
are output pins.

PWM output pins.

(2 pins)
(8 pins)

DA gate pulse output pins.

(4 pins)

Input pin to request
external interruption.
Active when falling edge.

PE7/DAB1
AN0 to AN3
PF0/AN4

to

PF3/AN7
PF4/AN8

to

PF7/AN11
SCK0
SO0
SI0
CS0

Output/output
Input

Input/input

Output/input

I/O
Ouput
Input
Input

Analog input pins to A/D converter. (12 pins)

(Port F)
Lower 4 bits are input port and upper 4 bits are output port.
Lower 4 bits also serve as standby release input pin.
(8 pins)

Serial clock (CH0) I/O pin.
Serial data (CH0) output pin.
Serial data (CH0) input pin.
Serial chip select (CH0) input pin.

– 5 –

Symbol I/O Description

CXP80712A/80716A/80720A/80724A

PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1

PH0 to PH7

PI1/RMC
PI2/PWM
PI3/TO/

DDO/ADJ
PI4/INT1/

NMI
PI5/SCK1

Input/input
Input/input
Input/input
Input/input
Input/input
Input/input
Input/input
Input/input

Output

I/O/input
I/O/output
I/O/output/

output/output
I/O/input/Input
I/O/I/O

Capstan FG input pin.
Drum FG input pin.
Drum PG input pin.

(Port G)

Playback CTL pulse input pin.

8-bit input port.
(8 pins)

Composite sync signal input pin.

External input pin to FRC capture unit.

(Port H)
8-bit output port ; Medium withstand voltage (12V) and high current
(12mA), N-ch open drain output.
(8 pins)

Remote control receiving circuit input pin.
14-bit PWM output pin.

(Port I)
7-bit I/O port.
I/O port can be
specified by bit
unit.
(7 pins)

Timer/counter, CTL duty detection, 32kHz
oscillation adjustment output pin.

Input pin to request external interruption and non
maskable interruption. Active when falling edge.

Serial clock (CH1) I/O pin.
PI6/SO1
PI7/SI1

PJ0 to PJ7

EXTAL
XTAL
TEX
TX

RST
MP
AVDD
AVREF
AVss
VDD
Vss

I/O/output
I/O/input

I/O

Input
Output
Input
Output

Input
Input

Input

Serial data (CH1) output pin.

Serial data (CH1) input pin.

(Port J)
8-bit I/O port. Function as standby release input can be specified by bit
unit. I/O can be specified by bit unit.

Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input the external clock to EXTAL pin and input
opposite phase clock to XTAL pin.

Connecting pin of crystal oscillator for 32kHz timer clock. When used
as event counter, input to TEX pin and leave TX pin open. (Feedback
resistor is not removed.)

System reset pin of active "L" level.
Microprocessor mode input pin. Always connect to GND.
Positive power supply pin of A/D converter.
Reference voltage input pin of A/D converter.
GND pin of A/D converter.
Positive power supply pin.
GND pin. Connect both Vss pins to GND.

– 6 –

Input/Output Circuit Formats for Pins

CXP80712A/80716A/80720A/80724A

Pin

PA0/PPO0

to

PA7/PPO7
PB0/PPO8

to

PB7/PPO15

16 pins

PC0/PPO16

to

PC2/PPO18
PC3/RTO3

to

PC7/RTO7

Port A
Port B

Data bus

Port C

PPO data

Port A or Port B

RD

PPO, RTO data

Port C data

Port C direction

Circuit format

Output becomes active from high
impedance by data writing to port register.

(Every bit)

IP

Input
protection
circuit

When reset

Hi-Z

Hi-Z

8 pins

PD0

to

PD7

8 pins

Data bus

Port D

Data bus

RD (Port C)

Port D data

Port D direction

RD (Port D)

(Every 4 bits)

PD0 to 3
PD4 to 7

IP

High
current
12mA

Hi-Z

– 7 –

CXP80712A/80716A/80720A/80724A

A

A

A

Pin

PE0/INT0
PE1/EC/INT2

2 pins

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1

4 pins

Port E

Port E

Data bus

DA gate output
or PWM output

Hi-Z control

Port E data

Port/DA output
select

RD (Port E)

Circuit format

Schmitt input

IP

MPX

A

When reset

Hi-Z

Data bus

RD (Port E)

Hi-Z

PE6/DAB0
PE7/DAB1

2 pins

AN0

to

AN3

4 pins

PF0/AN4

to

PF3/AN7

Port E

Data bus

Port F

DA gate output

Hi-Z control

Port E data

Port/DA output
select

RD (Port E)

Input multiplexer

IP

Input multiplexer

IP

MPX

A
A

A/D converter

A/D converter

H level

Hi-Z

Hi-Z

4 pins

Data bus

RD (Port F)

– 8 –

CXP80712A/80716A/80720A/80724A

A

Pin

PF4/AN8

to

PF7/AN11

4 pins

PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1

8 pins

Circuit format

Port F

Port F data

Data bus

RD
(Port F)

Port/AD select

Port G

Schmitt input

IP

RD (Port G)

Note) For PG4/SYNC0, PG5/SYNC1, CMOS schmitt input and TTL schmitt
input can be selected with the mask option.

Servo input

Data bus

IP

Input multiplexer

A/D
converter

When reset

Hi-Z

Hi-Z

PH0

to

PH7

8 pins

PI2/PWM
PI3/TO/
DDO/ADJ

2 pins

Port H

Port H data

Data bus

Port I

PI2: From 14-bit PWM
PI3: From timer/counter,
CTL duty detection circuit,
32kHz timer

Port I data

Port I direction

Data bus

RD (Port I)

RD (Port H)

Port I function
select

AA

Medium withstand
voltage 12V

Hi-Z

High current
12mA

MPX

Hi-Z

IP

– 9 –

CXP80712A/80716A/80720A/80724A

A

A

A

A

PIn

PI1/RMC
PI4/INT1/NMI
PI7/SI1

3 pins

PI5/SCK1
PI6/SO1

2 pins

Port I

Data bus

PI1: To remote control circuit
PI4: To interruption circuit
PI7: To serial CH1

Port I

Port I function
select

From serial CH1

Port I data

Port I direction

Data bus

RD (Port I)

Circuit format

Port I data

Port I direction

RD (Port I)

MPX

A

Schmitt input

A

MPX

Note)

A

PI5 is schmitt input
PI6 is inverter input

To serial CH1

When reset

IP

IP

Hi-Z

Hi-Z

PJ0

to

PJ7

8 pins

CS0

SI0

2 pins

SO0

1 pin

Port J

Port J data

Port J direction

Data bus

Standby release

SO0 from SIO

SO0 output enable

RD
(Port J)

Edge detection

Schmitt input

IP

Hi-Z

IP

Hi-Z

To SIO

Hi-Z

– 10 –

CXP80712A/80716A/80720A/80724A

PIn

SCK0

1 pin

EXTAL
XTAL

2 pins

TEX
TX

2 pins

TEX

TX

EXTAL

XTAL

Circuit format

Internal serial clock
from SIO

SCK0 output enable

External serial clock to SIO

IP

IP

Schmitt input

32kHz
timer counter

IP

• Shows the circuit
composition during
oscillation.

• Feedback resistor is
removed during stop.
XTAL becomes "H"
level.

• Shows the circuit
composition during
oscillation.

• Feedback resistor is
removed during 32kHz
oscillation circuit stop
by software.
At this time TEX pin
outputs "L" level and TX
pin outputs "H" level.

When reset

Hi-Z

Oscillation

Oscillation

RST

1 pin

MP

1 pin

Mask option

Pull-up resistor

Schmitt input

OP

IP

IP

CPU mode

L level

Hi-Z

– 11 –

CXP80712A/80716A/80720A/80724A

Absolute Maximum Ratings (Vss=0V)

Item Symbol Rating Unit Remarks

–0.3 to +7.0

AVss to +7.0

–0.3 to +0.3
–0.3 to +7.0
–0.3 to +7.0

–0.3 to +15.0

–5

–50

15

∗1

∗2
∗2

Supply voltage

Input voltage
Output voltage
Medium withstand output voltage
High level output current
High level total output current

VDD
AVDD
AVSS
VIN
VOUT
VOUTP
IOH
∑IOH

IOL

Low level output current

20

130

–20 to +75

–55 to +150

Low level total output current
Operating temperature
Storage temperature

IOLC
∑IOL
Topr
Tstg

600

Allowable power dissipation

∗1

AVDD and VDD should be set to a same voltage.

∗2

VIN and VOUT should not exceed VDD + 0.3V.

∗3

The high current operation transistors are the N-CH transistors of the PD and PH ports.

PD

380

V
V
V
V
V

V
mA
mA

mA
mA

mA

°C
°C

mW

PH pin

Total of output pins
Other than high current output

pins: per pin
High current port pin∗3: per pin
Total of output pins

QFP package type
LQFP package type

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.

– 12 –

CXP80712A/80716A/80720A/80724A

Recommended Operating Conditions (Vss = 0V)

Item Symbol Min. Max. Unit Remarks

4.5

Supply voltage

VDD

3.5

2.7

2.5

Analog power supply

HIgh level
input voltage

Low level
input voltage

Operating temperature

∗1

AVDD and VDD should be set to a same voltage.

∗2

Normal input port (each pin of PC, PD, PE0 to PE1, PF0 to PF3, PG, PI and PJ), MP pin.

∗3

Each pin of CS0, SI0, SCK0, RST, PE0/INT0, PE1/EC/INT2, PG (For PG4 and PG5, when CMOS schmitt

AVDD
VIH
VIHS
VIHTS
VIHEX
VIL
VILS
VILTS
VILEX
Topr

4.5

0.7VDD

0.8VDD

2.2

VDD – 0.4

0
0
0

–0.3

–20

5.5

5.5

5.5

5.5

5.5
VDD
VDD
VDD

VDD + 0.3

0.3VDD

0.2VDD

0.8

0.4
+75

Guaranteed range during high speed mode

V

(1/2 dividing clock) operation
Guaranteed range during low speed mode

V

(1/16 dividing clock) operation
Guaranteed operation range by TEX clock

V

Guaranteed data hold operation range

V

during STOP

∗1

V

∗2

V

CMOS schmitt input

V

TTL schmitt input

V

EXTAL pin

V

∗2

V

CMOS schmitt input

V

TTL schmitt input

V

EXTAL pin

V

∗5

∗5

∗3

∗4

TEX pin

∗3

∗4

TEX pin

∗6

∗6

°C

input is selected with mask option), PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1.

∗4

Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option)

∗5

It specifies only when the external clock is input.

∗6

It specifies only when the event count clock is input.

– 13 –

Electrical Characteristics
DC Characteristics

CXP80712A/80716A/80720A/80724A

(Ta = –20 to +75°C, Vss = 0V)

Item Symbol Pins Conditions Min.

High level
output voltage

Low level
output voltage

VOH

VOL

IIHE

PA to PD,
PE2 to PE7,
PF4 to PF7,
PH (VOL only)
PI1 to PI7
PJ, SO0, SCK0

PD, PH

VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V

EXTAL

Input current

IILE
IIHT

VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIH = 5.5V

TEX

IILT
IILR

RST

∗1

VDD = 5.5V,
VIL = 0.4V

PA to PG,

I/O leakage
current

IIZ

PI, PJ, MP
AN0 to AN3,
CS0, SI0, SO0
SCK0, RST

VDD = 5.5V,
VI = 0, 5.5V

∗1

Open drain
output leakage
current (N-CH

ILOH

PH

VDD = 5.5V
VOH = 12V

Tr OFF in state)

4.0

3.5

0.5

–0.5

0.1
–0.1
–1.5

Typ.

Max. Unit

V
V

0.4

0.6

1.5
40

–40

10

–10

–400

±10

50

V
V

V
µA
µA
µA
µA
µA

µA

µA

IDD1

VDD = 5V ± 0.5V

∗3

20

45

SLEEP mode

16MHz crystal oscillation (C1 = C2 = 15pF)

IDDS1

1.1

8

VDD = 5V ± 0.5V

32kHz crystal oscillation (C1 = C2 = 47pF)

Supply
current

∗2

IDD2

VDD

VDD = 3V ± 0.3V

35

100

SLEEP mode

IDDS2

7

30

VDD = 3V ± 0.3V

STOP mode

IDDS3

(EXTAL and TEX pins oscillation stop)

10

VDD = 5V ± 0.5V

Other than VDD,
Vss, AV

Input capacity

∗1

RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current

CIN

DD

AVss

Clock 1MHz

, and

0V other than the measured pins

10

20

when non-resistor is selected.

∗2

When entire output pins are open.

∗3

When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and
operating in high speed mode (1/2 dividing clock).

mA

mA

µA

µA

µA

pF

– 14 –

A

A

A

AC Characteristics
(1) Clock timing

CXP80712A/80716A/80720A/80724A

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pins Conditions Unit

System clock frequency

System clock input pulse width
System clock input

rise and fall times
Event count clock input

pulse width
Event count clock input

rise and fall times
System clock frequency
Event count clock input

pulse width
Event count clock input

rise and fall times

∗

tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2

bits (CPU clock selection).

fC

tXL,
tXH

tCR,
tCF

tEH,
tEL

tER,
tEF

fC

tTL,
tTH

tTR,
tTF

XTAL
EXTAL

XTAL
EXTAL

XTAL
EXTAL

EC

EC
TEX

TX
TEX

TEX

Fig. 1,
Fig. 2

Fig. 1,
Fig. 2 (External clock drive)

Fig. 1, Fig. 2
(External clock drive)

Fig. 3

Fig. 3
Fig. 2 VDD = 2.7 to 5.5V

(32kHz clock applied condition)
Fig. 3

Fig. 3

Min.

1

28

tsys × 4

32.768

10

Max.

16

200

∗

20

20

tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11")

MHz

ns

ns

ns

ns

kHz

µs

ms

Fig. 1. Clock timing

EXTAL

Fig. 2. Clock applied condition

Crystal oscillation
Ceramic oscillation

EXTAL

AA

C

1 C2

Fig. 3. Event count clock timing

TEX
EC

XTAL

1/fc

t

XH tXLtCF tCR

32kHz clock applying condition

External clock

EXTAL

AA

74HC04

XTAL

crystal oscillation

TEX

AA

1

C

TX

0.8VDD

0.2VDD

DD – 0.4V

V

0.4V

C2

t

EH tELtEF tER

tTH tTLtTF tTR

– 15 –

CXP80712A/80716A/80720A/80724A

(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item

CS0 ↓→SCK0
delay time

CS0 ↑→SCK0
floating delay time

CS0 ↓→SO0
delay time

CS0 ↑→SO0
floating delay time

CS0
high level width

SCK0
cycle time

SCK0
high and low level widths

SI0 input setup time
(against SCK0 ↑)

SI0 input hold time
(against SCK0 ↑)

SCK0 ↓→SO0 delay time

Symbol Pin Min.

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK0

SCK0

SO0

SO0

CS0

SCK0

SCK0

SI0

SI0

SO0

Chip select transfer mode
(SCK0 = output mode)

Chip select transfer mode
(SCK0 = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode

Input mode
Output mode
Input mode
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode

tsys + 200

2tsys + 200

16000/fc

tsys + 100

8000/fc – 50

100
200

tsys + 200

100

Max. UnitCondition

tsys + 200

tsys + 200

tsys + 200

tsys + 200

tsys + 200

100

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Note 1) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11")

Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.

– 16 –

Fig. 4. Serial transfer CH0 timing

CXP80712A/80716A/80720A/80724A

tWHCS

CS0

SCK0

0.2V

DD

tKCY

tDCSK tDCSKF

tKL tKH

0.8VDD

0.2VDD

tKSI

t

SIK

0.8VDD

0.8VDD

SI0

SO0

0.8VDD

Input

data

0.2VDD

DCSO tKSO tDCSOF

t

Output

data

0.8V

0.2VDD

DD

– 17 –

CXP80712A/80716A/80720A/80724A

Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pins Min. Max. UnitConditions

SCK1 cycle time

SCK1 high and low
level widths

SI1 input setup time
(against SCK1 ↑)

SI1 input hold time
(against SCK1 ↑)

tKCY

tKH
tKL

tSIK

tKSI

SCK1

SCK1

SI1

SI1

Output mode
Input mode
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode

16000/fc

8000/fc – 50

SCK1 input mode

Input mode

SCK1 ↓→SO1 delay time

tKSO

SO1

SCK1 output mode

Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.

Fig. 5. Serial transfer CH1 timing

tKCY

tKL tKH

1000

400

100
200
200
100

200
100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

SCK1

SI1

SO1

tKSO

tSIK tKSI

Input data

0.8VDD

0.2VDD

0.8VDD

0.2V

Output data

0.8VDD

0.2VDD

DD

– 18 –

CXP80712A/80716A/80720A/80724A

(3) A/D converter characteristics

(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V)

Item Symbol Pins Conditions Min. Typ. Max. Unit

Resolution
Linearity error
Absolute error
Conversion time
Sampling time
Reference input voltage
Analog input voltage

tCONV
tSAMP

VREF
VIAN

AV

REF

AN0 to AN11

IREF

AVREF current

AVREF

IREFS

Fig. 6. Definitions of A/D converter terms

Ta = 25°C
VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V

Operating mode
SLEEP mode

STOP mode
32kHz operating mode

160/fADC

12/fADC

∗

AVDD – 0.5

0

8

Bits

±1±2LSB

LSB

∗

µs
µs

AVDD

V

V

0.6

1.0

mA

10 µA

FFH
FEH

Digital conversion value

01H
00H

Linearity error

Analog input

∗

The value of fADC is as follows by selecting ADC
operation clock (MSC: Address 01FFH bit 0).
When PS2 is selected, fADC = fc/2
When PS1 is selected, fADC = fc

V

FTVZT

– 19 –

CXP80712A/80716A/80720A/80724A

(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item Symbol Pins Conditions Min. Max. Unit

INT0

External interruption
high and low level widths

tIH
tIL

INT1
INT2
NMI
PJ0 to PJ7

1

µs

Reset input low level width

Fig. 7. Interruption input timing

INT0
INT1
INT2
NMI
PJ0 to PJ7
(During standby release input)
(Falling edge)

Fig. 8. Reset input timing

RST

tRSL

RST

tIH tIL

0.8VDD

tRSL

0.2VDD

32/fc

µs

0.2VDD

(5) Others (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

Item

CFG input
high and low level widths

DFG input
high and low level widths

DPG minimum pulse width
DPG minimum

removal time
PBCTL input

high and low level widths
EXI input

high and low level widths

Symbol Pins Min.

tCFH
tCFL

tDFH
tDFL

tDPW
trem
tCTH

tCTL
tEIH

tEIL

CFG

DFG
DPG
DPG

PBCTL
EXI0

EXI1

Conditions

tsys = 2000/fc

tsys = 2000/fc

tFRC × 24 + 200

tFRC × 8 + 200

50

50

tFRC × 8 + 200 + tsys

tFRC × 8 + 200 + tsys

Max. Unit

ns

ns

ns
ns

ns

ns

Note) tsys indicates three values according to the contents of the clock control register (address; 00FEH)

upper 2 bits (CPU clock selection).

tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11")
tFRC [ns] = 1000/fc

– 20 –

Fig. 9. Other timings

CXP80712A/80716A/80720A/80724A

tCFH tCFL

CFG

DFG

DPG

0.8VDD

0.2VDD

tDFH tDFL

0.8VDD

0.2VDD

trem tDPW trem

0.8VDD

PBCTL

EXI0
EXI1

tCTH tCTL

0.8VDD

0.2VDD

tEIH tEIL

0.8VDD

0.2VDD

– 21 –

Supplement

A

Fig. 10. Recommended oscillation circuit

(i) (ii)

CXP80712A/80716A/80720A/80724A

EXTAL

AAA

1

C

Manufacturer

RIVER
ELETEC
CO., LTD.

KINSEKI LTD.

XTAL

Rd

C2

Model

HC-49/U03

HC-49/U (-S)

P3

fc (MHz)

8.00

10.00

12.00

16.00

8.00

10.00

12.00

16.00

32.768kHz

TEX

AA

1

C

C1 (pF) C2 (pF)

TX

10

5

16
16
12
12
30

C2

Rd

10

5

12
12
12
12

18

Rd (Ω)

0

0

470k

Circuit

example

(i)

(i)

(ii)

Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2).

Mask option table

Item

Reset pin pull-up resistor
Input circuit format

∗

In PG4/SYNC0 pin and PG5/SYNC1 pin, the input circuit format can be selected to every pin.

∗

Non-existent

C-MOS schmitt

Content

Existent

TTL schmitt

– 22 –

Characteristics Curve

CXP80712A/80716A/80720A/80724A

(fc = 16MHz, Ta = 25°C, Typical)

20.0

10.0

5.0

1.0

0.5

– Supply current [mA]

DD

I

0.1

(100µA)

0.05

(50µA)

0.01

(10µA)

V

DD – Supply voltage [V]

IDD vs. VDD

3

45

1/2 dividing mode
1/4 dividing mode

1/16 dividing mode

SLEEP mode

32kHz mode
(instruction)

32kHz
SLEEP mode

72

6

(VDD = 5V, Ta = 25°C, Typical)

20

15

– Supply current [mA]

DD

I

10

5

0

510 16

fc – System clock [MHz]

IDD vs. fC

1/2 dividing mode

1/4 dividing mode

1/16 dividing mode

SLEEP mode

– 23 –

Package Outline Unit: mm

100PIN QFP (PLASTIC)

23.9 ± 0.4
+ 0.4

20.0 – 0.1

+ 0.4

17.9 ± 0.4

14.0 – 0.01

+ 0.1

0.15 – 0.05

15.8 ± 0.4

CXP80712A/80716A/80720A/80724A

A

SONY CODE
EIAJ CODE

JEDEC CODE

75

76

0.65

0° to 15°

±0.12

0.15

(16.3)

DETAIL A

QFP-100P-L01
∗QFP100-P-1420-A

0.8 ± 0.2

100PIN LQFP (PLASTIC)

16.0 ± 0.2

∗ 14.0 ± 0.1

M

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT
LEAD MATERIAL

PACKAGE WEIGHT

51

50

+ 0.35

2.75 – 0.15

EPOXY RESIN
SOLDER PLATING

COPPER / 42 ALLOY

1.4g

100

0.5 ± 0.08

SONY CODE
EIAJ CODE
JEDEC CODE

(15.0)

A

26

1

+ 0.08

0.18 – 0.03

(0.22)

25

+ 0.2

1.5 – 0.1

+ 0.05

0.127 – 0.02

0.5 ± 0.2

0.1

0.1 ± 0.1

NOTE: Dimension “∗” does not include mold protrusion.

0° to 10°

DETAIL A

LQFP-100P-L01

∗QFP100-P-1414-A

0.5 ± 0.2

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT

EPOXY/PHENOL RESIN
SOLDER PLATING
42 ALLOY

– 24 –