Datasheet CXP508L6, CXP508L4 Datasheet (Sony)

CXP508L4/508L6

For the availability of this product, please contact the sales office.

CMOS 4-bit Single Chip Microcomputer

Description

The CXP508L4/508L6 is a CMOS 4-bit micro­computer which consists of 4-bit CPU, ROM, RAM,
I/O port, 8-bit timer, 8-bit timer/counter, 18-bit time
base timer, 8-bit serial I/O, vector interruption, and a
liquid crystal displayer (LCD) controller/driver. They
are integrated into a single clip with the standby
function etc. which are to be operated at low power
consumption.

64 pin SDIP (Plastic) 64 pin QFP (Plastic)

Features

• Instruction cycle 4µs/2MHz (2.4V to 3.5V)

• ROM capacity 4.096 × 8 bits (CXP508L4)

6.144 × 8 bits (CXP508L6)

• RAM capacity 400 × 4 bits

(24 × 4 bits is used in combination
with the LCD display memory)

• 32 general purpose I/O ports

(For 16 segment outputs)

• LCD controller/driver (Direct drive possible)

— Optical specification of 24, 20 or 16 segment

outputs
— 1/2, 1/3, 1/4 duty selectable through program
— 1/3 bias

• 2 external interruption input pins

• 8-bit/4-bit variable serial I/O

• 8-bit timer, 8bit timer/event counter and 18-bit time

base timer are independently controllable

• Arithmetic and logical operations possible between
the entire RAM area, I/O area and the accumulator
by means of memory mapped I/O

• Reference to the entire ROM area is possible with
the table look-up instruction

• 2 types of power down models, sleep and stop

• 64-pin plastic SDIP/QFP available

• Piggy back package (CXP5080) available

Structure

Silicon gate CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E95108-ST

Block Diagram

CXP508L4/508L6

400 × 4

bits

(Enables to specify the
I/O with bit unit)

Port A Port B Port C Port D Port E Port F

Register

Data memory

Stack

Data memory

(Enables to specify the
I/O with port unit)

4 4 4 4

ALU

Accumulator

Flag

Timer (8)

Timer/Counter (8)

Serial I/O (8)

Interrupt control

(Combines use of mask with
segment output, optional)

Program counter

Program memory
6144 × 8 bits

(CXP508L6)
4096 × 8 bits

(CXP508L4)

(13)

LCD
controller/driver

VL
VLC1
VLC2
VLC3

SEG16

to

SEG23

(Common with Port E, Port F)

1684

SEG0

COM0

to

SEG15

to

COM3

Port YPort X

PX3/SI

(Common with serial I/O)

PX0/SC

PX2/SOA

PX1/SOB

PY3/EC

PY2/INT2

PY1

PY0

Instruction control

Time base timer

(18)

Clock control

SS

DD

WP

INT1

V

V

EXTAL
XTAL

RST

– 2 –

Pin Configuration (Top View)

2
3
4
5
6
7
8
9

10

11
12
13
14
15
16
17
18
19

20

21

22

23

24

25

26 27

28

29

30

31

32

1

40
39
38
37
36
35
34
33

41

42

43

44

45

46

47

48

49

50

51

PY0
PY1

INT2/PY2

EC/PY3

SC/PX0
SOB/PX1
SOA/PX2

SI/PX3

PD0
PD1
PD2
PD3
PC0
PC1
PC2
PC3
PB0
PB1
PB2

PB3

PA0

PA1

PA2

PA3

Vss

NC

PE3/SEG23

PE2/SEG22

PE1/SEG21

PE0/SEG20

PF3/SEG19

PF2/SEG18

COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16/PF0
SEG17/PF1

INT1

WP

RST

EXTAL

XTAL

V

L

V

DD

V

LC3

V

LC2

V

LC1

COM0

COM1

COM2

52

53

54

55

56

57

58

59

60

63

64

61

62

CXP508L4/508L6

XTAL

EXTAL

RST

WP

INT1

PY0
PY1

INT2/PY2

EC/PY3

SC/PX0
SOB/PX1
SOA/PX2

SI/PX3

PD0
PD1
PD2
PD3
PC0
PC1
PC2
PC3
PB0
PB1
PB2
PB3
PA0
PA1
PA2
PA3

NC

Vss

VL

1
2
3
4
5
6
7
8
9

10

11
12
13
14
15
16
17
18
19
20

21
22
23

24
25

26

27

28
29
30

31

32

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

VDD
VLC3
VLC2
VLC1
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16/PF0
SEG17/PF1
SEG18/PF2
SEG19/PF3
SEG20/PE0
SEG21/PE1
SEG22/PE2
SEG23/PE3

Note) Do not make any connection to NC pin.

– 3 –

CXP508L4/508L6

Absolute Maximum Ratings

Item
Power supply voltage
LCD bias voltage
Input voltage
Output voltage
High level output current
High level total output current
Low level output current
Low level total output current
Operating temperature
Storage temperature

Allowable power dissipation

∗1

VLC1, VLC2, VLC3, VIN and VOUT should not exceed VDD + 0.3V.

∗2

The PE and PF are specified when PA to PD, PX0 to PX2, PY0, PY1 and mask option are port selected.

Symbol Ratings Unit Remarks
VDD
VLC1, VLC2, VLC3
VIN
VOUT
IOH
∑IOH
IOL
∑IOL
Topr
Tstg

–0.3 to +5.0
–0.3 to +5.0
–0.3 to +5.0
–0.3 to +5.0

–5

–50

15
50

–20 to +75

–55 to +150

1000

∗1
∗1
∗1

V
V
V

V
mA
mA
mA
mA

°C
°C

mW

PD

600

mW

(Ta = –20 to +75°C, VSS = 0V)

General purpose port∗2: per pin
Entire pin total
General purpose port∗2: per pin
Entire pin total

SDIP
QFP

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.

Recommended Operating Conditions

Item

Power supply voltage VDD

Symbol Min.

2.4

2.0

Max. Unit Remarks

3.5

3.5

V

Guaranteed range during operation
Guaranteed data hold operation range

V

during STOP

VLC1,

LCD bias voltage

VLC2,

VSS

VDD

V

Liquid crystal power supply voltage

VLC3
VIH

High level input voltage

VIHS
VIHEX
VIL

Low level input voltage

VILS
VILEX

Operating temperature

∗1

The optimum value is determined by the characteristics of the liquid crystal display element used.

∗2

They are the respective pins of INT1, WP, PX0, PX3, PY2, PY3 and RST.

∗3

Specified only during external clock input.

Topr

0.7VDD

0.8VDD

VDD – 0.4

0
0

–0.3

–20

VDD
VDD

VDD + 0.3

0.3VDD

0.2VDD

0.4

+75

V
V

Hysteresis input

V

EXTAL pin
V
V

Hysteresis input
V

EXTAL pin

°C

∗2

∗3

∗2

∗3

(VSS = 0V)

∗1

– 4 –

CXP508L4/508L6

Electrical Characteristics
DC characteristics (Ta = –20 to +75°C, VSS = 0V)

Item

High level output
voltage

Low level output
voltage

Input current

High impedance
I/O leakage current

Common output
impedance

Segment output
impedance

Symbol Pin Condition Min. Typ. Max. Unit

VOH

PA to PF∗1,
PX0 to PX2,
PY0, PY1,

VDD = 2.4V, IOH = –0.3mA
VDD = 2.4V, IOH = –0.5mA
VDD = 2.4V, IOH = –5µA
VDD = 2.4V, IOH = –10µA

∗3

∗3

∗2
∗2

1.8

1.4

1.8

1.4

V
V
V
V

VL (VOL only)

VDD = 2.4V, IOL = 1.0mA

0.4

V

VOL

IIH
IILE
IILR
IIL

EXTAL

RST

∗4

∗5

PA to PF∗6,

VDD = 2.4V, IOL = 2.0mA
VDD = 3.5V, VIH = 3.5V

VDD = 3.5V, VIL = 0.4V

0.3
–0.3
–1.5

0.6
20

–20

–200

–1.0

V
µA
µA
µA

mA
PX0 to PX2∗6,
PX3∗8, PY0∗7,

IIZ

RCOM

PY1∗7, PY2∗8,
PY3∗8, INT1∗8,
WP∗8, RST

∗5

COM0 to COM3

VDD = 3.5V
VI = 0, 3.5V

VDD = 3.5V

±5

3

µA

5

kΩ

VLC1 = 2.65V

RSEG

SEG0 to SEG15
SEG16 to SEG23

VLC2 = 1.75V

∗1

VLC3 = 0.88V

5

15

kΩ

VDD = 3.5V During external clock
1MHz operation
Entire output pins open

SLEEP mode
STOP mode

1.3

0.6

4

1.2
7

Current power
supply

IDD

VDD

IDDSP
IDDS

VLC1 to VLC3,

Input capacitance

CIN

COM0 to COM3,
SEG0 to SEG15,
SEG16 to SEG23∗1,
Other pins than VDD,

Clock 1MHz
0V other than the measured
pins

10

20

VSS

∗1

The PE to PF show when the combined pins are selected as the port, and SEG16 to SEG23 show when
the combined pins are selected as the segment output.

∗2

It is when the respective pins of PA to PF and PX0 to PX2 select the 3-state output circuit, and PY0 and
PY1 are when the inverter output circuit is selected.

∗3

It is when the respective pins of PA to PF, PX0 to PX2, PY0 and PY1 select the pull-up resistance.

∗4

It is when the crystal or ceramic oscillation circuit is selected.

∗5

The RST pin specifies the input current when the pull-up resistance is selected, and specifies leakage
current when non-resistance is selected.

∗6

The respective pins of PA to PF and PX0 to PX2 specify the input current when the pull-up resistance is
selected, and specify the leakage current when in the port state during the 3-state output circuit or standby
is selected at high impedance.

∗7

The respective pins of PY0 and PY1 specify the input current when the pull-up resistance is selected, and
specify the leakage current when in the port state during standby is selected at high impedance.

∗8

The respective pins of PX3, PY2, PY3, INT1 and WP only specify the leakage current.

mA

mA

µA

pF

– 5 –

CXP508L4/508L6

A

A

AC characteristics

(1) Clock timing (Ta = –20 to +75°C, VDD = 2.4 to 3.5V, VSS = 0V)

Item

System clock frequency

System clock input pulse width
System clock input rising and falling

times
Event count clock input pulse width
Event count clock input rising and

falling times

∗1

The external clock in Fig. 2. specified only when the option is selected for crystal or ceramic oscillation.

∗2

tsys = 8/fc

Note) When adjusting the frequency accurately, there may be cases in which they may differ from Fig. 2.

Fig. 1. Clock timing

EXTAL

Symbol Pin Condition Min. Max. Unit

fc

tXL
tXH

tCR
tCF

tEL
tEH

tER
tEF

XTAL
EXTAL

EXTAL

EXTAL

EC

EC

Fig. 1., Fig. 2.
Fig. 1., Fig. 2.

External clock drive
Fig. 1., Fig. 2.

External clock drive
Fig. 3.

Fig. 3.

1/fc

∗1

∗1

0.5

230

∗2

tsys

+ 0.05

VDD – 0.4V

0.4V

2

200

20

MHz

ns

ns

µs

ms

Fig. 2. Clock applying condition

Crystal oscillation
Ceramic oscillation

EXTAL

AA

C

1 C2

Fig. 3. Event count clock timing

EC

t

XH tXLtCF tCR

External clock

XTAL

EXTAL

AA

∗

XTAL

OPEN

1

0.8VDD

0.2VDD

EH tELtEF tER

t

– 6 –

CXP508L4/508L6

(2) Serial transfer (Ta = –20 to +75°C, VDD = 2.4 to 3.5V, VSS = 0V)

Item

Serial transfer clock (SC)
cycle time

Serial transfer clock (SC)
high and low level widths

Serial data input setup time
(against SC ↑)

Serial data input hold time
(against SC ↑)

High data∗3output delay time
from the SC falling time

High data∗4output delay time
from the SC falling time

Low data output delay time
from the SC falling time

Symbol Pin Condition Min. Max. Unit

tKCY

tKH
tKL

tSIK

tKSI
tKSOA

tKSOB
tKSOA
tKSOB
tKSOA
tKSOB

SC

SC

SI

SI

SOA
SOB
SOA
SOB
SOA
SOB

Input mode
Output mode
input mode
Output mode
Output mode
SC input mode
SC output mode
SC input mode
SC output mode

∗1
∗2

tsys/4 + 1.42

tsys
tsys/8 + 0.7
tsys/2 – 0.1
tsys/2 – 1.6

0.1

0.2

tsys/8 + 0.5

0.1

tsys/8 + 0.5

tsys/8 + 1.6

tsys/8 + 0.5

µs
µs
µs
µs
µs
µs
µs
µs
µs

µs

µs

µs

Note 1) tsys = 8/fc
Note 2) The load of data output delay time is 50pF + 1TTL.

∗1

It is specified when SC pin is selected to the 3-atate output by the mask option.

∗2

It is specified when SC pin is selected to the pull-up resistance by the mask option. As the tsys receives
restriction by this item, take notice that it limits the upper limit of the system clock frequency fc.

∗3

It is specified when SOA and PX1/SOB pins are selected to the 3-state output by the mask option.

∗4

It is specified when SOA and PX1/SOB pins are selected to the pull-up resistance by the mask option.

– 7 –

Fig. 4. Serial transfer timing

t

KCY

tKL tKH

CXP508L4/508L6

SC

SI

SOA
SOB

tKSOA
tKSOB

tSIK tKSI

Input data

0.8VDD

0.2VDD

Output data

0.8VDD

DD

0.2V

0.8VDD

0.2VDD

(3) Others (Ta = –20 to +75°C, VDD = 2.4 to 3.5V, VSS = 0V)

Item

External interruption high and
low level widths

Reset input low level width

Wake-up input high level width

Symbol Pin Condition Min. Max. Unit

tI1H, tI1L
tI2H, tI2L
tRSL

tWPH

INT1
INT2
RST

WP

During edge detection mode

STOP mode
SLEEP mode

tsys + 0.05
tsys + 0.05

2tsys

500

tsys + 0.05

µs
µs
µs
ns
µs

Note) tsys = 8/fc

– 8 –

Fig. 5. Interruption input timing

CXP508L4/508L6

tI1L tI1H

INT1
(Rising edge)

INT1
(Falling edge)

INT2

Fig. 6. Reset input timing

0.8VDD

0.2VDD

tI1H tI1L

0.8VDD

0.2VDD

tI2L tI2H

0.8VDD

0.2VDD

tRSL

RST

Fig. 7. Wake-up input timing

WP

0.2VDD

tWPH

0.8VDD

– 9 –

CXP508L4/508L6

A

A

A

Notes on Operation

See Fig. 8., Additive capacity calculation chart, when using the crystal oscillator and select the appropriate
capacity.

Fig. 8. Crystal oscillation circuit additive capacity calculation chart (Ta = –20 to +75°C, VDD = 2.4 to 3.5V)

200

EXTAL XTAL

150

C1

C2

100

C-Additive capacity [pF]

50

A
A

C1 = C2 = C

A

0.1 1 5 100
f-Crystal oscillation frequency [MHz]

Note) The above chart shows a range in which the average quartz resonator has a relatively fast oscillation

rising edge and stable characteristics. The capacity should be selected to correspond to the appropriate
constant for each quartz resonator, should the frequency of the quartz resonator be accurately
adjusted.

Fig. 9. Shows recommended circuit and oscillators. Use the trimmer capacitor to C1, in the case of accurate
adjustment of the oscillation frequency.

Fig. 9. Recommended oscillation circuit

Manufacturer

Model

Frequency

C1 C2 Rd

EXTAL XTAL

Rd

C1 C2

MURATA MFG
CO., LTD.

CSA2.00MG040

CST2.00MG040

– 10 –

2.00MHz

2.00MHz

100pF

—

(built in)

100pF

—

(built in)

—

—

Package Outline Unit: mm

CXP508L4/508L6

64PIN SDIP (PLASTIC) 750mil

+ 0.4

57.6 – 0.1

64

33

+ 0.3

19.05

17.1 – 0.1

+ 0.1

132

1.778
+ 0.4

4.75 – 0.1

0.5 MIN

0.5 ± 0.1

3 MIN

0.9 ± 0.15

PACKAGE STRUCTURE

EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY

8.6g

SONY CODE
EIAJ CODE
JEDEC CODE

SDIP-64P-01

SDIP064-P-0750-A

MOLDING COMPOUND
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT

0.25 – 0.05

0° to 15°

52

64

SONY CODE
EIAJ CODE
JEDEC CODE

64PIN QFP(PLASTIC)

23.9 ± 0.4
+ 0.4

20.0 – 0.1

51

1

1.0

+ 0.15

0.4 – 0.1

33

32

+ 0.4

14.0 – 0.1

17.9 ± 0.4

20

19

± 0.12

+ 0.35

2.75 – 0.15

M

PACKAGE STRUCTURE

QFP–64P–L01

∗

QFP064–P–1420

PACKAGE MATERIAL

LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT

EPOXY RESIN
SOLDER/PALLADIUM

COPPER /42 ALLOY

1.5g

0.15 – 0.05

+ 0.2

0.1 – 0.05

PLATING

+ 0.1

0.15

16.3

0.8 ± 0.2

– 11 –