Datasheet CXL1008P, CXL1008M Datasheet (Sony)

CXL1008M/P

CMOS-CCD Signal Processor for Skew Compensation

Description

CXL1008M/P are CMOS-CCD signal processors developed for the variable-speed video signal processor for home-use 8mm VCRs.

Features

• Low power consumption 105mW (Typ.)

• Built-in peripheral circuit

• Adjustment is necessary for one part.

Structure

CMOS-CCD

Functions

• 1/2H 359-bit, direct 20-bit CCD register

• Clock driver

• Timing oscillation circuit

• Automatic bias circuit

• Sync tip clamp circuit

• Dummy VD insert circuit

• Sample/hold circuit

CXL1008M

28 pin SOP (Plastic)

CXL1008P

28 pin DIP (Plastic)

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VDD 11 V

VCL 6V

•Operating temperature Topr –10 to +60 °C

• Storage temperature Tstg –55 to +150 °C

• Allowable power dissipaiton

PD CXL1008M 500 mW

CXL1008P 1000 mW

Recommended Operating Conditions

Supply voltage VDD 9V ± 5 %

VCL 5V ± 5 %

Recommended Clock Conditions

• Clock input amplitude VCLK 0.15 to 1.0 (0.3 Typ.) Vp-p

• Clock frequency fCLK 10.738635 MHz

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E60248-PS

Block Diagram

13

AUTO

FEED OUT

24

FEED IN

25

CCD OUT

23

21

SIG DELAY

SIG IN2

12

CXL1008M/P

SIG OUT

19

AUTOBIAS

CIRCUIT

T10

T9

T1

T2

11

28 27

26

SKEW

2

3

SIG IN1

SKEW IN

4

T3

Pin Configuration (Top View)

1/2H

OUTPUT

D

CIRCUIT

50mV

REFERENCE

OUTPUT

φ1

CONTROL

φ2

DRIVER

DUTY

CONTROL

6

5

T4

T5

18

1

SS

V

SS

V

14

20

CL

V

TIMING

GENERATOR

DD

V

7

CLK IN

22

REC/PB

8

T6

10

17

16 15

9

MUTE IN

JOG IN EXT VD T8

T7

T8

EXT VD

JOG IN

V

SIG OUT

DD

V

SIG DELAY

REC/PB

CCD OUT

FEED OUT

FEED IN

SKEW IN

T9

T10

SS

15 16 17 18 19 20

23

21 22

24 25 26 27 28

14 13 12 11 10

9 8 7 6 5 4

3 2

1

VCL AUTO SIG IN2 SIG IN1 MUTE IN T7 T6 CLK IN T5 T4 T3 T2 T1

SS

V

– 2 –

Pin Description

CXL1008M/P

Pin No.

1 7

10

11

12 13

14 16

17

18

Symbol I/O

VSS CLK IN

MUTE IN

SIG IN1

SIG IN2 AUTO

VCL EXT VD

JOG IN

VSS

I

0.3Vp-p 5V when

I

muting, normally 0V

1.1Vp-p or

I

less

2.2Vp-p or

I

less

O

+5V 5V when VD

I

is inserted JOG mode

I

PB/REC mode 0V

Supply voltage

Description

GND Input the sine wave of 3fsc (10.738635MHz) The video signal mute is generated at High level.

See the Logic Table of Signal Output Selection State (Table 1).

Signal input pin of CCD DL. Input composite video signal.

Signal input pin of the through side. Input composite video signal.

The DC level of automatic bias is output. Power supply 1 Use this pin when VD is inserted to the video signal

with the extrenal dummy VD signal input. JOG/NORMAL PB selection pin.

5V

See the Logic Table of Signal Output Selection State (Table 1).

GND

Impedance

(Ω)

> 50k

> 100k

> 100k 10k

> 100k

19 20

21

22 23

24 25

SIG OUT VDD

SIG DELAY

REC/PB CCD OUT

FEED OUT FEED IN

O

+9V

I

5V when PB

I

0V when REC O O

I

Final output Power supply 2 After the output from Pin 23 CCD OUT passes through

LPF, input it to the same pin and insert clamp and VD. Operate the clock at High when PB.

Stop the clock at Low when REC. Direct output from CCD DL Feedback DC output Smoothing capacitor connection pin of the bias

commutation loop on the output circuit

0.6 to 1.5k

> 100k

0.6 to 1.5k 10k

> 100k

Select Direct DL and 1/2H DL signals when High

26

SKEW IN

I

and Low, respectively. See the Logic Table of CCD DL Mode Selection

> 100k

(Table 2).

Note) T1 through T10 test pins must be connected as shown in the application circuit because of the IC

internal circuit.

Notes on Handling

Countermeasures for electrostatics are necessary because some pins have low electrostatic strength (particularly Pin 26: SKEW IN).

– 3 –

Unit Note

Max.

Min. Typ.

1

mA

12

7

1

mA

10

8

V

1.0

0.3

0.15

2

V

6.0

5.0

4.0

2

V

4.4

4.2

4.0

2

V

4.4

4.2

4.0

3

V

2.4

2.0

1.7

3

V

2.5

2.0

1.5

4

mV

55

0

–55

5

dB

3.0

0

–3.0

5

dB

0

–0.8

–1.2

5

dB

0

–0.8

–1.2

6

%

1.3

0

–1.3

7

dB

0

–2

–3

8

dB

—

0

–0.5

8

dB

—

0

–0.5

9

dB

0.2

0

–0.2

CXL1008M/P

10

%

4

10

3

2

0

10

%

4

2

0

H

∗1, ∗2

P2 P3 P4 P5

Control Pin Conditions

DD = 9.0V, VCL = 5.0V, fCLK = 10.7MHz, VCLK = 0.3Vp-p sine wave)

a

2 3 4 5 P1

a

Switch Conditions

c

1

c

H ←→ L

H

e

a

c

b

H

e

a

a c

a

H

H L L L

a a

e

a

a c

b

L L L

a

b f

a

b

c

b

H ←→ L H

H H L L a

a

b

a

f

a

b

b c

a

L L L

b

a

b

b ←→ c

b ←→ d

b

c

b

H ←→ L H

H H L L b

b

a

b ←→ c

b ←→ d b

b c

a

L

H

L

c

a

b

g

b

c

b

a

PB, JOG

Symbol Test Conditions

DD

I

ICL

Items

Electrical Characteristics

(See the Electrical Characteristics Test Circuit) (Ta = 25°C, V

Power current

CLK

Vdi1

Vdi2

Vdi3

Clock input level

Signal input pin voltage

Direct ←→ 1/2H

Vdo1

Vdo2

∆Dab

IGCCD

IGIn2

Signal output pin voltage

CCD signal output

voltage difference

Signal insert gain

– 4 –

Direct ←→ 1/2H

3.58MHz/100kHz

10MHz/100kHz

IGDL

∆Gab

fCCD

fIn2

CCD output signal gain

difference

Frequency characteristics

10MHz/100kHz

Direct ←→ 1/2H at 3.58MHz

1.1Vp-p input

2.2Vp-p input

fDL

∆fab

DGCCD

DGIn2

DGDL

Frequency characteristics

difference

Differential gain

Unit Note

Max.

Min. Typ.

10

deg

5

3

0

10

deg

5

3

0

10

deg

5

3

0

Vp-p

1.1

—

Vp-p

2.2

—

11

dB

—

55

50

11

dB

—

65

50

11

dB

—

65

50

12

mV

100

50

0

V

—

4.0

CXL1008M/P

V

1.0

—

H

∗1, ∗2

P2 P3 P4 P5

Control Pin Conditions

2 3 4 5 P1

Switch Conditions

1

L

H

L

c

a

b

g

b

c

b

a

1.1Vp-p input

2.2Vp-p input

H

L

H

L

d

a

b

g

f ←→ e

a ←→ e b

b

c

a/b

c

b

g

f ←→ e b

a

2Vp-p video signal from

sync tip

Symbol Test Conditions

CCD

DP

DPIn2

Items

Differential phase

DPDL

VIN1–AC

VIN2–AC

S/NCCD

S/NIn2

Allowable input amplitude

S/N rate

S/NDL

VVD

VD insert depth

VIN H

VIN L

Control pins correspond to P1 through P5 of the Electrical Characteristics Test Circuit.

Logical input

1

∗

– 5 –

Symbols "H" and "L" in control pin conditions represent "VIN H" and "VIN L" of logical input.

∗2

ANALYZER

SPECTRUM

OSCILLOSCOPE

VECTOR SCOPE

×1

NOISE METER

GROUND

100kHz 1.1Vp-p SINE WAVE

100kHz 300mVp-p SINE WAVE

b

a

10MHz 300mVp-p SINE WAVE

3.58MHz 300mVp-p SINE WAVE

c

d

e

CXL1008M/P

5-STAIR CASE WAVE

100kHz 2.2Vp-p SINE WAVE

f

g

14

13

12

11

10

9

8

7

6

5

4

3

2

1

10µ

100k

SW3

A1

5V

0.1µ

5V

P1

0.1µ

SW1

a

b

CLK

V1

b

a

SW2

c

Note 2) BPF Frequency Response

Note 1) LPF Frequency Response

BIAS

V

20k1M

Frequency [Hz]

200 50

0

–3

[dB]

0

–3

(Delay Time to 140ns)

[dB]

0 4.1M 10.7M

–50

Frequency [MHz]

0 5.8 10.7

–50

LPF

c

BPF

×1 ×1

0.1µ d

2SA1175

V2

220k

10µ

0.1µ

Note 2)

P2P3P5

9V

P4

5V

22µ

390k

A2

15

16

17

18

19

20

21

22

23

10k

24

25

2627

28

Note 1)

×1

a

b

SW5

SW4

a

2k

b

2k

2SA1175

V3

9V

5V

Electrical Characteristics Test Circuit

– 6 –

CXL1008M/P

Notes)

1) Current value when the clock is in operation in the PB or JOG mode. In the REC mode, the clock is stopped (Pin 22 is at low) to save power.

2) With the signal input pin voltage value, the video signal sync tip is clamped.

3) Vdo1 is a CCD OUT output voltage when the SIG IN1 input voltage is Vdi1. Vdo2 is a SIG OUT output voltage when the SIG IN2 input voltage is Vdi2. Vdo1 and Vdo2 represent outputs for the sync tip clamp level when a white level signal is input as shown in the diagram.

Output signal

Vdo

100%40%

1.0Vp-p

Vdi Input signal

4) ∆Dab denotes an output voltage difference of CCD OUT when the direct DL and 1/2H DL are switched.

5) IGCCD is a CCD OUT gain when a 1.1Vp-p 100kHz sine wave is input to SIG IN1.

IGCCD = 20 log

Output amplitude (Vp-p)

1.1Vp-p

It is measured by giving a Vdi1 + 0.6 bias with VBias. IGin2 and IGDL are SIG OUT gains when 2.2Vp-p 100kHz sine wave is input to each of SIG IN2 and SIG DELAY pins.

IGin2 = 20 log

Output amplitude (Vp-p)

2.2Vp-p

It is measured by giving a Vdi2 + 1.1V bias with VBias.

– 7 –

CXL1008M/P

6) ∆Gab is a gain difference between the direct DL and 1/2H DL.

7) It represents a loss at 3.58MHz compared with 100kHz. It is measured by raising the SIG IN1 input pin by 0.6V higher than the sync tip clamp level (Vdi1) with VBias.

3.85MHz 300mVp-p sine wave 100kHz 300mVp-p sine wave

SIG IN1 DC

F

CCD = 20 log

V3.58MHz output

VBias = Vdi1 + 0.6V

V100kHz output

8) It represents a loss at 10MHz compared with 100kHz. It is measured by raising the SIG IN2 or SIG DELAY input pin by 1.1V higher than the sync tip clamp level (Vdi2 or Vdi3) with VBias.

9) ∆Fab is a frequency response difference between the direct DL and 1/2H DL.

10)

Chroma 40 IRE

140 IRE

1H 63.5µs

1.1Vp-p at DGCCD

2.2Vp-p at DGin2 or DGDL

40 IRE

DG is measured with a vectorscope in each mode of the 5-stage waves.

11) Measure S/N of the BPF 100kHz to 4.2MHz in the subcarrier trap mode with a video noise meter.

12)

SIG DELAY Input waveform

EXT VD input

SIG OUT Output waveform

VD

V

2Vp-p

Set a voltage value at VVD when inserting EXT VD to the 2Vp-p signal output waveform sync tip of SIG OUT.

– 8 –

CXL1008M/P

CLOCK

3fsc (10.738635MHz) Sine wave

0.15 to 1.0Vp-p

Function Outline

Output signal selection

SIG IN2 (PB)

SIG DELAY (JOG)

50mV REF

SIG OUT

The video output signal is selected by selecting the output switch for three signals: Pin 10 (MUTE IN), Pin 17 (JOG IN) and Pin 16 (EXT VD).

Table 1. Logic Table of Signal Output Selection State

Input control signal state Video signal output selection state

JOG IN

0 0 0 0 1 1 1 1

MUTE IN EXT VD PB JOG VD insert MUTE

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

O O

× × × × × ×

× × × ×

O

× × ×

× × × × ×

O

×

O

× ×

O O

× ×

O O

Note 1) Figures "0" and "1" of the input control signal state are equivalent to "Low" and "High" of logic. Note 2) Items marked with the symbol "O" in the video signal output selection state are selected. Note 3) PB = JOG IN · MUTE IN

JOG = JOG IN · MUTE IN · EXT VD VD insert = JOG IN · EXT VD MUTE = MUTE IN

– 9 –

CXL1008M/P

CCD selection

SIG IN1

Application Circuit

SKEW IN

1/2H (359bit)

D (20bit)

10µ

220k

2728

10µ

26

4.7k2.2k

10k

SKEW IN

390

220

10k

25

10µ

2k

24

22µ

CCD OUT

8.2k390

18k

REC/PB

23

0.022µ

1M

22

1k

1.8k

120 10µH

220p 270p

47µ

21

20

Table 2. Logic Table of CCD DL Mode

Selection

1.5k

19

Control signal

SKEW IN

JOG

1000p

18

IN

17

0 1

560

EXT

VD

16

CCD DL mode

D

×

O

9V

SIGNAL OUTPUT

220k

15

1/2H

O

×

6

1

2

3

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

5

4

100k

7

0.01µF

3fsc

0.3Vp-p

SINE WAVE

Transistor to be used PNP: 2SA1175

9

8

10

MUTE

IN

2M

11

2M

0.047µ

12

10µ

0.047µ

13

510

14

5V

47µ 1000p

510

Frequency characteristics (Ta = 25°C)

0

–1

Gain [dB]

–2

SIGNAL INPUT

10k 100k 1M

f – Frequency [Hz]

– 10 –

CXL1008M/P

Supply voltage (VCL) vs.

2

1

0

–1

– Insert gain [dB]

CCD

IG

–2

–3

Supply voltage (VCL) vs.

Differential gain (DG

5

4

Insert gain (IG

CCD)

5.004.75

V

CL – Supply voltage [V]

CCD)

5.25

Supply voltage (VCL) vs.

Frequency characteristics (f

1

0

–1

–2

–3

– Frequency characteristics [dB]

CCD

f

–4

5.004.75

V

CL – Supply voltage [V]

Supply voltage (VCL) vs.

Output pin voltage (V

2.5

CCD)

5.25

do1)

3

2

– Differential gain [%]

CCD

1

DG

0

V

CL – Supply voltage [V]

Supply voltage (VDD) vs.

Insert gain (IG

2

1

0

–1

– Insert gain [dB]

CCD

IG

–2

–3

V

DD – Supply voltage [V]

2.0

1 – Output pin voltage [V]

do

V

1.5

5.004.75

5.25

5.004.75

V

CL – Supply voltage [V]

5.25

Supply voltage (VDD) vs.

CCD)

– Frequency characteristics [dB]

CCD

f

9.08.5

9.5

Frequency characteristics (f

1

0

–1

–2

–3

–4

V

DD – Supply voltage [V]

CCD)

9.08.5

9.5

– 11 –

CXL1008M/P

Supply voltage (VDD) vs. Differential gain (DG

5

4

3

2

– Differential gain [%]

CCD

DG

1

0

V

DD – Supply voltage [V]

Ambient temperature (Ta) vs.

Insert gain (IG

2

1

Supply voltage (VDD) vs.

CCD)

2.5

2.0

1 – Output pin voltage [V]

do

V

9.08.5

9.5

1.5

Output pin voltage (V

9.08.5

V

DD – Supply voltage [V]

do1)

9.5

Ambient temperature (Ta) vs.

CCD)

Frequency characteristics (f

1

0

CCD)

0

–1

– Insert gain [dB]

CCD

IG

–2

–3

Ta – Ambient temperature [°C]

Ambient temperature (Ta) vs.

Differential gain (DG

5

4

3

2

– Differential gain [%]

CCD

DG

1

–1

–2

– Frequency characteristics [dB]

–3

CCD

f

200

40

60

–4

200

6040

Ta – Ambient temperature [°C]

Ambient temperature (Ta) vs.

CCD)

2.5

2.0

1 – Output pin voltage [V]

do

V

Output pin voltage (V

do1)

0

200

40

60

Ta – Ambient temperature [°C]

1.5 200

6040

Ta – Ambient temperature [°C]

– 12 –

Package Outline Unit: mm

CXL1008M/P

CXL1008M

28PIN SOP (PLASTIC)

+ 0.4

18.8 – 0.1

28 15

+ 0.3

114

0.45 ± 0.1

0.24

M

1.27

PACKAGE STRUCTURE

PACKAGE MATERIAL

SONY CODE EIAJ CODE

JEDEC CODE

SOP-28P-L02 SOP028-P-0375

LEAD TREATMENT LEAD MATERIAL

7.6 – 0.1

10.3 ± 0.4

PACKAGE MASS

9.3

+ 0.1

0.15 – 0.05

+ 0.4

2.3 – 0.15

0.15

+ 0.2

0.1 – 0.05

0.5 ± 0.2

EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY

0.6g

CXL1008P

28PIN DIP (PLASTIC)

+ 0.4

37.8 – 0.1

28 15

+ 0.3

15.24

13.0 – 0.1

114

Two kinds of package surface:

1.All mat surface type.

2.Center part is mirror surface.

SONY CODE EIAJ CODE JEDEC CODE

2.54

0.5 ± 0.1

1.2 ± 0.15

DIP-28P-03 DIP028-P-0600

+ 0.4

4.6 – 0.1

0.5 MIN

3.0 MIN

PACKAGE STRUCTURE

PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS

EPOXY RESIN SOLDER PLATING COPPER ALLOY

4.2g

+ 0.1

0.25 – 0.05

0° to 15°

– 13 –