Datasheet CXK5V8257BYM, CXK5V8257BTM, CXK5V8257BM-70LL, CXK5V8257BM-10LL Datasheet (Sony)

CXK5V8257BTM/BYM/BM -70LL/10LL

For the availability of this product, please contact the sales office.

32768-word × 8-bit High Speed CMOS Static RAM

Description

The CXK5V8257BTM/BYM/BM is 262,144 bits
high speed CMOS static RAM organized as 32768­words by 8 bits.

A polysilicon TFT cell technology realized extermely
low stand-by current and higher data retention stability.

Operating on a single 3.3V supply, directly LVTTL
compatible (All inputs and outputs).

And special feature are, low power consumption,
high speed and broad package line-up.

The CXK5V8257BTM/BYM/BM is a suitable RAM
for portable equipment with battery back up.

Features

• Single +3.3V supply: 3.3V ±0.3V

• Directly LVTTL compatible: All inputs and outputs

• Fast access time: (Access time)

CXK5V8257BTM/BYM/BM

-70LL 70ns (Max.)

-10LL 100ns (Max.)

• Low standby current:

CXK5V8257BTM/BYM/BM

-70LL/10LL 3.5µA (Max.)

• Low power data retention: 2.0V (Min.)

• Available in many packages

CXK5V8257BTM/BYM 8mm × 13.4mm 28 pin

TSOP Package

CXK5V8257BM 450mil 28 pin

SOP Package

CXK5V8257BTM

28 pin TSOP (Plastic)

CXK5V8257BM

28 pin SOP (Plastic)

Block Diagram

A14
A13
A12
A11

A9
A8
A7
A6
A5

A10

A4
A3
A2
A1
A0

Buffer

Buffer

CXK5V8257BYM

28 pin TSOP (Plastic)

Row

Decoder

Memory

Matrix

512 × 512

I /O Gate

Column

Decoder

VCC

GND

Function

32768-word × 8 bit static RAM

Structure

OE

WE

CE

Buffer

I /O Buffer

I /O8

I /O1

Silicon gate CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E93836A5Z-ST

Pin Configuration (Top View) Pin Description

CXK5V8257BTM/BYM/BM

21

OE

A11

A13

WE

Vcc
A14
A12

A12
A14

Vcc

WE
A13

A11

OE

22
23

A9

24

A8

25
26

27
28

1
2
3

A7

4

A6

5

A5

6

A4

7

A3
A3

7

A4

6
5

A5

4

A6

3

A7

2
1

28
27

26

A8

25

A9

24
23
22

CXK5V8257BTM

(Standard Pinout)

CXK5V8257BYM

(Mirror Image Pinout)

A10

A14

20

CE
I/O8

19

I/O7

18

I/O6

17

I/O5

16
15

I/O4

14

GND

13

I/O3

12

I/O2

11

I/O1

10

A0

9

A1

8

A2

8

A2

9

A1

10

A0

11

I/O1

12

I/O2

13

I/O3

14

GND

15

I/O4
I/O5

16

I/O6

17

I/O7

18

I/O8

19

CE

20

A10

21

1

A12

2

A7

3

A6

4

A5

5
6

A4

7

A3

8

A2

9

A1

10

A0

11

I/O1

12

I/O2

13

I/O3

14

GND

CXK5V8257BM

28
27
26
25
24
23
22
21
20
19
18
17
16
15

Absolute Maximum Ratings (Ta = 25°C, GND = 0V)

Item Symbol Rating Unit

Supply voltage

VCC

–0.5 to +4.6

V

Vcc
WE
A13
A8
A9
A11
OE
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4

Symbol Description
A0 to A14
I/O1 to I/O8
CE
WE
OE
VCC
GND

Address input
data input/output
Chip enable input
Write enable input
Output enable input
+3.3V power supply
Ground

Input voltage
Input and output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Soldering temperature · time

∗1

VIN, VI/O = –3.0V Min. for pulse width less than 50ns.

VIN
VI/O
PD
Topr
Tstg
Tsolder

–0.5∗1to VCC + 0.5
–0.5∗1to VCC + 0.5

0.7

0 to +70

–55 to +150

235 · 10

V
V

W
°C
°C

°C · s

Truth Table

CE OE WE Mode I/O1 to I/O8 VCC Current

H

×

×

Not selected

L

H

H

Output disable

L

L

H

Read

L

×

L

Write

High Z
High Z
Data out
Data in

ISB1, ISB2
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2

× : “H” or “L”

DC Recommended Operating Conditions (Ta = 0 to +70°C, GND = 0V)

Item Symbol Min. Typ. Max. Unit
Supply voltage
Input high voltage
Input low voltage

∗2

VIL = –3.0V Min. for pulse width less than 50ns.

VCC

VIH
VIL

3.0

2.0

–0.3

∗2

3.3
—
—

– 2 –

3.6

VCC + 0.3

0.8

V

CXK5V8257BTM/BYM/BM

Electrical Characteristics

• DC characteristics (VCC = 3.3V ± 0.3V, GND = 0V, Ta = 0 to +70°C)

∗

—

1

Max. Unit

0.5

µA

Item Symbol Test Conditions Min. Typ.

Input leakage current

ILI

VIN = GND to VCC

–0.5

Output leakage
current

Operating power
supply current

Average operating
current

Standby current

Output high
voltage

Output low
voltage

∗

1

VCC = 3.3V, Ta = 25°C

ILO

ICC1

ICC2

ISB1

ISB2
VOH

VOL

CE = VIH,
OE = VIH or WE = VIL,
VI/O = GND to VCC

CE = VIL,
VIN = VIH or VIL,
IOUT = 0mA

Min. cycle,
Duty = 100%, IOUT = 0mA

CE ≥ VCC – 0.2V

CE = VIH
IOH = –2mA

IOL = 2.0mA

70LL
10LL
0 to +70°C

0 to +40°C
+25°C

–0.5

—

—
—
—
—
—
—

2.4

—

—

0.9

21
18
—
—

0.12

0.06
—

—

0.5

2

40
35

3.5

0.7

0.35

0.7
—

0.4

µA

mA

mA

µA

mA

V

V

I/O capacitance (Ta = 25°C, f = 1MHz)

Item Symbol Test condition Min. Typ. Max. Unit
Input capacitance
I/O capacitance

CIN
CI/O

VIN = 0V
VI/O = 0V

—
—

—
—

8

10

pF
pF

Note) This parameter is sampled and is not 100% tested.

AC Characteristics

• AC test conditions (VCC = 3.3V ± 0.3V, Ta = 0 to +70°C)

Item Conditions
Input pulse high level
Input pulse low level
Input rise time
Input fall time
Input and output reference level

Output load
conditions

∗2

CL includes scope and jig capacitances.

-70LL

-10LL

VIH = 2.0V
VIL = 0.8V

tr = 5ns
tf = 5ns

1.4V
CL∗2= 30pF, 1TTL

∗2

CL

= 100pF, 1TTL

C

L

TTL

– 3 –

• Read cycle (WE = “H”)

CXK5V8257BTM/BYM/BM

Item Symbol Unit

Read cycle time
Address access time
Chip enable access time (CE)
Output enable to output valid
Output hold from address change
Chip enable to output in low Z (CE)
Output enable to output in low Z (OE)
Chip disable to output in high Z (CE)
Output disable to output in high Z (OE)

∗1

tHZ and tOHZ are defined as the time required for outputs to turn to high impedance state and are not

referred to as output voltage levels.

• Write cycle

Item Symbol Unit

tRC
tAA
tCO
tOE
tOH
tLZ
tOLZ
tHZ
tOHZ

∗1

∗1

-70LL -10LL

Min. Max. Min. Max.

70
—
—
—
20
10

5
—
—

Min. Max. Min. Max.

—
70
70
35
—
—
—
30
30

-70LL -10LL

100

—
—
—
20
10
10
—
—

—
100
100

50

—

—

—

35

35

ns
ns
ns
ns
ns
ns
ns
ns
ns

Write cycle time
Address valid to end of write
Chip enable to end of write
Data to write time overlap
Data hold from write time
Write pulse width
Address setup time
Write recovery time (WE)
Write recovery time (CE)
Output active from end of write
Write to output in high Z

∗2

tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as

output voltage level.

tWC
tAW
tCW
tDW
tDH
tWP
tAS
tWR
tWR1
tOW
tWHZ

∗2

70
60
60
30

0

55

0
0

0
10
—

—
—
—
—
—
—
—
—
—
—

30

100

80
80
35

0

60

0
0
0

10

—

—
—
—
—
—
—
—
—
—
—

35

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

– 4 –

Timing Waveform

• Read cycle (1): CE = OE = VIL, WE = VIH

Address

tOH

Data out

Previous data valid Data valid

• Read cycle (2): WE = VIH

Address

CE

CXK5V8257BTM/BYM/BM

tRC

tAA

tRC

tAA

tCO

tHZ

tLZ

OE

Data out

• Write cycle (1): WE control

Address

OE

CE

WE

tOLZ

High impedance

tWC

tAW

tCW

tAS tWP

tOHZtOE

Data valid

tWR

(∗1)

Data in

Data out

tDW

Data valid

tWHZ

High impedance

(∗2)(∗2)

tDH

tOW

– 5 –

• Write cycle (2): CE control

Address

OE

CXK5V8257BTM/BYM/BM

tWC

tAW

tDH

tWR1

(∗3)

tAS tCW

CE

tWP

WE

tDW

Data in

Data out

∗1

Write is executed when both CE and WE are at low simultaneously.

∗2

Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition.

∗3

tWR1 is measured at the period from the rising edge of CE to the end of write cycle.

Data valid

High impedance

– 6 –

Data retention waveform

• Low supply voltage data retention waveform

CXK5V8257BTM/BYM/BM

t

R

VCC

3.0V

2.0V
VDR

CE
GND

CDRS

t

Data retention mode

CE ≥ VCC – 0.2V

Data Retention Characteristics (Ta = 0 to +70°C)

Item Symbol Test condiitions Min. Typ. Max. Unit

Data retention voltage

Data retention
current

VDR

ICCDR1

ICCDR2

CE ≥ VCC – 0.2V

VCC = 3.0V,
CE ≥ 2.8V

VCC = 2.0 to 3.6V,
CE ≥ VCC – 0.2V

0 to +70°C
0 to +40°C

+25°C

2.0
—
—
—

—

—
—
—

0.1

0.12

∗1

3.6
3

0.6

0.3

3.5

V

µA

µA

Data retention setup
time

Recovery time

∗1

VCC = 3.3V, Ta = 25°C

tCDRS
tR

Chip disable to data retention mode

0
5

—
—

—
—

ns

ms

– 7 –

Package Outline Unit: mm

CXK5V8257BTM

CXK5V8257BTM/BYM/BM

28PIN TSOP (Plastic)

∗8.0 ± 0.1

821

13.4 ± 0.3

∗11.8 ± 0.1

22

+ 0.1

0.2 – 0.05

NOTE: Dimension “∗” does not include mold protrusion.

SONY CODE
EIAJ CODE
JEDEC CODE

7128

0.55 ± 0.1

TSOP-28P-L01
TSOP028-P-0000-A

1.2 MAX

A

+ 0.07

0.127 – 0.02

+ 0.1

0.05 – 0.05

0.5 ± 0.1

0° to 10°

DETAIL A

PACKAGE STRUCTURE

PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT

EPOXY RESIN
SOLDER PLATING
COPPER / 42 ALLOY

0.2g

0.1

CXK5V8257BYM

28PIN TSOP (Plastic)

∗8.0 ± 0.1

218

13.4 ± 0.3

∗11.8 ± 0.1

7

+ 0.1

0.2 – 0.05

NOTE: Dimension “∗” does not include mold protrusion.

SONY CODE
EIAJ CODE
JEDEC CODE

22281

0.55 ± 0.1

TSOP-28P-L01R
TSOP028-P-0000-B

1.2 MAX

A

+ 0.07

0.127 – 0.02

+ 0.1

0.05 – 0.05

0.5 ± 0.1

0° to 10°

DETAIL A

PACKAGE STRUCTURE

PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT

EPOXY RESIN
SOLDER PLATING
COPPER / 42 ALLOY

0.2g

0.1

– 8 –

CXK5V8257BM

CXK5V8257BTM/BYM/BM

28PIN SOP (PLASTIC)

28

1

SONY CODE
EIAJ CODE
JEDEC CODE

+ 0.4

18.0 – 0.1

0.4 ± 0.1

SOP-28P-L05
∗SOP028-P-0450

0.24

15

+ 0.3

8.4 – 0.1

11.8 ± 0.4

14

1.27

M

PACKAGE STRUCTURE

PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL

PACKAGE WEIGHT

0° to 10°

EPOXY RESIN

SOLDER PLATING

42 ALLOY

0.7g

+ 0.4

2.3 – 0.15

+ 0.2

0.1 – 0.05

1.0 ± 0.2

0.15 – 0.05

0.15

+ 0.1

– 9 –