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CXK582000TM/YM/M-85LL/10LL
For the availability of this product, please contact the sales office.
262144-word × 8-bit High Speed CMOS Static RAM
Description
The CXK582000TM/YM/M is a high speed CMOS
static RAM organized as 262144-words by 8 bits.
A polysilicon TFT cell technology realized
extremely low stand-by current and higher data
retention stability.
Special feature are low power consumption and
high speed and board package line-up.
The CXK582000TM/YM/M is a suitable RAM for
portable equipment with battery back up.
Features
• Fast access time (Access time)
-85LL 85ns (Max.)
-10LL 100ns (Max.)
• Low standby current 40µA (Max.)
• Low data retention current 24µA (Max.)
• Single +5V supply: 4.5V to 5.5V.
• Low voltage date retention : 2.0V (Min.)
• Broad package line-up
CXK582000TM/YM 8mm × 20mm 32 pin
TSOP Package
CXK582000M 525mil 32 pin
SOP Package
Function
262144 word x 8 bit static RAM
CXK582000TM
32 pin TSOP (PIastic)
32 pin SOP (PIastic)
Block Diagram
A10
A11
A9
A8
A13
A15
A17
A16
A14
A12
A7
Buffer
Preliminary
32 pin TSOP (PIastic)
CXK582000M
Row
Decoder
CXK582000YM
Memory
Matrix
2048 × 1024
VCC
GND
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
A6
A5
A4
A3
A2
A1
A0
OE
WE
CE1
CE2
Buffer
Buffer
I /O Gate
Column
Decoder
I /O Buffer
I/O1
I/O8
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E94234-ST
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CXK582000TM/YM/M
Pin Configuration (Top View)
1
A11
2
A9
3
A8
A13
4
WE
5
CE2
6
A15
Vcc
A17
A16
A14
A12
A12
A14
A16
A17
Vcc
A15
CE2
WE
A13
A11
7
8
9
10
11
12
13
A7
14
A6
A5
15
16
A4
16
A4
15
A5
14
A6
13
A7
12
11
10
9
8
7
6
5
4
A8
3
A9
2
1
CXK582000TM
(Standard Pinout)
CXK582000YM
(Mirror image Pinout)
Pin Description
32
OE
31
A10
30
CE1
29
I/O8
28
I/O7
27
I/O6
26
I/O5
I/O4
25
GND
24
I/O3
23
I/O2
22
I/O1
21
A0
20
19
A1
18
A2
A3
17
17
A3
18
A2
19
A1
20
A0
21
I/O1
22
I/O2
23
I/O3
24
GND
25
I/O4
26
I/O5
I/O6
27
I/O7
28
I/O8
29
CE1
30
A10
31
OE
32
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CXK582000M
32
Vcc
31
A15
30
CE2
29
WE
28
A13
27
A8
26
A9
25
A11
24
OE
23
A10
22
CE1
21
I/O8
20
I/O7
19
I/O6
18
I/O5
17
I/O4
Symbol Description
A0 to A17
I/O1 to I/O8
CE1, CE2
WE
OE
VCC
GND
Address input
Data input output
Chip enable 1, 2 input
Write enable input
Output enable input
Power supply
Ground
Absolute Maximum Ratings (Ta = 25°C, GND = 0V)
Item Symbol Rating Unit
Supply voltage
Input voltage
Input and output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Soldering temperature · time
VCC
VIN
VI/O
PD
Topr
Tstg
Tsolder
–0.5 to +7.0
–0.5∗ to VCC + 0.5
–0.5∗ to VCC + 0.5
0.7
0 to +70
–55 to +150
235 · 10
V
V
V
W
°C
°C
°C · s
∗ VIN, VI/O = –3.0V Min. for pulse width less than 50ns.
Truth Table
CE1 CE2 OE WE
H
×
×
×
×
L
×
×
L
H
H
H
Mode I/O pin VCC Current
Not selected
Not selected
Output disable
High Z
High Z
High Z
ISB1, ISB2
ISB1, ISB2
ICC1, ICC2, ICC3
L
H
L
H
×: “H” or “L”
L
H
Read
×
L
Write
Data out
Data in
ICC1, ICC2, ICC3
ICC1, ICC2, ICC3
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DC Recommended Operating Conditions (Ta = 0 to +70°C, GND = 0V)
Item Symbol Min. Typ. Max. Unit
CXK582000TM/YM/M
ILI
ILO
ICC1
ICC2
ICC3
VCC
VIH
VIL
4.5
2.2
–0.3∗
VIN = GND to VCC
CE1 = VIH or CE2 = VIL or
OE = VIH or WE = VIL
VI/O = GND to VCC
CE1 = VIL, CE2 = VIH
VIN = VIH or VIL
IOUT = 0mA
Min. cycle
duty = 100%
IOUT = 0mA
Cycle time 1µs
duty = 100%
IOUT = 0mA
CE1 ≤ 0.2V
CE2 ≥ Vcc – 0.2V
VIL ≤ 0.2V
VIH ≥ Vcc – 0.2V
Supply voltage
Input high voltage
Input low voltage
∗ VIL = –3.0V Min. for pulse width less than 50ns.
Electrical Characteristics
• DC Characteristics
Item Symbol Min.
Input leakage current
Output leakage current
Operating power supply
current
Average operating current
5.0
—
—
5.5
VCC + 0.3
0.8
(VCC = 5V ± 10%, GND = 0V, Ta = 0 to +70°C)
-85LLX
-10LLX
V
V
V
Typ.∗
–1
–1
—
—
—
—12
—
—
7
45
40
Max. UnitTest conditions
+1
+1
15
80
70
24
µA
µA
mA
mA
mA
Standby current
Output high voltage
Output low voltage
∗ VCC = 5V, Ta = 25°C
ISB1
ISB2
VOH
VOL
CE2 ≤ 0.2V
CE1 ≥ Vcc – 0.2V
or
{
CE2 ≥ Vcc – 0.2V
CE1 = VIH or CE2 = VIL
IOH = –1.0mA
IOL = 1.0mA
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0 to +70°C
0 to +40°C
+25°C
—
—
—
—
2.4
—
—
—
1.4
0.6
—
—
40
8
4
3
—
0.4
µA
mA
V
V
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I/O capacitance (Ta = 25°C, f = 1MHz)
Item Symbol Test conditons Min. Typ. Max. Unit
CXK582000TM/YM/M
Input capacitance
I/O capacitance
CIN
CI/O
VIN = 0V
VI/O = 0V
—
—
Note) This parameter is sampled and is not 100% tested.
AC Characteristics
• AC test conditions (VCC = 5V ± 10%, Ta = 0 to +70°C)
Item Conditions
Input pulse high level
Input pulse low level
Input rise time
Input fall time
Input and output reference level
Output load conditions
VIH = 2.2V
VIL = 0.8V
tr = 5ns
tf = 5ns
1.5V
CL∗ = 100pF, 1TTL
∗ CL includes scope and jig capacitances.
—
—
7
8
pF
pF
TTL
L
C
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CXK582000TM/YM/M
• Read cycle (WE = “H”)
Item Symbol
Read cycle time
Address access time
Chip enable access time (CE1)
Chip enable access time (CE2)
Output enable to output valid
Output hold from address change
Chip enable to output in low Z (CE1, CE2)
Output enable to output in low Z (OE)
Chip disable to output in high Z (CE1, CE2)
Output disable to output in high Z (OE)
∗ tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not
referred to as output voltage levels.
• Write cycle
tRC
tAA
tCO1
tCO2
tOE
tOH
tLZ1, tLZ2
tOLZ
tHZ1, tHZ2∗
tOHZ∗
-85LL -10LL
Min. Max. Min. Max.
85
—
—
—
—
15
10
5
—
—
—
85
85
85
45
—
—
—
25
25
(Ta = 0 to +70°C)
100
—
—
—
—
15
10
5
—
—
—
100
100
100
50
—
—
—
35
35
(Ta = 0 to +70°C)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Item Symbol
Write cycle time
Address valid to end of write
Chip enable to end of write
Data to write time overlap
Data hold from write time
Write pulse width
Address setup time
Write recovery time (WE)
Write recovery time (CE1, CE2)
Output active from end of write
Write to output in high Z
∗ tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage level.
tWC
tAW
tCW
tDW
tDH
tWP
tAS
tWR
tWR1
tOW
tWHZ∗
-85LL -10LL
Min. Max. Min. Max.
85
65
65
35
0
60
0
5
5
10
—
—
—
—
—
—
—
—
—
—
—
25
100
70
70
45
0
70
0
5
5
10
—
—
—
—
—
—
—
—
—
—
—
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Timing Waveform
• Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH
Address
tAA
tOH
CXK582000TM/YM/M
tRC
Data out
• Read cycle (2) : WE = VIH
Address
CE1
CE2
OE
Data out
Previous data valid Data valid
tRC
tAA
tCO1
tLZ1
tCO2
tLZ2
tOLZ
High impedance
tOHZtOE
Data valid
tHZ1
tHZ
tHZ2
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• Write cycle (1) : WE control
Address
OE
CE1
CE2
WE
tAS
tWC
tAW
tCW
tCW
tWP
CXK582000TM/YM/M
tWR
(∗1)
Data in
Data out
• Write cycle (2) : CE1 control
Address
OE
CE1
tWHZ
(∗2)
tWC
tAW
tAS tCW
tDW
Data valid
High impedance
tCW
tDH
tOW
tWR1
(∗2)
(∗3)
CE2
WE
Data in
Data out
– 7 –
tWP
tDW
Data valid
High impedance
tDH
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• Write cycle (3) : CE2 control
Address
OE
CE1
CE2
WE
tAS
tWC
tAW
tWP
tCW
tCW
tWR1
CXK582000TM/YM/M
(∗3)
tDH
Data in
Data out
tDW
Data valid
High impedance
∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously.
∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition.
∗3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until
the end of the write cycle.
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Data retention waveform
• Low supply voltage data retention waveform (1) (CE1 control)
CDRS
t
VCC
4.5V
2.2V
VDR
CE1
GND
Data retention mode
CE1 ≥ V
CC – 0.2V
• Low supply voltage data retention waveform (2) (CE2 control)
Data retention mode
CC
V
4.5V
CE2
DR
V
CXK582000TM/YM/M
tR
tRtCDRS
0.4V
GND
CE2 ≤ 0.2V
Data Retention Characteristics (Ta = 0 to +70°C)
Item Symbol Test conditions Min. Typ. Max. Unit
Data retention voltage
VDR
ICCDR1
∗
VCC = 3.0V∗
2.0
0 to +70°C
1
0 to +40°C
—
—
—
—
—
5.5
24
4.8
V
µA
Data retention current
Data retention setup time
Recovery time
ICCDR2
tCDRS
tR
+25°C
VCC = 2.0 to 5.5V∗
Chip disable to data retention mode
—
—
0
5
0.8
1.4
—
—
2.4
40
—
—
µA
ns
ms
∗ CE1 ≥ Vcc – 0.2V, CE2 ≥ Vcc – 0.2V (CE1 control) or CE2 ≤ 0.2V (CE2 control)
– 9 –
Page 10
Package Outline Unit: mm
CXK582000TM
CXK582000TM/YM/M
32PIN TSOP (I) (PLASTIC)
8.0 ± 0.2
32
116
+ 0.08
0.2 – 0.03
NOTE : ∗NOT INCLUDE MOLD FINS.
SONY CODE
EIAJ CODE
JEDEC CODE
M
0.08
TSOP-32P-L01
TSOP032-P-0820-A
+ 0.2
17
20.0 ± 0.2
∗18.4 ± 0.2
0.5
1.07 – 0.1
0.1
A
+ 0.05
0.127 – 0.02
0.1 ± 0.1
0.5 ± 0.1
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY
CXK582000YM
32PIN TSOP (PLASTIC)
8.0 ± 0.2
17
16
+ 0.08
0.2 – 0.03
NOTE > Dimension “∗” does not include mold protrusion.
SONY CODE
EIAJ CODE
JEDEC CODE
0.08
TSOP-32P-L01R
TSOP032-P-0820-B
32
∗18.4 ± 0.2
1
M
0.5
PACKAGE STRUCTURE
20.0 ± 0.2
A
0.1 ± 0.1
DETAIL A
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
+ 0.2
1.07 – 0.1
0.1
0.127 – 0.02
0.5 ± 0.1
0° to 10°
EPOXY RESIN
SOLDER PLATING
42 ALLOY
0.3g
+ 0.05
– 10 –
Page 11
CXK582000M
CXK582000TM/YM/M
32PIN SOP (PLASTIC) 525mil
32
1
SONY CODE
EIAJ CODE
JEDEC CODE
0.4 ± 0.1
+ 0.4
20.5 – 0.1
SOP-32P-L02
∗SOP032-P-0525-A
1.27
17
+ 0.3
11.2 – 0.1
14.0 ± 0.4
16
M
0.12
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
11.9
A
+ 0.1
0.15 – 0.05
0.2 ± 0.1
0° to 10°
DETAIL A
EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY
+ 0.15
2.9 – 0.25
0.1
0.8 ± 0.2
– 11 –
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