Page 1
CXD3504R
Selective Delay Line for LCD
Description
The CXD3504R is a selective delay line IC for
performing signal processing during dot and line
inverted drive of liquid crystal panels for Sony
projectors.
This chip has three built-in 10-bit × 1200-word 1H
delay lines, and data path with or without a 1H delay
can be selected by the control pins.
Features
• Supports dot and line inverted drive of liquid crystal
panels for Sony projectors
• Three built-in 10-bit × 1200-word 1H delay lines
• Data path with or without a 1H delay can be selected
by the control pins.
Applications
LCD projectors, etc.
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Vss = 0V)
• Supply voltage VDD –0.3 to +4.6 V
• Input voltage VI –0.3 to VDD + 0.3 V
• Output voltage VO –0.3 to VDD + 0.3 V
• Operating temperature Topr –30 to +75 °C
• Storage temperature Tstg –55 to +125 °C
• Allowable power dissipation
PDmax 850mW (Ta ≤ 75°C)
Recommended Operating Conditions
• Supply voltage VDD 3.0 to 3.6 V
• Operating temperature Topr –30 to +75 °C
• Input voltage VIN 0 to VDD V
– 1 –
E99815-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
176 pin LQFP (Plastic)
Page 2
– 2 –
CXD3504R
Block Diagram
117118119120121122123124125126127128129130131132
VDD
R2IN0
R2IN1
R2IN2
R2IN3
R2IN4
R2IN5
R2IN6
R2IN7
R2IN8
R2IN9
R1IN0
R1IN1
R1IN2
R1IN3
R1IN4
111112113114115116
R1IN5
R1IN6
R1IN7
R1IN8
R1IN9
V
SS
110
VDD
109
R1OUT9
108
R1OUT8
107
R1OUT7
106
R1OUT6
105
R1OUT5
104
VSS
103
VDD
102
R1OUT4
101
R1OUT3
100
R1OUT2
R1OUT1
R1OUT0
VSSVDD
TEST3
R2OUT9
R2OUT8
R2OUT7
R2OUT6
R2OUT5
V
SS
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
85
86
87
88
99 98 97 96 95 94 93 92 91 90 89
79
80
81
82
83
84
V
SS
B1OUT5
B1OUT6
B1OUT7
B1OUT8
B1OUT9
TEST1
V
DD
VSS
G2OUT0
G2OUT1
G2OUT2
G2OUT3
G2OUT4
V
DD
VSS
G2OUT5
G2OUT6
G2OUT7
G2OUT8
G2OUT9
V
DD
VSS
G1OUT0
G1OUT1
G1OUT2
G1OUT3
G1OUT4
V
DD
VSS
G1OUT5
G1OUT6
G1OUT7
G1OUT8
G1OUT9
TEST2
V
DD
VSS
R2OUT0
R2OUT1
R2OUT2
R2OUT3
R2OUT4
V
DD
169
170
171
172
173
174
175
162
161
160
159
158
157
163
164
165
166
167
168
176
VDD
B2IN0
B2IN1
B2IN2
B2IN3
B2IN5
B2IN4
B2IN6
B2IN7
B2IN8
B2IN9
B1IN0
B1IN1
B1IN2
B1IN3
B1IN4
B1IN5
B1IN6
B1IN7
B1IN8
149
150
151
152
153
154
155
142
141
140
139
138
137
143
144
145
146
147
148
156
B1IN9
V
SS
VDD
G2IN0
G2IN1
G2IN3
G2IN2
G2IN4
G2IN5
G2IN6
G2IN7
G2IN8
G2IN9
G1IN0
G1IN1
G1IN2
G1IN3
G1IN4
G1IN5
G1IN6
136
135
134
G1IN7
G1IN8
G1IN9
133
VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VSS
PECLCK
NC
CMOSCK
V
SS
CLKSEL
SELRA
SELGA
SELBA
SELB
XCLR
HD
HDSEL
HDEDGE
NC
REDGE
GEDGE
BEDGE
POLSLA
NC
NC
V
DD
VSS
B2OUT0
B2OUT1
B2OUT2
B2OUT3
B2OUT4
V
DD
VSS
B2OUT5
B2OUT6
41 42 43 44
B1OUT3
B1OUT4
TEST0
V
DD
B2OUT7
B2OUT8
B2OUT9
V
DD
VSS
B1OUT0
B1OUT1
B1OUT2
R CH FIFO
G CH FIFO
TIMING
GENERATOR
INPUT
LATCH
&
SELECT
OUTPUT
SELECT
&
LATCH
CLK SEL
B CH FIFO
Page 3
– 3 –
CXD3504R
Pin Configuration
117118119120121122123124125126127128129130131132
VDD
R2IN0
R2IN1
R2IN2
R2IN3
R2IN4
R2IN5
R2IN6
R2IN7
R2IN8
R2IN9
R1IN0
R1IN1
R1IN2
R1IN3
R1IN4
111112113114115116
R1IN5
R1IN6
R1IN7
R1IN8
R1IN9
V
SS
110
VDD
109
R1OUT9
108
R1OUT8
107
R1OUT7
106
R1OUT6
105
R1OUT5
104
VSS
103
VDD
102
R1OUT4
101
R1OUT3
100
R1OUT2
R1OUT1
R1OUT0
VSSVDD
TEST3
R2OUT9
R2OUT8
R2OUT7
R2OUT6
R2OUT5
V
SS
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
85
86
87
88
99 98 97 96 95 94 93 92 91 90 89
79
80
81
82
83
84
V
SS
B1OUT5
B1OUT6
B1OUT7
B1OUT8
B1OUT9
TEST1
V
DD
VSS
G2OUT0
G2OUT1
G2OUT2
G2OUT3
G2OUT4
V
DD
VSS
G2OUT5
G2OUT6
G2OUT7
G2OUT8
G2OUT9
V
DD
VSS
G1OUT0
G1OUT1
G1OUT2
G1OUT3
G1OUT4
V
DD
VSS
G1OUT5
G1OUT6
G1OUT7
G1OUT8
G1OUT9
TEST2
V
DD
VSS
R2OUT0
R2OUT1
R2OUT2
R2OUT3
R2OUT4
V
DD
169
170
171
172
173
174
175
162
161
160
159
158
157
163
164
165
166
167
168
176
VDD
B2IN0
B2IN1
B2IN2
B2IN3
B2IN5
B2IN4
B2IN6
B2IN7
B2IN8
B2IN9
B1IN0
B1IN1
B1IN2
B1IN3
B1IN4
B1IN5
B1IN6
B1IN7
B1IN8
149
150
151
152
153
154
155
142
141
140
139
138
137
143
144
145
146
147
148
156
B1IN9
V
SS
VDD
G2IN0
G2IN1
G2IN3
G2IN2
G2IN4
G2IN5
G2IN6
G2IN7
G2IN8
G2IN9
G1IN0
G1IN1
G1IN2
G1IN3
G1IN4
G1IN5
G1IN6
136
135
134
G1IN7
G1IN8
G1IN9
133
VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VSS
PECLCK
NC
CMOSCK
V
SS
CLKSEL
SELRA
SELGA
SELBA
SELB
XCLR
HD
HDSEL
HDEDGE
NC
REDGE
GEDGE
BEDGE
POLSLA
NC
NC
V
DD
VSS
B2OUT0
B2OUT1
B2OUT2
B2OUT3
B2OUT4
V
DD
VSS
B2OUT5
B2OUT6
41 42 43 44
B1OUT3
B1OUT4
TEST0
V
DD
B2OUT7
B2OUT8
B2OUT9
V
DD
VSS
B1OUT0
B1OUT1
B1OUT2
Page 4
– 4 –
CXD3504R
Pin Description
∗1
Connect to GND or VDD when using CMOS clock.
∗2
Connect to GND or VDD when using small amplitude clock.
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Symbol
VSS
PECLCK
NC
CMOSCK
VSS
CLKSEL
SELRA
SELGA
SELBA
SELB
XCLR
HD
HDSEL
HDEDGE
NC
REDGE
GEDGE
BEDGE
POLSLA
NC
NC
VDD
VSS
B2OUT0
B2OUT1
B2OUT2
B2OUT3
B2OUT4
VDD
VSS
B2OUT5
B2OUT6
B2OUT7
I/O
P
I
I
P
I
I
I
I
I
I
I
I
I
I
I
I
I
P
P
O
O
O
O
O
P
P
O
O
O
Description
GND
Very little amp. clock input
∗1
CMOS clock input
∗2
GND
0: PECL, 1: CMOS
SELA (Data path selection A) for R
SELA (Data path selection A) for G
SELA (Data path selection A) for B
Data path selection B
0: Direct Reset
Horizontal sync signal input
HD selection (0: ↓, 1: ↑)
CK trigger selection of HD (0: ↓, 1: ↑)
Reserve
CK trigger selection of R (0: ↓, 1: ↑)
CK trigger selection of G (0: ↓, 1: ↑)
CK trigger selection of B (0: ↓, 1: ↑)
SELA polarity selection
Power supply
GND
B2 output
B2 output
B2 output
B2 output
B2 output
Power Supply
GND
B2 output
B2 output
B2 output
Input pin for
open status
L
L
L
L
L
H
L
L
L
L
L
L
Page 5
– 5 –
CXD3504R
Pin
No.
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Symbol
B2OUT8
B2OUT9
VDD
VSS
B1OUT0
B1OUT1
B1OUT2
B1OUT3
B1OUT4
TEST0
VDD
VSS
B1OUT5
B1OUT6
B1OUT7
B1OUT8
B1OUT9
TEST1
VDD
VSS
G2OUT0
G2OUT1
G2OUT2
G2OUT3
G2OUT4
VDD
VSS
G2OUT5
G2OUT6
G2OUT7
G2OUT8
G2OUT9
VDD
VSS
G1OUT0
I/O
O
O
P
P
O
O
O
O
O
I
P
P
O
O
O
O
O
I
P
P
O
O
O
O
O
P
P
O
O
O
O
O
P
P
O
Description
B2 output
B2 output
Power supply
GND
B1 output
B1 output
B1 output
B1 output
B1 output
1: Test mode
Power supply
GND
B1 output
B1 output
B1 output
B1 output
B1 output
1: Test mode
Power supply
GND
G2 output
G2 output
G2 output
G2 output
G2 output
Power supply
GND
G2 output
G2 output
G2 output
G2 output
G2 output
Power supply
GND
G1 output
Input pin for
open status
L
L
Page 6
– 6 –
CXD3504R
Pin
No.
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
Symbol
G1OUT1
G1OUT2
G1OUT3
G1OUT4
VDD
VSS
G1OUT5
G1OUT6
G1OUT7
G1OUT8
G1OUT9
TEST2
VDD
VSS
R2OUT0
R2OUT1
R2OUT2
R2OUT3
R2OUT4
VDD
VSS
R2OUT5
R2OUT6
R2OUT7
R2OUT8
R2OUT9
TEST3
VDD
VSS
R1OUT0
R1OUT1
R1OUT2
R1OUT3
R1OUT4
VDD
VSS
I/O
O
O
O
O
P
P
O
O
O
O
O
I
P
P
O
O
O
O
O
P
P
O
O
O
O
O
I
P
P
O
O
O
O
O
P
P
Description
G1 output
G1 output
G1 output
G1 output
Power supply
GND
G1 output
G1 output
G1 output
G1 output
G1 output
1: Test mode
Power supply
GND
R2 output
R2 output
R2 output
R2 output
R2 output
Power supply
GND
R2 output
R2 output
R2 output
R2 output
R2 output
1: Test mode
Power supply
GND
R1 output
R1 output
R1 output
R1 output
R1 output
Power supply
GND
Input pin for
open status
L
L
Page 7
– 7 –
CXD3504R
Pin
No.
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Symbol
R1OUT5
R1OUT6
R1OUT7
R1OUT8
R1OUT9
VDD
VSS
R1IN9
R1IN8
R1IN7
R1IN6
R1IN5
R1IN4
R1IN3
R1IN2
R1IN1
R1IN0
R2IN9
R2IN8
R2IN7
R2IN6
R2IN5
R2IN4
R2IN3
R2IN2
R2IN1
R2IN0
VDD
VSS
G1IN9
G1IN8
G1IN7
G1IN6
G1IN5
G1IN4
G1IN3
I/O
O
O
O
O
O
P
P
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
P
P
I
I
I
I
I
I
I
Description
R1 output
R1 output
R1 output
R1 output
R1 output
Power supply
GND
R1 input
R1 input
R1 input
R1 input
R1 input
R1 input
R1 input
R1 input
R1 input
R1 input
R2 input
R2 input
R2 input
R2 input
R2 input
R2 input
R2 input
R2 input
R2 input
R2 input
Power supply
GND
G1 input
G1 input
G1 input
G1 input
G1 input
G1 input
G1 input
Input pin for
open status
Page 8
– 8 –
CXD3504R
Pin
No.
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
Symbol
G1IN2
G1IN1
G1IN0
G2IN9
G2IN8
G2IN7
G2IN6
G2IN5
G2IN4
G2IN3
G2IN2
G2IN1
G2IN0
VDD
VSS
B1IN9
B1IN8
B1IN7
B1IN6
B1IN5
B1IN4
B1IN3
B1IN2
B1IN1
B1IN0
B2IN9
B2IN8
B2IN7
B2IN6
B2IN5
B2IN4
B2IN3
B2IN2
B2IN1
B2IN0
VDD
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
P
P
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
P
Description
G1 input
G1 input
G1 input
G2 input
G2 input
G2 input
G2 input
G2 input
G2 input
G2 input
G2 input
G2 input
G2 input
Power supply
GND
B1 input
B1 input
B1 input
B1 input
B1 input
B1 input
B1 input
B1 input
B1 input
B1 input
B2 input
B2 input
B2 input
B2 input
B2 input
B2 input
B2 input
B2 input
B2 input
B2 input
Power supply
Input pin for
open status
Page 9
– 9 –
CXD3504R
Electrical Characteristics (Input/Output level/VDD = 3.0 to 3.6V, Vss = 0V, Ta = –30 to +75°C)
∗1
Input pins except PECLCK
∗2
XCLR
∗3
CLKSEL, SELRA, SELGA, SELBA, SELB, HDSEL, HDEDGE, REDGE, GEDGE, BEDGE, POLSLA
∗4
All output pins
Min.
0.7VDD
—
VDD – 0.8
—
–10
80
90
Typ.
—
—
—
—
—
160
180
Max.
—
0.2VDD
—
0.4
10
320
360
Unit
V
V
V
V
µA
kΩ
kΩ
Applicable pins
∗1, ∗2, ∗3
∗4
∗1, ∗2, ∗3
∗2
∗3
Item
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
Input leak current
Pull-up resistor
Pull-down resistor
Symbol
VIH
VIL
VOH
VOL
IIL
RUP
RDN
Conditions
CMOS input
IOH = –12mA
IOL = 12mA
VI = VSS, VDD
AC Characteristics
PECLCK
(CMOSCK)
HD
t1
t5
d in
99b
d in
100b
d in1cd in
2c
Input Data
(R, G, B )
Through
Output
Delay
Output
d in3cd in4cd in5cd in
6c
d in8cd in9cd in
10c
d in
11c
d in
12c
d in
13c
d in
95b
d in
96b
d in
97b
d in
98b
d in
99b
d in
100b
d in4cd in5cd in6cd in7cd in8cd in
9c
d in
95a
d in
96a
d in
97a
d in
98a
d in
99a
d in
100a
d in4bd in5bd in6bd in7bd in8bd in
9b
No Care
No Care
t3
t4
t2
d in
7c
Note: The above timing values are for PECCLK (CMOSCK) = 80MHz and an output pin capacitance of 20pF.
Item
Input frequency
HD set-up time to PECLCK bar
HD hold time from PECLCK bar
R, G, B input data set-up time to PECLCK bar
R, G, B input data hold time from PECLCK bar
R, G, B output data delay from PECLCK
HD set-up time to CMOSCK bar
HD hold time from CMOSCK bar
R, G, B input data set-up time to CMOSCK bar
R, G, B input data hold time from CMOSCK bar
R, G, B output data delay from CMOSCK
Symbol
f
t1
t2
t3
t4
t5
t1
t2
t3
t4
t5
Min.
—
1.5
4.5
1
6.5
4
2
3
1.5
4.5
3
Max.
80
—
—
—
—
13
—
—
—
—
12
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 10
– 10 –
CXD3504R
Description of Operation
1) The following describes only R, but the operation for G and B is the same.
SELRA:SELB = 0:0 R2IN → through → R1OUT
R1IN → delay → R2OUT
SELRA:SELB = 0:1 R2IN → delay → R1OUT
R1IN → through → R2OUT
SELRA:SELB = 1:0 R1IN → through → R1OUT
R2IN → delay → R2OUT
SELRA:SELB = 1:1 R1IN → delay → R1OUT
R2IN → through → R2OUT
However, POLSLA = 0
2) Be sure to set XCLR to "0" for a clock or more while HD is "1". (when HDSEL = 0) Also, input the HD signal
with a "0" period length of 6 clocks or more.
Very Little Signal Amplifier (VDD = 3.0 to 3.6V, Vss = 0V, Ta = –30 to +75°C)
Item
High level input voltage
Low level input voltage
Input frequency
Input amplitude
∗1
Symbol
VIH
VIL
f
Vpp
Min.
0.4
0
—
0.4
Typ.
—
—
—
—
Max.
3.6
3.2
80
—
Unit
V
V
MHz
V
Applicable pins: PECLCK (Pin 2)
∗1
Input the signal through a capacitor. Also, this amplitude is the value between the through capacitor and the
input pin.
2
PECLCK
Page 11
– 11 –
CXD3504R
Application Circuit
VDD
R2IN0
R2IN1
R2IN2
R2IN3
R2IN4
R2IN5
R2IN6
R2IN7
R2IN8
R2IN9
R1IN0
R1IN1
R1IN2
R1IN3
R1IN4
R1IN5
R1IN6
R1IN7
R1IN8
R1IN9
V
SS
VDD
R1OUT9
R1OUT8
R1OUT7
R1OUT6
R1OUT5
V
SS
VDD
R1OUT4
R1OUT3
R1OUT2
R1OUT1
R1OUT0
V
SS
VDD
TEST3
R2OUT9
R2OUT8
R2OUT7
R2OUT6
R2OUT5
V
SS
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
85
86
87
88
79
80
81
82
83
84
V
SS
B1OUT5
B1OUT6
B1OUT7
B1OUT8
B1OUT9
TEST1
V
DD
VSS
G2OUT0
G2OUT1
G2OUT2
G2OUT3
G2OUT4
V
DD
VSS
G2OUT5
G2OUT6
G2OUT7
G2OUT8
G2OUT9
V
DD
VSS
G1OUT0
G1OUT1
G1OUT2
G1OUT3
G1OUT4
V
DD
VSS
G1OUT5
G1OUT6
G1OUT7
G1OUT8
G1OUT9
TEST2
V
DD
VSS
R2OUT0
R2OUT1
R2OUT2
R2OUT3
R2OUT4
V
DD
VDD
B2IN0
B2IN1
B2IN2
B2IN3
B2IN5
B2IN4
B2IN6
B2IN7
B2IN8
B2IN9
B1IN0
B1IN1
B1IN2
B1IN3
B1IN4
B1IN5
B1IN6
B1IN7
B1IN8
B1IN9
V
SS
VDD
G2IN0
G2IN1
G2IN3
G2IN2
G2IN4
G2IN5
G2IN6
G2IN7
G2IN8
G2IN9
G1IN0
G1IN1
G1IN2
G1IN3
G1IN4
G1IN5
G1IN6
G1IN7
G1IN8
G1IN9
V
SS
VSS
PECLCK
NC
CMOSCK
V
SS
CLKSEL
SELRA
SELGA
SELBA
SELB
XCLRHDHDSEL
HDEDGE
NC
REDGE
GEDGE
BEDGE
POLSLA
NCNCV
DD
VSS
B2OUT0
B2OUT1
B2OUT2
B2OUT3
B2OUT4
V
DD
VSS
B2OUT5
B2OUT6
B1OUT3
B1OUT4
TEST0
V
DD
B2OUT7
B2OUT8
B2OUT9
V
DD
VSS
B1OUT0
B1OUT1
B1OUT2
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ0.1µ0.1µ0.1µ
From CXD2467Q
To CXA3197R
0.1µ
3.3V
10µ/16V
0.1µ
169
170
171
172
173
174
175
162
161
160
159
158
157
163
164
165
166
167
168
176
149
150
151
152
153
154
155
142
141
140
139
138
137
143
144
145
146
147
148
156
136
135
134
133
117118119120121122123124125126127128129130131132 111112113114115116 110 109 108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
0.1µ
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Page 12
– 12 –
CXD3504R
Package Outline Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
42 ALLOY
PACKAGE STRUCTURE
1 44
45
88
89132
133
176
0.5
0.2 – 0.04
+ 0.05
0.1 M
24.0 ± 0.2
26.0 ± 0.2
(1.4)
1.6 MAX
0.125 – 0.02
+ 0.07
A
0.5 ± 0.2
0.1 ± 0.1
0 ° to 10 °
0.1
LQFP-176P-L061
P-LQFP176-24X24-0.5
1.8 g
176PIN LQFP(PLASTIC)
DETAIL A
Sony Corporation
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