Page 1
CXD3408GA
Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
Description
The CXD3408GA is a timing generator and CCD
signal processor IC for the ICX406 CCD image sensor.
Features
• Timing generator functions
• Horizontal drive frequency 18MHz
(base oscillation frequency 36MHz)
• Supports frame readout/draft (quadruple speed)
/AF (auto-focus)
• High-speed/low-speed shutter function
• Horizontal and vertical drivers for CCD image
sensor
• CCD signal processor functions
• Correlated double sampling
• Programmable gain amplifier (PGA) allows gain
adjustment over a wide range (–6 to +42dB)
• 10-bit A/D converter
• Chip Scale Package (CSP):
CSP allows vast reduction in the CCD camera
block footprint
Applications
Digital still cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX406 (1/1.8", 3980K pixels)
Absolute Maximum Ratings
• Supply voltage
V
DDa, VDDb, VDDc, VDDdVSS – 0.3 to +7.0 V
VDDe, VDDf, VDDgVSS – 0.3 to +4.0 V
VL –10.0 to VSS V
VH VL – 0.3 to +26.0 V
• Input voltage (analog)
V
IN VSS – 0.3 to VDD + 0.3 V
• Input voltage (digital)
VI VSS – 0.3 to VDD + 0.3 V
• Output voltage
VO1 VSS – 0.3 to VDD + 0.3 V
VO2 VL – 0.3 to VSS + 0.3 V
V
O3 VL – 0.3 to VH + 0.3 V
• Operating temperature
Topr –20 to +75 °C
• Storage temperature
Tstg –55 to +125 °C
Recommended Operating Conditions
• Supply voltage
V
DDb 3.0 to 5.25 V
VDDa, VDDc, VDDd, VDDe, VDDf, VDDg
3.0 to 3.6 V
VM 0.0 V
VH 14.5 to 15.5 V
VL –7.0 to –8.0 V
• Operating temperature
Topr –20 to +75 °C
– 1 –
E01341A26
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
96 pin LFLGA (Plastic)
Page 2
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CXD3408GA
Block Diagram
C7
C3
A1NCA2
NC
D8C2D7C1B8
AVDD3B6AVDD4B9AVSS3A6AVSS4C5AVSS5A3SCK2A4SSI2B4SEN2A5TEST3C4TEST4B5TEST5E2DVDD1F2DVSS3F3DVDD2E3DVSS1
F1
B3
DVSS2
D0 (LSB)
Latch
Serial Port
Register
DAC
PGACDS ADC
Preblanking
Dummy Pixel
Auto Zero
Pulse Generator
V Driver
Serial Port
Register
SSG
Black Level
Auto Zero
B2
D1
B1
D2
C3
D3
C2
D4
C1
D5
D3
D6
D2
D7
D1
D8
E1
D9 (MSB)
G1
ADCLKI
G2
CLPOBI
G3
CLPDMI
L3
V
SS4
H1
ADCLK
H2
CLPOB
H3
CLPDM
J3
V
SS5
L1
OSCI
K1
OSCO
J1
CKI
J2
CKO
K2
MCKO
N8
SNCSL
L2
SSI1
M6
VL
L4
VM
M5
VH
M9
WEN
N9
ID/EXP
J7
V
SS3
J9
H2
J8
H1
H9
V
DD3
K9
V
SS2
K8
RG
K7
V
DD2
H8
V
DD4
H7
XRS
G7
PBLK
G8
XSHD
G9
XSHP
F7
PBLKI
F8
XSHDI
E7
AV
SS2
F9
XSHPI
D9
AV
SS1
E8
AV
DD2
E9
AV
DD1
C9
CCDIN
C6
C9
A7
C8
B7
C7
A8
AV
SS6
A9
AV
DD5
C8
C4
M1
SCK1
N1
SEN1
N3
VSS6
L7
VSS1
K3
VDD5
L9
VDD1
M2
VD
N2
HD
N7
SUB
N4
V4
N6
V3B
V3A
L6
V2
M4N5
V1B
M7
TEST2
M3
TEST1
M8
RST
L8
SSGSL
L5
V1A
Selector
Latch
Selector
1/2
Page 3
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CXD3408GA
Pin Configuration (Top View)
NC
D2
D5
D8
D9
DV
SS2
ADCLKI
ADCLK
CKI
OSCO
OSCI
SCK1
SEN1
A
B
C
D
E
F
G
H
J
K
L
M
N
NC
D1
D4
D7
DV
DD1
DVSS3
CLPOBI
CLPOB
CKO
MCKO
SSI1
VD
HD
SCK2
D0
D3
D6
DV
SS1
DVDD2
CLPDMI
CLPDM
VSS5
VDD5
VSS4
TEST1
V
SS6
SSI2
SEN2
TEST4
VM
V2
V4
TEST3
TEST5
AVSS5
V1A
VH
V1B
AV
SS4
AVDD4
C9
V3A
VL
V3B
C8
C7
C3
C1
AV
SS2
PBLKI
PBLK
XRS
VSS3
VDD2
VSS1
TEST2
SUB
AVSS6
AVDD3
C4
C2
AV
DD2
XSHDI
XSHD
V
DD4
H1
RG
SSGSL
RST
SNCSL
AV
DD5
AVSS3
CCDIN
AV
SS1
AV
DD1
XSHPI
XSHP
V
DD3
H2
V
SS2
VDD1
WEN
ID/EXP
123456789
Page 4
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CXD3408GA
Pin Description
No connected. (Open)
No connected. (Open)
CCD signal processor block serial interface clock input. (Schmitt trigger)
CCD signal processor block serial interface data input. (Schmitt trigger)
CCD signal processor block test input 3. Connect to DVSS.
CCD signal processor block analog GND.
Capacitor connection.
CCD signal processor block analog GND.
CCD signal processor block analog power supply.
ADC output.
ADC output.
ADC output (LSB).
CCD signal processor block serial interface enable input. (Schmitt trigger)
CCD signal processor block test input 5. Connect to DVDD.
CCD signal processor block analog power supply.
Capacitor connection.
CCD signal processor block analog power supply.
CCD signal processor block analog GND.
ADC output.
ADC output.
ADC output.
CCD signal processor block test input 4. Connect to DVSS.
CCD signal processor block analog GND.
Capacitor connection.
Capacitor connection.
Capacitor connection.
CCD output signal input.
ADC output.
ADC output.
ADC output.
Capacitor connection.
Capacitor connection.
CCD signal processor block analog GND.
ADC output (MSB).
CCD signal processor block digital power supply. (Power supply for ADC)
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D7
D8
D9
E1
E2
NC
NC
SCK2
SSI2
TEST3
AVSS4
C8
AVSS6
AVDD5
D2
D1
D0
SEN2
TEST5
AVDD4
C7
AVDD3
AVSS3
D5
D4
D3
TEST4
AVSS5
C9
C3
C4
CCDIN
D8
D7
D6
C1
C2
AVSS1
D9
DVDD1
—
—
I
I
I
—
—
—
—
O
O
O
I
I
—
—
—
—
O
O
O
I
—
—
—
—
I
O
O
O
—
—
—
O
—
Pin
No.
Symbol I/O Description
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CXD3408GA
CCD signal processor block digital GND.
CCD signal processor block analog GND.
CCD signal processor block analog power supply.
CCD signal processor block analog power supply.
CCD signal processor block digital GND.
CCD signal processor block digital GND.
CCD signal processor block digital power supply.
Pulse input for horizontal and vertical blanking period pulse cleaning. (Schmitt trigger)
CCD data level sample-and-hold pulse input. (Schmitt trigger)
CCD precharge level sample-and-hold pulse input. (Schmitt trigger)
Clock input for analog/digital conversion. (Schmitt trigger)
CCD optical black signal clamp pulse input. (Schmitt trigger)
CCD dummy signal clamp pulse input. (Schmitt trigger)
Pulse output for horizontal and vertical blanking period pulse cleaning.
CCD data level sample-and-hold pulse output.
CCD precharge level sample-and-hold pulse output.
Clock output for analog/digital conversion.
CCD optical black signal clamp pulse output.
CCD dummy signal clamp pulse output.
Sample-and-hold pulse output for analog/digital conversion phase alignment.
Timing generator block digital power supply. (Power supply for CDS block)
Timing generator block 3.0 to 5.0V power supply. (Power supply for H1/H2)
Inverter input.
Inverter output.
Timing generator block digital GND.
Timing generator block digital GND.
CCD horizontal register clock output.
CCD horizontal register clock output.
Inverter output for oscillation. When not used, leave open or connect a capacitor.
System clock output for signal processor IC.
Timing generator block digital power supply. (Power supply for common logic block)
Timing generator block digital power supply. (Power supply for RG)
CCD reset gate pulse output.
Timing generator block digital GND.
Inverter input for oscillation. When not used, fix to low.
E3
E7
E8
E9
F1
F2
F3
F7
F8
F9
G1
G2
G3
G7
G8
G9
H1
H2
H3
H7
H8
H9
J1
J2
J3
J7
J8
J9
K1
K2
K3
K7
K8
K9
L1
DVSS1
AVSS2
AVDD2
AVDD1
DVSS2
DVSS3
DVDD2
PBLKI
XSHDI
XSHPI
ADCLKI
CLPOBI
CLPDMI
PBLK
XSHD
XSHP
ADCLK
CLPOB
CLPDM
XRS
VDD4
VDD3
CKI
CKO
VSS5
VSS3
H1
H2
OSCO
MCKO
VDD5
VDD2
RG
VSS2
OSCI
—
—
—
—
—
—
—
I
I
I
I
I
I
O
O
O
O
O
O
O
—
—
I
O
—
—
O
O
O
O
—
—
O
—
I
Pin
No.
Symbol I/O Description
Page 6
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CXD3408GA
Timing generator block serial interface data input.
Schmitt trigger input/No protective diode on power supply side.
Timing generator block digital GND.
Timing generator block digital GND. (GND for vertical driver)
CCD vertical register clock output.
CCD vertical register clock output.
Timing generator block digital GND.
Internal SSG enable.
High: Internal SSG valid, Low: External sync valid (With pull-down resistor)
Timing generator block digital power supply. (Power supply for common logic block)
Timing generator block serial interface clock input.
Schmitt trigger input/No protective diode on power supply side.
Vertical sync signal input.
Timing generator block test input 1.
Normally fix to GND. (With pull-down resistor)
CCD vertical register clock output.
Timing generator block 15.0V power supply. (Power supply for vertical driver)
Timing generator block –7.5V power supply. (Power supply for vertical driver)
Timing generator block test input 2.
Normally fix to GND. (With pull-down resistor)
Timing generator block reset input.
High: Normal operation, Low: Reset control
Normally apply reset during power-on.
Schmitt trigger input/No protective diode on power supply side
Memory write timing pulse output.
Timing generator block serial interface strobe input.
Schmitt trigger input/No protective diode on power supply side
Horizontal sync signal input.
Timing generator block digital GND.
CCD vertical register clock output.
CCD vertical register clock output.
CCD vertical register clock output.
CCD electronic shutter pulse output.
Control input used to switch sync system.
High: CKI sync, Low: MCKO sync (With pull-down resistor)
Vertical direction line identification pulse output/exposure time identification pulse
output.
Switching possible using the serial interface data. (Default: ID)
L2
L3
L4
L5
L6
L7
L8
L9
M1
M2
M3
M4
M5
M6
M7
M8
M9
N1
N2
N3
N4
N5
N6
N7
N8
N9
SSI1
VSS4
VM
V1A
V3A
VSS1
SSGSL
VDD1
SCK1
VD
TEST1
V2
VH
VL
TEST2
RST
WEN
SEN1
HD
VSS6
V4
V1B
V3B
SUB
SNCSL
ID/EXP
I
—
—
O
O
—
I
—
I
I
I
O
—
—
I
I
O
I
I
—
O
O
O
O
I
O
Pin
No.
Symbol I/O Description
Page 7
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CXD3408GA
Electrical Characteristics
Timing Generator Block Electrical Characteristics
DC Characteristics (Within the recommended operating conditions)
VDD2
VDD3
VDD4
VDD1, VDD5
RST, SCK1,
SSI1, SEN1
TEST1, TEST2
SNCSL, SSGSL
VD, HD
H1, H2
RG
XSHP, XSHD,
XRS, PBLK,
CLPOB,
CLPDM,
ADCLK
CKO
MCKO
ID/EXP,
WEN
V1A, V1B,
V3A, V3B,
V2, V4
SUB
V
DDa
VDDb
VDDc
VDDd
VIH1
VIL1
VIH2
VIL2
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH5
VOL5
VOH6
VOL6
VOH7
VOL7
IOL
IOM1
IOM2
IOH
IOSL
IOSH
3.0
3.0
3.0
3.0
0.7VDDd
0.8VDDd
VDDd – 0.8
VDDb – 0.8
VDDa – 0.8
VDDd – 0.8
VDDd – 0.8
VDDd – 0.8
10.0
5.0
5.4
3.3
3.3
3.3
3.3
3.6
5.25
3.6
3.6
0.3VDDd
0.2VDDd
0.4
0.4
0.4
0.4
0.4
0.4
–5.0
–7.2
–4.0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
Feed current where I
OH = –1.2mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –22.0mA
Pull-in current where IOL = 14.4mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –6.9mA
Pull-in current where IOL = 4.8mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –2.4mA
Pull-in current where IOL = 4.8mA
V1A/B, V2, V3A/B, V4 = –8.25V
V1A/B, V2, V3A/B, V4 = –0.25V
V1A/B, V3A/B = 0.25V
V1A/B, V3A/B = 14.75V
SUB = –8.25V
SUB = 14.75V
Supply voltage 1
Supply voltage 2
Supply voltage 3
Supply voltage 4
Input
voltage 1
∗1
Input
voltage 2
∗2
Input/Output
voltage
Output
voltage 1
Output
voltage 2
Output
voltage 3
Output
voltage 4
Output
voltage 5
Output
voltage 6
Output
current 1
Output
current 2
Item Pins Symbol Conditions Min. Typ. Max. Unit
V
V
0.8V
DD
d
V
I+
VI –
0.2VDDd
∗1
This input pin is a schmitt trigger input and it does not have protective diode of the power supply side in the IC.
∗
2
These input pins are with pull-down resistor in the IC.
Note) This table indicates conditions at 3.3V drive.
V
OH4
Feed current where IOH = –3.3mA
V
DDc – 0.8
V
V
OL4
Pull-in current where IOL = 2.4mA
0.4
V
Page 8
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CXD3408GA
Inverter I/O Characteristics for Oscillation (Within the recommended operating conditions)
Item
Logical Vth
Input
voltage
Output
voltage
Feedback
resistor
Oscillation
frequency
Pins
OSCI
OSCI
OSCO
OSCI, OSCO
OSCI, OSCO
Symbol
LVth
V
IH
VIL
VOH
VOL
RFB
f
Conditions
Feed current where IOH = –3.6mA
Pull-in current where IOL = 2.4mA
VIN = VDDd or VSS
Min.
0.7V
DDd
V
DDd – 0.8
500k
20
Typ.
V
DDd/2
2M
Max.
0.3VDDd
0.4
5M
50
Unit
V
V
V
V
V
Ω
MHz
Item
Logical Vth
Input
voltage
Input
amplitude
Pins
CKI
Symbol
LVth
V
IH
V
IL
VIN
Conditions
fmax 50MHz sine wave
Min.
0.7V
DDd
0.3
Typ.
VDDd/2
Max.
0.3VDDd
Unit
V
V
V
Vp-p
Item
Rise time
Fall time
Output noise voltage
Symbol
TTLM
TTMH
TTLH
TTML
TTHM
TTHL
VCLH
VCLL
VCMH
VCML
Conditions
VL to VM
VM to VH
VL to VH
VM to VL
VH to VM
VH to VL
Min.
200
200
30
200
200
30
Typ.
350
350
60
350
350
60
Max.
500
500
90
500
500
90
1.0
1.0
1.0
1.0
Unit
ns
ns
ns
ns
ns
ns
V
V
V
V
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude
is the input amplitude characteristics in the case of input through a capacitor.
Switching Characteristics (VH = 15.0V, VM = GND, VL = –7.5V)
Notes)
1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between
each power supply pin (VH, VL) and GND.
3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.
Page 9
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CXD3408GA
Switching Waveforms
V1A (V1B, V3A, V3B)
V2 (V4)
SUB
TTMH TTHM
VH
VM
VL
VM
VL
VH
VL
90%
10%
90%
10%
TTLM
TTLM
90%
10%
90%
10%
TTLH TTHL
90%90%
10% 10%
TTML
90%
10%
TTML
90%
10%
Waveform Noise
VCMH
VCML
VM
VL
VCLH
VCLL
Page 10
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CXD3408GA
Measurement Circuit
N1
N2
L4
L5
L6N7L7
N8
N9
M1M2M3
N4N5N6
M4
N3 L2 K2 K9 K8 K7 K1 L1 K3 J9 J8 J7 J3 J2 J1 H9 H8 H7 H3 H2 L3 G9 G8 G7
A2 A1 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B9 B8 C1 C2 C3 C4 C5 C6
M5
M6
E1
L8
L9
M7M8M9
E8
D8
D7
D3D2D1C9C8
C7
F3
F2
G1
E9D9E7
G3
G2
H1
F9F8F7
F1
E3
E2
VD
CXD3408GA
V2VHVLD9SSGSL
V
DD1
SCK1VDTEST1V4V1B
V3B
TEST2
RST
WEN
SEN1HDVM
V1A
V3A
SUB
V
SS1
SNCSL
ID/EXP
CLPDMI
CLPOBI
ADCLK
XSHPI
XSHDI
PBLKI
DV
DD2
DVSS3
ADCLKI
AV
DD1
AVSS1
AVSS2
DVSS2
DVSS1
DVDD1
AVDD2
C2C1D6D7D8
CCDIN
C4
C3
VSS6
SSI1
MCKO
V
SS2
RG
V
DD2
OSCO
OSCI
V
DD5
H2
H1
V
SS3
VSS5
CKO
CKI
V
DD3
VDD4
XRS
CLPDM
CLPOB
V
SS4
XSHP
XSHD
PBLK
NC
NC
SCK2
SSI2
TEST3
AV
SS4
C8
AV
SS6
AVDD5
D2
D1
D0
SEN2
TEST5
AV
DD4
C7
AV
SS3
AVDD3
D5
D4
D3
TEST4
AV
SS5
C9
Serial interface data
HD
+3.3V
+15.0V
–7.5V
C2
C2 C2
C2
C2
R1
R1
R1
R2
R1
R1 R1
C2
C2
C2
C2
C2
C2
C2
C2
C2
C1
C1
C1
C1
C1
C1
C2
C3
CKI
C6 C4 C5 C5 C6 C6
C1 3300pF C2 560pF C3 820pF C4 8pF C5 180pF C6 10pF
R1 30Ω R2 10Ω
Page 11
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CXD3408GA
AC Characteristics
AC characteristics between the serial interface clocks
SSI1
0.2V
DDd
0.2VDDd
0.8V
DDd
ts2
th1ts1
ts3
0.8V
DDd
0.8V
DDd
SCK1
SEN1
SEN1
Symbol
ts1
th1
ts2
ts3
Definition
SSI1 setup time, activated by the rising edge of SCK1
SSI1 hold time, activated by the rising edge of SCK1
SCK1 setup time, activated by the rising edge of SEN1
SEN1 setup time, activated by the rising edge of SCK1
Min. Typ. Max.
20
20
20
20
Unit
ns
ns
ns
ns
Serial interface clock internal loading characteristics (1)
(Within the recommended operating conditions)
th1
Enlarged view
Example: During frame mode
0.2V
DDd
ts1
0.2V
DDd
V1A
VD
HD
HD
V1A
SEN1
0.8V
DDd
Symbol
t
s1
t
h1
Definition
SEN1 setup time, activated by the falling edge of HD
SEN1 hold time, activated by the falling edge of HD
Min. Typ. Max.
0
110
Unit
ns
µs
∗
Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal period
during which V1A/B and V3A/B values take the ternary value and during that horizontal period.
(Within the recommended operating conditions)
Page 12
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CXD3408GA
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD3408GA at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD3408GA and controlled at the rising edge of SEN1. See "Description of Operation".
0.8VDDd
SEN1
Output signal
tpdPULSE
Symbol
tpdPULSE
Definition
Output signal delay, activated by the rising edge of SEN1
Min. Typ. Max.
1005
Unit
ns
(Within the recommended operating conditions)
Serial interface clock internal loading characteristics (2)
th1
0.2VDDd
ts1
0.2V
DDd
VD
HD
VD
HD
SEN1
0.8V
DDd
Enlarged view
Example: During frame mode
Symbol
ts1
th1
Definition
SEN1 setup time, activated by the falling edge of VD
SEN1 hold time, activated by the falling edge of VD
Min. Typ. Max.
0
200
Unit
ns
ns
∗
Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD.
(Within the recommended operating conditions)
Page 13
– 13 –
CXD3408GA
RST
0.2VDDd
tw1
0.8VDDd
VD
HD
ts1
th1
0.2V
DDd
0.2V
DDd
0.2V
DDd
RST loading characteristics
Symbol
tw1
Definition
RST pulse width
Min. Typ. Max.25Unit
ns
(Within the recommended operating conditions)
VD and HD phase characteristics
Symbol
t
s1
t
h1
Definition
VD setup time, activated by the falling edge of HD
VD hold time, activated by the falling edge of HD
Min. Typ. Max.
20
100
Unit
ns
ns
(Within the recommended operating conditions)
HD
MCKO
ts1
th1
0.2VDDd
0.8V
DDd
0.2VDDd
HD loading characteristics
Symbol
ts1
th1
Definition
HD setup time, activated by the rising edge of MCKO
HD hold time, activated by the rising edge of MCKO
Min. Typ. Max.
20
5
Unit
ns
ns
MCKO load capacitance = 10pF
(Within the recommended operating conditions)
Page 14
– 14 –
CXD3408GA
0.8VDDd
MCKO
WEN, ID/EXP
tpd1
WEN and ID/EXP load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpd1
Definition
Time until the above outputs change after the rise of MCKO
Min. Typ. Max.
6020
Unit
ns
Output variation characteristics
Page 15
– 15 –
CXD3408GA
CCD Signal Processor Block Electrical Characteristics
DC Characteristics (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Item
Supply voltage 1
Supply voltage 2
Supply voltage 3
Analog input
capacitance
Input voltage
A/D clock duty
Output voltage
Pins
DVDD1
DVDD2
AVDD1,
AVDD2,
AVDD3,
AVDD4,
AVDD5
CCDIN
SCK2, SSI2,
SEN2, TEST3,
TEST4, XSHDI,
XSHPI, ADCLKI,
CLPOBI,
CLPDMI, PBLKI
ADCLKI
D0 to D9
Symbol
VDDe
VDDf
VDDg
CIN
VI +
VI –
VOH
VOL
Conditions
Feed current where I
OH = –2.0mA
Pull-in current where IOL = 2.0mA
Min.
3.0
3.0
3.0
VDDe – 0.9
Typ.
3.3
3.3
3.3
15
1.8
1.1
50
Max.
3.6
3.6
3.6
0.4
Unit
V
V
V
pF
V
V
%
V
V
Analog Characteristics (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Item
CCDIN input voltage amplitude
PGA maximum gain
PGA minimum gain
ADC resolution
ADC maximum conversion rate
ADC integral non-linearity error
ADC differential non-linearity error
Signal-to-noise ratio
CCDIN input voltage clamp level
CCD optical black signal clamp
level
Symbol
V
IN
Gmax
Gmin
Fc max
EL
ED
SNR
∗1
CLP
OB
Conditions
PGA gain = 0dB, output full scale
PGA gain setting data = "3FFh"
PGA gain setting data = "000h"
PGA gain = 0dB
PGA gain = 0dB
CCDIN input connected to GND
via a coupling capacitor
PGA gain = 0dB
OBLVL = "8h"
PGA gain = 0dB
Min.
900
18
Typ.
42
–6
10
±1.0
±0.5
62
1.5
32
Max.
1100
±5.0
±1.0
Unit
mV
dB
dB
bit
MHz
LSB
LSB
dB
V
LSB
∗
1
SNR = 20 log (full-scale voltage/rms noise)
Page 16
– 16 –
CXD3408GA
AC Characteristics
AC characteristics between the serial interface clocks
SSI2
0.2V
DD
0.2VDD
0.8VDD
ts2
th1ts1
ts3
0.8V
DD
0.8VDD
SCK2
SEN2
SEN2
Symbol
tp1
ts1
th1
ts2
ts3
Definition
SCK2 clock period
SSI2 setup time, activated by the rise of SCK2
SSI2 hold time, activated by the rise of SCK2
SCK2 setup time, activated by the rise of SEN2
SEN2 setup time, activated by the rise of SCK2
Min. Typ. Max.
100
30
30
30
30
Unit
ns
ns
ns
ns
ns
(Fc = 18MSPS, DV
DD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
∗
The setting values are reflected to the operation 6 ADCLKI clocks after the serial data is loaded at the rise of
SEN2.
Page 17
– 17 –
CXD3408GA
CDS/ADC Timing Chart
N N + 1
N – 10
CCDIN
XSHPI
XSHDI
ADCLKI
D0 to D9
N – 9N – 8N – 7
tw1
DL
N + 2 N + 3
Symbol
tw1
DL
Definition
ADCLKI clock period
ADCLKI clock duty
Data latency
Min. Typ. Max.
50
9
54
Unit
ns
%
clocks
(Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
∗
Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0".
Preblanking Timing Chart
11 Clocks
11 Clocks
PBLKI
ADCLKI
D0 to D9
All "0"
Page 18
– 18 –
CXD3408GA
Description of Operation
Pulses output from the CXD3408GA's timing generator block are controlled mainly by the RST pin and by the
serial interface data. The Pin Status Table is shown below, and the details of serial interface control are
described on page 20 and thereafter.
Pin Status Table
Pin
No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
NC
NC
SCK2
SSI2
TEST3
AV
SS4
C8
AVSS6
AVDD5
D2
D1
D0
SEN2
TEST5
AVDD4
C7
AVDD3
AVSS3
D5
D4
D3
TEST4
AVSS5
C9
C3
C4
CCDIN
D8
D7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D3
D7
D8
D9
E1
E2
E3
E7
E8
E9
F1
F2
F3
F7
F8
F9
G1
G2
G3
G7
G8
G9
H1
H2
H3
H7
H8
H9
J1
D6
C1
C2
AVSS1
D9
DVDD1
DVSS1
AVSS2
AVDD2
AVDD1
DVSS2
DVSS3
DVDD2
PBLKI
XSHDI
XSHPI
ADCLKI
CLPOBI
CLPDMI
PBLK
XSHD
XSHP
ADCLK
CLPOB
CLPDM
XRS
VDD4
VDD3
CKI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ACT L L H
ACT L L ACT
ACT L L ACT
ACT L L ACT
ACT L L H
ACT L L H
ACT L L ACT
—
—
ACT ACT ACT ACT
Symbol CAM SLP RST
Pin
No.
Symbol
STB CAM SLP RSTSTB
Page 19
– 19 –
CXD3408GA
∗1
It is for output. For input, all items are "ACT".
Note) ACT means that the circuit is operating, and DIS means that loading is stopped.
L indicates a low output level, and H a high output level in the controlled status.
Also, VH, VM and VL indicate the voltage levels applied to VH (Pin M5), VM (Pin L4) and VL (Pin M6),
respectively, in the controlled status.
Pin
No.
J2
J3
J7
J8
J9
K1
K2
K3
K7
K8
K9
L1
L2
L3
L4
L5
L6
L7
L8
CKO
V
SS5
VSS3
H1
H2
OSCO
MCKO
VDD5
VDD2
RG
VSS2
OSCI
SSI1
VSS4
VM
V1A
V3A
VSS1
SSGSL
ACT ACT L ACT
—
—
ACT L L ACT
ACT L L ACT
ACT ACT ACT ACT
ACT ACT L ACT
—
—
ACT L L ACT
—
ACT ACT ACT ACT
ACT ACT ACT DIS
—
—
ACT VH VH VM
ACT VH VH VL
—
ACT ACT ACT ACT
L9
M1
M2
M3
M4
M5
M6
M7
M8
M9
N1
N2
N3
N4
N5
N6
N7
N8
N9
VDD1
SCK1
VD
∗1
TEST1
V2
VH
VL
TEST2
RST
WEN
SEN1
HD
∗1
VSS6
V4
V1B
V3B
SUB
SNCSL
ID/EXP
—
ACT ACT ACT DIS
ACT L L H
—
ACT VM VM VM
—
—
—
ACT ACT ACT L
ACT L L L
ACT ACT ACT DIS
ACT L L H
—
ACT VM VM VL
ACT VH VH VM
ACT VH VH VL
ACT VH VH VL
ACT ACT ACT ACT
ACT L L L
Symbol
Pin
No.
Symbol
CAM SLP RSTSTB CAM SLP RSTSTB
Page 20
– 20 –
CXD3408GA
Timing Generator Block Serial Interface Control
The CXD3408GA's timing generator block basically loads and reflects the timing generator block serial
interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion
specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value.
Note that some items reflect the timing generator block serial interface data at the falling edge of VD or the
rising edge of SEN1.
00 01 02 03 04 05 06 07 41 42 43 44 45 46 47
SSI1
SCK1
SEN1
There are two categories of timing generator block serial interface data: CXD3408GA timing generator block
drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data").
The details of each data are described below.
Page 21
– 21 –
CXD3408GA
Control Data
Data
D00
to
D07
D08,
D09
D10
to
D12
D13
D14
D15,
D16
D17
D18
to
D31
D32
D33
D34,
D35
D36,
D37
D38,
D39
D40
to
D47
Symbol
CHIP
CTG
MODE
SMD
HTSG
—
NTPL
—
FGOB
EXP
PTOB
LDAD
STB
—
Function
Chip enable
Category switching
Drive mode switching
Electronic shutter mode switching
∗
1
HTSG control switching
∗1
—
SSG function switching
—
Wide OBCLP generation switching
ID/EXP output switching
OBCLP waveform patterm switching
ADCLK logic phase adjustment
Standby control
—
Data = 0 Data = 1
10000001 → Enabled
Other values → Disabled
See D08 to D09 CTG.
See D10 to D12 MODE.
OFF ON
OFF ON
——
NTSC PAL
——
OFF ON
ID EXP
See D34 to D35 PTOB.
See D36 to D37 LDAD.
See D38 to D39 STB.
——
RST
All
0
All
0
All
0
0
0
All
0
0
All
0
0
0
All
0
All
0
All
0
∗1
See D13 SMD.
1
0
Page 22
– 22 –
CXD3408GA
Shutter Data
Data
D00
to
D07
D08,
D09
D10
to
D19
D20
to
D31
D32
to
D41
D42
to
D47
Symbol
CHIP
CTG
SVD
SHD
SPL
—
Function
Chip enable
Category switching
Electronic shutter vertical period
specification
Electronic shutter horizontal period
specification
High-speed shutter position
specification
—
Data = 0 Data = 1
10000001 → Enabled
Other values → Disabled
See D08 to D09 CTG.
See D10 to D19 SVD.
See D20 to D31 SHD.
See D32 to D41 SPL.
——
RST
All
0
All
0
All
0
All
0
All
0
All
0
Page 23
– 23 –
CXD3408GA
Detailed Description of Each Data
Shared data: D08 , D09 CTG [Category]
Of the data provided to the CXD3408GA by the serial interface, the CXD3408GA loads D10 and subsequent
data to each data register as shown in the table below according to the combination of D08 and D09 .
D09
0
0
1
D08
0
1
X
Description of operation
Loading to control data register
Loading to shutter data register
Test mode
D11
0
0
1
1
D12
0
0
0
0
D10
0
1
0
1
D11
0
0
1
1
D12
1
1
1
1
D10
0
1
0
1
Description of operation Description of operation
Draft mode (default)
AF1 mode
AF2 mode
Frame mode
Draft mode
Frame mode (A field read out)
Frame mode (B field read out)
Test mode
Note that the CXD3408GA can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Control data: D10 to D12 MODE [Drive mode]
The CXD3408GA timing generator block drive mode can be switched as follows. However, the drive mode bits
are located to the CXD3408GA and reflected at the falling edge of VD.
Draft mode is the pulse eliminator drive mode called octuple speed mode in the ICX406. This is a high frame
rate drive mode that can be used for purposes such as monitoring and auto focus (AF).
AF1 and AF2 modes are the pulse eliminator drive modes called by the same names in the ICX406. These
drive modes are based on draft mode, and are used to increase the frame rate for auto focus (AF). In these
modes, the screen is swept in the vertical direction and the center portion lines are cut out.
Frame mode is the ICX406 drive mode in which the data for all lines are read. This drive mode is comprised of
A and B Fields, so when it is established, repeated drive is performed in the manner of A → B → A → and so
on.
Frame mode (A or B Field) is the drive mode in which each field can be specified separately.
Control data: D17 NTPL [SSG function switching]
The CXD3408GA internal SSG output pattern can be switched as follows. However, the SSG function switching
bits are loaded to the CXD3408GA and reflected at the falling edge of VD.
D17
0
1
Description of Operation
NTSC equivalent pattern output
PAL equivalent pattern output
VD period in each pattern is defined as follows.
See the Timing Charts for the actual operation.
NTSC equivalent pattern
PAL equivalent pattern
Frame mode
1012H + 1672ck
944H + 464ck
Draft mode
224H + 1372ck × 2
269H + 2039ck
AF1 mode
112H + 1372ck
134H + 2354ck
AF2 mode
56H + 686ck
67H + 1178ck
Page 24
– 24 –
CXD3408GA
Control data: D32 FGOB [Wide CLPOB generation]
This controls wide CLPOB generation during the vertical OPB period. See the Timing Charts for the actual
operation. The default is "OFF".
D32
0
1
Description of operation
Wide CLPOB generation OFF
Wide CLPOB generation ON
Control data: D34 , D35 PTOB [CLPOB waveform pattern]
This indicates the CLPOB waveform pattern. The default is "Normal".
D35
0
0
1
1
D34
0
1
0
1
Waveform pattern
(Normal)
(Shifted rearward)
(Shifted forward)
(Wide)
Control data: D36 , D37 LOAD [ADCLK logical phase]
This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO.
D37
0
0
1
1
D36
0
1
0
1
Degree of adjustment (°)
0
90
180
270
Control data: D38 , D39 STB [Standby]
The operating mode is switched as follows. However, the standby bits are loaded to the CXD3408GA and
control is applied immediately at the rising edge of SEN1.
D39
X
0
1
D38
0
1
1
Symbol
CAM
SLP
STB
Operating mode
Normal operating mode
Sleep mode
Standby mode
See the Pin Status Table for the pin status in each mode.
Page 25
– 25 –
CXD3408GA
Control data/shutter data: [Electronic shutter]
The CXD3408GA realizes various electronic shutter functions by using control data D13 SMD and D14 HTSG
and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL.
These functions are described in detail below.
First, the various modes are shown below.
These modes are switched using control data D13 SMD.
D13
0
1
Description of operation
Electronic shutter stopped mode
Electronic shutter mode
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example.
However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC.
MSB LSB
D29 D28D31 D30 D27 D26 D25 D24 D23 D22 D21 D20
1100
↓
C
X001
↓
1
0011
↓
3
SHD is expressed as 1C3h .
[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[Electronic shutter mode]
During this mode, the shutter data items have the following meanings.
Note) The bit data definition area is assured in terms of the CXD3408GA functions, and does not assure the
CCD characteristics.
The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure
time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the
operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors.
(Exposure time) = SVD + {(number of HD per 1V) – (SHD + 1)}
Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed
shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this
period is finished.
The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of
horizontal periods applied to SHD can be considered as (number of SUB pulses – 1).
Symbol
SVD
SHD
SPL
Data
D10 to D19
D20 to D31
D32 to D41
Description
Number of vertical periods specification (000h ≤ SVD ≤ 3FFh)
Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh)
Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh)
Page 26
– 26 –
CXD3408GA
VD
SHD
1
V1A
SUB
WEN
SMD
000h
002h
SVD
050h
10Fh
SHD
1
SVD
EXP
Exposure time
VD
SPL
001 002000
SHD
1
V1A
SUB
WEN
SMD
000h
001h
SPL
000h
002h
SVD
0A3h
10Fh
SHD
EXP
Exposure time
1
SVD
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the
low-speed shutter period.
In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD.
Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed
shutter to high-speed shutter or vice versa.
Page 27
– 27 –
CXD3408GA
VD
V1A
SUB
WEN
0
1
0
HTSG
1
0
1
SMD
Vck
Exposure time
EXP
[HTSG control mode]
This mode controls the V1A/B and V3A/B ternary level outputs (readout pulse block) using D14 HTSG.
D14
0
1
Description of operation
Readout pulse (SG) normal operation
HTSG control mode
[EXP pulse]
The ID/EXP pin (N9) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The
default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time
when it is high. The transition point is the last SUB pulse falling edge, and midpoint value (1338ck) of each
V1A/B and V3A/B ternary out put falling edge. When there is no SUB pulse, the later ternary output falling
edge (1416ck) is used. See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for
an image of operation.
Note that the above specification is based on draft mode. For frame mode, the former value is 1260ck and the
latter value is 1416ck.
Page 28
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CXD3408GA
VD
SUB
CLPOB
CLPDM
V1ACCV1B
V2
V3A
V3B
V4
CCD OUT
1547
1719
1712
1714
1716
1718
1720
1709
1711
1713
1715
3
1
57
246810
2
12
4689111357911
PBLK
ID/EXP
WEN
A Field B Field
HD
1
75 82
174821013943 9431013
A B
High-speed sweep block High-speed sweep block
∗
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗
VD of this chart is NTSC equivalent pattern (1012H + 1672ck units). For PAL equivalent pattern, it is 944H + 464ck units.
Chart-1 Vertical Direction Timing Chart
MODE
Frame mode
Applicable CCD image sensor
• ICX406
Page 29
– 29 –
CXD3408GA
VD
HD
SUB
V1A
V2
V3A
V3B
V4
CLPOB
CLPDM
ID/EXP
PBLK
V1B
CCD OUT
145
10
21 30 37
101
61
17 26 33
46
42
5
10
14 21 30 37
1
6
1
10 17 26 33
46
42
WEN
3
1
218
3
1218
D D
1717
1710
1713
1706
1717
1710
1713
1706
226226
∗
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗
VD of this chart is NTSC equivalent pattern (224H + 1372ck + 1372ck units). For PAL equivalent pattern, it is 269H + 2039ck units.
Chart-2 Vertical Direction Timing Chart
MODE
Draft mode
Applicable CCD image sensor
• ICX406
Page 30
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CXD3408GA
VD
SUB
CLPOB
CLPDM
V1A
V1B
V2
V3A
V3B
V4
CCD OUT
PBLK
ID/EXP
WEN
HD
2
9
29106 106
10
6
10
6
E FG GEF
113113
High-speed
sweep block
Frame shift block
High-speed
sweep block
Frame shift block
∗
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗
240 stages are fixed for high-speed sweep block; 232 stages are fixed for frame shift block.
∗
VD of this chart is NTSC equivalent pattern (112H + 1372ck units). For PAL equivalent pattern, it is 134H + 2354ck units.
Chart-3 Vertical Direction Timing Chart
MODE
AF1 mode
Applicable CCD image sensor
• ICX406
Page 31
– 31 –
CXD3408GA
VD
SUB
CLPOB
CLPDM
V1A
High-speed sweep block
V1B
V2
V3A
V3B
V4
CCD OUT
PBLK
ID/EXP
WEN
HD
2
12
21247 47
10
6
10
6
G G E FE
Frame shift block
High-speed sweep block
Frame shift block
F
57 57
∗
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗
360 stages are fixed for high-speed sweep block; 360 stages are fixed for frame shift block.
∗
VD of this chart is NTSC equivalent pattern (56H + 686ck units). For PAL equivalent pattern, it is 67H + 1178ck units.
Chart-4 Vertical Direction Timing Chart
MODE
AF2 mode
Applicable CCD image sensor
• ICX406
Page 32
– 32 –
CXD3408GA
HD
MCKO
H1
H2
V1A/BV2V3A/B
V4
SUB
PBLK
CLPOB (1)
CLPOB (2)
CLPOB (3)
CLPOB (4)
CLPOB (wide)
CLPDM
(2669)
0 50 100 200150 250 300 350 400 450 500 550
ID/EXP
WEN
317 345 361 365
604
18892
5024
4216
5816
34758
5832
343319
252156
22060
34360
284124
232168
124
124
∗
The HD of this chart indicates the actual CXD3408GA load timing.
∗
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
∗
SUB is output at the timing shown above when output is controlled by the serial interface data.
∗
ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1.
Chart-5 Horizontal Direction Timing Chart
MODE
Frame mode
Applicable CCD image sensor
• ICX406
Page 33
– 33 –
CXD3408GA
HD
MCKO
H1
H2
V1A/BV2V3A/B
V4
SUB
PBLK
CLPOB (1)
CLPOB (2)
CLPOB (3)
CLPOB (4)
CLPOB (wide)
CLPDM
(2669)
0 50 100 200150 250 300 350 400 450 500 550
ID/EXP
WEN
317 345 361 365
604
9268
5024
4216
5816
34758
5832
343319
10884
10060
34360
11676
232168
124
124
156132
172148
164124
180140
220196
212
228188
244204
284260
300276
292252
308268
236
∗
The HD of this chart indicates the actual CXD3408GA load timing.
∗
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
∗
SUB is output at the timing shown above when output is controlled by the serial interface data.
∗
ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4.
Chart-6 Horizontal Direction Timing Chart
MODE
Draft mode, AF1 mode, AF2 mode
Applicable CCD image sensor
• ICX406
Page 34
– 34 –
CXD3408GA
HD
MCKO
H1
H2
V1A/BV2V3A/B
V4
SUB
PBLK
CLPOB
CLPDM
(2669)
0 50 100 200150 250 300 350 400 450 500 550
ID/EXP
WEN
317 345 361 365
604
11660
232168
172 228 284 340 396 452 508 564
11660 172 228 284 340 396 452 508 564
14488 200 256 312 368 424 480 536
14488 200 256 312 368 424 480 536
#4#3#2#1 #5
∗
The HD of this chart indicates the actual CXD3408GA load timing.
∗
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
∗
SUB is output at the timing shown above when output is controlled by the serial interface data.
∗
ID/EXP of this chart shows ID.
∗
High-speed sweep of V1A/B, V2, V3A/B, V4 is performed up to 72H of 2660ck (#1739).
Chart-7 Horizontal Direction Timing Chart
(High-speed sweep: C)
MODE
Frame mode
Applicable CCD image sensor
• ICX406
Page 35
– 35 –
CXD3408GA
HD
MCKO
H1
H2
V1A/BV2V3A/B
V4
SUB
PBLK
CLPOB
CLPDM
(2669)
0 50 100 200150 250 300 350 400 450 500 550
ID/EXP
WEN
317 345 361 365
604
232168
60
60
5024
124
100 124 164 188 228 252 292 316 356 380 420 444 484 508 548
108 148 172 212 236 276 300 340 364 404 428 468 492 532 55684
92 132 156 196 220 260 284 324 348 388 412 452 476 516 54068
76 116 140 180 204 244 268 308 332 372 396 436 460 500 524
#6 #7#4 #5#3#1 #2 #8
∗
The HD of this chart indicates the actual CXD3408GA load timing.
∗
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
∗
SUB is output at the timing shown above when output is controlled by the serial interface data.
∗
ID/EXP of this chart shows ID. PBLK, CLPOB, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4.
∗
Frame shift of V1A/B, V2, V3A/B and V4 is performed up to 7H 1563ck (#232) in AF1 mode and 10H 1688ck (#360) in AF2 mode.
In addition, high-speed sweep is performed up to 111H 2015ck (#240) in AF1 mode and 55H 1688ck (#360) in AF2 mode.
Chart-8 Horizontal Direction Timing Chart
(Frame shift: F)
(High-speed sweep: G)
MODE
AF1 mode, AF2 mode
Applicable CCD image sensor
• ICX406
Page 36
– 36 –
CXD3408GA
HD
[A Field]
[B Field]
A
B
V3B
V4
V3B
V4
V1A
V1B
V2
V3A
V1A
V1B
V2
V3A
(2669)
0
(2669)
0
1104
1136
1168
1200
1202
1260
1292
124
156
188
220
252
284
∗
The HD of this chart indicates the actual CXD3408GA load timing.
∗
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
Chart-9 Horizontal Direction Timing Chart
MODE
Frame mode
Applicable CCD image sensor
• ICX406
Page 37
– 37 –
CXD3408GA
HD
D
V3B
V4
V1A
V1B
V2
V3A
(2669)
0
(2669)
0
1104
1136
1168
1200
1202
1356
1358
1260
1292
1324
1416
60
76
92
108
124
140
156
172
68
84
100
116
132
148
164
180
∗
The HD of this chart indicates the actual CXD3408GA load timing.
∗
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
Chart-10 Horizontal Direction Timing Chart
MODE
Draft mode
Applicable CCD image sensor
• ICX406
Page 38
– 38 –
CXD3408GA
HD
E
V3B
V4
V1A
V1B
V2
V3A
(2669)
0
(2669)
0
1104
1136
1168
1200
1202
1356
1358
1260
1292
1324
1416
60
76
92
108
124
140
156
172
68
84
100
116
132
148
164
180
188
204
220
236
252
268
284
300
196
212
228
244
260
276
292
308
1448
1464
1480
1496
1512
1528
1544
1560
1456
1472
1488
1504
1520
1536
1552
1568
∗
The HD of this chart indicates the actual CXD3408GA load timing.
∗
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
Chart-11 Horizontal Direction Timing Chart
MODE
AF1 mode, AF2 mode
Applicable CCD image sensor
• ICX406
Page 39
– 39 –
CXD3408GA
HD
HD'
CKI
CKO
ADCLK
MCKO
H1
H2
RG
XSHP
XSHD
XRS
317
60
1
∗
HD' indicates the HD which is the actual CXD3408GA load timing.
∗
The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse.
∗
The logical phase of ADCLK can be specified by the serial interface data.
Chart-12 High-Speed Phase Timing Chart
MODE
Applicable CCD image sensor
• ICX406
Page 40
– 40 –
CXD3408GA
VD
V1A
V1B
V2
V3A
V3B
V4
SUB
Mechanical
shutter
Exposure
time
CCD OUT
MODE
SMD
SHD
Close Open
ABC
EE
F
00000 3 3 00
11111 0 0 1 1
050h 050h 050h 050h 050h 000h 000h 050h 050h
ABCDE F
∗
This chart is a drive timing chart example of electronic shutter normal operation.
∗
Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet.
∗
The CXD3408GA does not generate the pulse to control mechanical shutter operation.
∗
The switching timing of drive mode and electronic shutter data is not the same.
Chart-13 Vertical Direction Sequence Chart
MODE
Draft → Frame → Draft
Applicable CCD image sensor
• ICX406
Page 41
– 41 –
CXD3408GA
CCD Signal Processor Block Serial Interface Control
The CXD3408GA's CCD signal processor block basically loads the CCD signal processor block serial interface
data sent in the following format at the rising edge of SEN2, and the setting values are then reflected to the
operation 6 ADCLKI clocks after that.
CCD signal processor block serial interface control requires clock input to ADCLKI in order to load and reflect
the serial interface data to operation, so this should normally be performed when the timing generator block is
in the normal operation mode.
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
SSI2
SCK2
SEN2
There are four categories of CCD signal processor block serial interface data: standby control data, PGA gain
setting data, OB clamp level setting data, and input pulse polarity setting data.
Note that when data from multiple categories is loaded consecutively, the data for the category loaded last is
valid and data from other categories is lost. When transferring data from multiple categories, raise SEN2 for
each category and wait until the setting value 6 ADCLKI clocks after that has been reflected to operation, then
transmit the next category.
The detail of each data are described below.
Standby Control Data
Data
D00
D01
to
D03
D04
to
D14
D15
Symbol
TEST
CTG
FIXED
STB
Function
Test code
Category switching
—
Standby control
Data = 0 Data = 1
Set to 0.
D01 to D03 CTG
Set to All 0.
Normal operating mode Standby mode
Data
D00
D01
to
D03
D04,
D05
D06
to
D15
Symbol
TEST
CTG
FIXED
GAIN
Function
Test code
Category switching
—
PGA gain setting data
Data = 0 Data = 1
Set to 0.
D01 to D03 CTG
Set to All 0.
See D06 to D15 GAIN.
PGA Gain Setting Data
Page 42
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CXD3408GA
Data
D00
D01
to
D03
D04
to
D11
D12
to
D15
Symbol
TEST
CTG
FIXED
OBLVL
Function
Test code
Category switching
—
OB clamp level setting data
Data = 0 Data = 1
Set to 0.
D01 to D03 CTG
Set to All 0.
See D12 to D15 OBLVL.
OB Clamp Level Setting Data
Data
D00
D01
to
D03
D04
to
D12
D13
to
D15
Symbol
TEST
CTG
FIXED
POL
Function
Test code
Category switching
—
Input pulse polarity setting data
Data = 0 Data = 1
Set to 0.
D01 to D03 CTG
Set to All 0.
Set to All 0.
Input Pulse Polarity Setting Data
Page 43
– 43 –
CXD3408GA
Detailed Description of Each Data
Shared data: D01 to D03 CTG [Category]
Of the data provided to the CXD3408GA by the CCD signal processor block serial interface, the CXD3408GA
loads D04 and subsequent data to each data register as shown in the table below according to the combination
of D01 to D03 .
PGA gain setting data: D06 to D15 GAIN [PGA gain]
The CXD3408GA can set the programmable gain amplifier (PGA) gain from –6dB to +42dB in 1024 steps by
using PGA gain setting data D06 to D15 GAIN.
The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN.
D01
0
0
0
0
1
D02
0
0
1
1
X
D03
0
1
0
1
X
Description of operation
Loading to standby control data register
Loading to PGA gain setting data register
Loading to OB clamp level setting data register
Loading to input pulse polarity setting data register
Access prohibited
Standby control data: D15 STB [Standby]
The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor
block is in standby mode, only the serial interface is valid.
D15
0
1
Description of operation
Normal operating mode
Standby mode
MSB LSB
D06 D07 D08 D09 D10 D11 D12 D13 D14 D15
1100
↓
C
01
↓
1
0011
↓
3
GAIN is expressed as 1C3h .
For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting
values are –6dB, 0dB, +20dB, +34dB and +42dB.
Page 44
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CXD3408GA
OB clamp level setting data: D12 to D15 OBLVL [OB clamp level]
The CXD3408GA can set the OPB clamp output value from 0 to 60LSB in 4LSB steps by using CCD signal
processor block control data D12 to D15 OBLVL.
The OPB clamp output setting data is expressed as shown in the table below using D12 to D15 OBLVL.
MSB LSB
D12 D13 D14 D15
0110
↓
6
OBLVL is expressed as 6h .
For example, when OBLVL is set to "0h", "1h", "8h" and "Fh", the respective OPB clamp output setting values
are 0LSB, 4LSB, 32LSB and 60LSB.
Page 45
– 45 –
CXD3408GA
Application Circuit Block Diagram
SEN2
SCK2
SSI2
F9 F8 F7 G2G3 G9 G8 G7 H2 H1 G1 B7 A7 C6
B3
A1A2B2
B1
C3C2C1D3D2
D1
E1J2K2
M2
N2
N9
M9
M8
N8
L8
M4
N5
L5
K8
J9
J8
C8
C7
D8
D7
C9
N4L5N7
N6
A3B4A4M1N1L2B5C4L1J1 K1 A5M7M3
H3
CCD
ICX406
TG/CDS/PGA/ADC
CXD3408GA
Controller
SSI1
SEN1
SCK1
TEST5
TEST4
TEST3
TEST2
TEST1
OSCO
CKI
OSCI
D1
VD
HD
D0 (LSB)
Signal
Processor
Block
D2
NC
NC
D3D4D5D6D7D8D9 (MSB)
MCKO
CKO
SSGSL
SNCSL
RST
WEN
ID/EXP
0.1µF
C7
XSHPI
XSHDI
PBLKI
CLPDMI
CLPOBI
XSHP
XSHD
PBLK
CLPDM
CLPOB
ADCLK
ADCLKI
0.1µF
C8
0.1µF
C9
1µF
C1
1µF
CCDINCCDOUT
390pFC2390pFC3240pF
C4
H1
H2
RG
V1A
V1BV2V3A
V3B
V4
SUB
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
This block diagram illustrates connections with each circuit
block, and is not an actual circuit diagram. See the CCD
image sensor data sheet for an example of specific circuit
connections with the CCD image sensor.
Page 46
– 46 –
CXD3408GA
Notes on Operation
1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the
figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In
addition, start up the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pin and CCD signal processor
block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin power supplies at the same time either
before or at the same time as the VH pin power supply is started up.
2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator
block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by
initializing the serial data.
3. Separate the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins from the CCD signal processor
block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pins.
Also, the ADC output driver stage is connected to the dedicated power supply pin DVDD1. Separating this
pin from other power supplies is recommended to avoid affecting the internal analog circuits.
4. The difference in potential between the timing generator block VDD4 pin supply voltage 3 VDDc and the CCD
signal processor block DV
DD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin supply voltages 1 VDDe,
2 V
DDf and 3 VDDg should be 0.1V or less.
5. The timing generator block and CCD signal processor block ground pins should use a shared ground which
is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the
timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to
the analog ground. The difference in potential between the timing generator block VSS1, VSS2, VSS3, VSS4,
V
SS5, VSS6 and VM and the CCD signal processor block DVSS1, DVSS2, DVSS3, AVSS1, AVSS2, AVSS3, AVSS4,
AVSS5 and AVSS6 should be 0.1V or less.
6. Do not perform serial communication with the CCD signal processor block during the effective image
period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which
are used by the CCD signal processor block, use of the dedicated ports is recommended. When using
these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the
effects on picture quality before use.
t1
t2
15.0V
0V
–7.5V
20%
20%
t2 ≥ t1
Page 47
– 47 –
CXD3408GA
Package Outline Unit: mm
96PIN LFLGA
PACKAGE MASS
PACKAGE STRUCTURE
ORGANIC SUBSTRATE
0.3 g
PACKAGE MATERIAL
TERMINAL TREATMENT
TERMINAL MATERIAL
GOLD PLATING
NICKEL PLATING
SONY CODE
EIAJ CODE
JEDEC CODE
LFLGA-96P-02
P-LFLGA96-12X8-0.8
1.3 MAX
S
0.10
DETAIL X
S
S
0.2
PIN 1 INDEX
X
B
B
0.2
12.0
S
8.0
A0.2 S
0.15
x4
0.8
B
D
E
F
G
H
J
K
L
C
A
M
N
123456789
0.8
M
SAB
96 -φ0.45 ± 0.05
A
0.5
0.5
3 – φ0.50
0.5
0.9
0.9
1.2
0.8
0.10MAX
0.5
φ0.08
(0.3)
(0.3)
(0.3)
(0.3)
Sony Corporation
96PIN LFLGA
PACKAGE MASS
PACKAGE STRUCTURE
ORGANIC SUBSTRATE
0.3g
PACKAGE MATERIAL
TERMINAL TREATMENT
TERMINAL MATERIAL
SONY CODE
EIAJ CODE
JEDEC CODE
LFLGA-96P-051
P-LFLGA96-12.0X8.0-0.8
1.3 MAX
S
0.10
DETAIL X
S
S
0.2
PIN 1 INDEX
X
B
B
0.2
12.0
S
8.0
A0.2 S
0.15
x4
0.8
B
D
E
F
G
H
J
K
L
C
A
M
N
123456789
0.8
M
SAB
96 -φ0.45 ± 0.05
A
0.5
0.5
3 – φ0.50
0.5
0.9
0.9
1.2
0.8
0.10MAX
0.5
φ0.08
(0.3)
(0.3)
(0.3)
(0.3)
NICKEL & GOLD PLATING
COPPER
Oita Ass'y
HITACHI TOKYO Ass'y
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