Datasheet CXD3068Q Datasheet (Sony)

CD Digital Signal Processor with Built-in Digital Servo

Description

The CXD3068Q is a digital signal processor LSI for

CD players. This LSI incorporates a digital servo.

Features

• All digital signal processings during playback are

performed with a single chip

• Highly integrated mounting possible due to a builtin RAM

Digital Signal Processor (DSP) Block

• Playback mode supporting CAV (Constant Angular

Velocity)

• Frame jitter free

• 0.5× to 4× continuous playback possible

• Allows relative rotational velocity readout

• Wide capture range playback mode

• Spindle rotational velocity following method

• Supports 1× to 4× playback variable pitch

playback

• Bit clock, which strobes the EFM signal, is generated by the digital PLL.

• EFM data demodulation

• Enhanced EFM frame sync signal protection

• Refined super strategy-based powerful error

correction C1: double correction, C2: quadruple correction Supported during 4× playback

• Noise reduction during track jumps

• Auto zero-cross mute

• Subcode demodulation and Sub-Q data error

detection

• Digital spindle servo

• 16-bit traverse counter

• Asymmetry correction circuit

• CPU interface on serial bus

• Error correction monitor signal, etc. output from a

new CPU interface

• Servo auto sequencer

• Fine search performs track jumps with high

accuracy

• Digital audio interface output

• Digital level meter, peak meter

• Bilingual supported

• VCO control mode

• CD TEXT data demodulation

• EFM playability reinforcement function

Digital Servo (DSSP) Block

• Microcomputer software-based flexible servo control

• Offset cancel function for servo error signal

• Auto gain control function for servo loop

• E:F balance, focus bias adjustment function

• Surf jump function supporting micro two-axis

• Tracking filter: 6 stages

Focus filter: 5 stages

Applications

CD players

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings

• Supply voltage VDD –0.5 to +4.6 V

• Input voltage VI –0.5 to +4.6 V

(VSS – 0.5V to VDD + 0.5V)

• Output voltage VO –0.5 to +4.6 V (VSS – 0.5V to VDD + 0.5V)

• Storage temperature Tstg –55 to +150 °C

•

Supply voltage difference

VSS – AVSS

–0.3 to +0.3 V

VDD – AVDD

–0.3 to +0.3 V

Note) AVDD includes XVDD and AVSS includes XVSS. Recommended Operating Conditions

• Supply voltage VDD

2.7 to 3.6 V

• Operating temperature

Topr –20 to +75 °C

Input/Output Capacitance

• Input pin CI 9 (Max.) pF

• Output pin CO 11 (Max.) pF

• I/O pin CI/O 11 (Max.) pF

Note) Measurement conditions VDD = VI = 0V

fM = 1MHz

– 1 –

PE00326-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXD3068Q

80 pin QFP (Plastic)

Preliminary

– 2 –

CXD3068Q

Block Diagram

D/A

Interface

Error

Corrector

32K

RAM

Digital

OUT

Sub Code Processor

Clock

Generator

Asymmetry

Corrector

Digital

PLL

Digital

CLV

CPU

Interface

Servo

Auto

Sequencer

Signal processor block

RFAC

ASYO ASYE

BIAS

XPCK

FILO

FILI

PCO

CLTV

MDP

LOCK

SENS DATA

XLAT

CLOK

SCOR

SBSO EXCK

SCSY SQSO SQCK

XRST

TEST

TES1

PWMI

ASYI

FSTO

C4M

Servo block

SERVO

Interface

MIRR DFCT

FOK

SERVO DSP

FOCUS SERVO

TRACKING

SERVO

SLED SERVO

PWM GENERATOR

FOCUS PWM

GENERATOR

TRACKING PWM

GENERATOR

SLED PWM

GENERATOR

RFDC

CE

TE

SE

FE

VC

IGEN

OPAmp

Analog SW

A/D

Converter

ADIO

FFDR FRDR TFDR TRDR SFDR SRDR

SOUT SOCK XOLT SCLK COUT SSTP ATSK MIRR DFCT FOK

XTAI

XTAO

XTSL

V16M

VPCO

VCTL

MUTE

BCK

PCMD

LRCK

C2PO

WDCK

DOUT

MD2

WFCK

EMPH

GFS

XUGF

EFM

demodurator

16

27

50

48

49

57

62

12

23

24

25

52

53 54 55

4 5 6

7

15

76

77

78

79

80

40 39 38

41

42

43

44

46

29 30

34

31

32

33

8

9

19

20 21 22

26

73 74 75

2

37 36

3

14

17

67

65

66

10

11

13

68

58

59

60

69

71

72

63 64

– 3 –

CXD3068Q

Pin Configuration

21

22

23

24

25

26

27

28

29

30

40 39

38 37 36 35

34

31

32

33

4142

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70

69

68

67

63 64 65 66

61

62

71

72 73

74 75 76 77 78 79 80

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

1

DVDD2

ASYE

MD2

DOUT

LRCK

PCMD

BCK

EMPH

XTSL

DV

SS2

XTAI

XTAO

SOUT

SOCK

XOLT

SQSO

SQCK

SCSY

SBSO

EXCK

SE FE

VC TES1 TEST DV

SS1

FRDR FFDR

DFCT

TRDR TFDR SRDR SFDR DV

DD1

FSTO SSTP MDP

FOK

VPCO

V16M

VCTL

PCO

FILO

CLTV

TE

ASYO

AV

DD

0

IGEN

AV

SS

0

ADIO

RFDC

BIAS

AV

DD

1

RFAC

ASYI

FILI

AV

SS

1

CE

XRST

CLOK

SCLK

XLAT

MUTE

DATA

SENS

WFCK

DV

DD

0

ATSK

MIRR

XUGF

XPCK

GFS

C2PO

SCOR

C4M

WDCK

DV

SS

0

COUT

LOCK PWMI

– 4 –

CXD3068Q

Pin Description

No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15

16 17

18 19 20 21 22 23

24 25

26 27 28 29 30 31 32 33

—

I I I I I

O

I

I/O

O O O O O O

O O

— I/O I/O I/O I/O

I

I/O

O

I

O

—

O O O O O

1, 0

1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0

1, 0 1, 0

— 1, 0 1, 0 1, 0 1, 0

1, 0

1, Z, 0

1, 0

— 1, 0 1, 0 1, 0 1, 0 1, 0

Digital power supply. System reset. Reset when low. Mute input (low: off, high: on) Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. SENS output to CPU. SENS serial data readout clock input. Anti-shock input/output. WFCK output. XUGF output. MNT0 or RFCK is output by switching with the command. XPCK output. MNT1 is output by switching with the command. GFS output. MNT2 or XROF is output by switching with the command. G2PO output. MNT3 or GTOP is output by switching with the command. Outputs a high signal when either subcode sync S0 or S1 is detected.

4.2336MHz output. 1/4 frequency division output for V16M in CAV-W mode or variable pitch mode.

Word clock output. f = 2Fs. GRSCOR is output by the command switching. Digital GND. Track count signal I/O. Mirror signal I/O. Detect signal I/O. Focus OK signal I/O. Spindle motor external control input. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.

If GFS is low eight consecutive samples, this pin outputs low. Input when LKIN = 1. Spindle motor servo control output. Disc innermost track detection signal input. 2/3 frequency division output for XTAI pin. Digital power supply. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output.

DVDD0 XRST MUTE DATA XLAT CLOK SENS SCLK ATSK WFCK XUGF XPCK GFS C2PO SCOR

C4M WDCK

DVSS0 COUT MIRR DFCT FOK PWMI

LOCK MDP

SSTP FSTO DVDD1 SFDR SRDR TFDR TRDR FFDR

Symbol I/O Description

– 5 –

CXD3068Q

34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

59 60

61 62 63 64 65 66 67

O

—

I I I I I I I I

O

—

I

—

O

I I

—

I

O

I

O

—

I I

I/O

O

—

I

I O O O O

1, 0

—

Analog

—

1, 0

—

Analog

1, Z, 0

—

1, 0

1, Z, 0

—

1, 0 1, 0 1, 0 1, 0

Focus drive output. Digital GND. Test. Normally, GND. Test. Normally, GND. Center voltage input. Focus error signal input. Sled error signal input. Tracking error signal input. Center servo analog input. RF signal input. Test. No connected. Analog GND. Constant current input for operational amplifier. Analog power supply. EFM full-swing output. (low = Vss, high = VDD) Asymmetry comparator voltage input. EFM signal input. Analog GND. Multiplier VCO1 control voltage input. Master PLL filter output (slave = digital PLL). Master PLL filter input. Master PLL charge pump output. Analog power supply. Asymmetry circuit constant current input. Wide-band EFM PLL VCO2 control voltage input. Wide-band EFM PLL VCO2 oscillation output. Serves as wide-band EFM

PLL clock input by switching with the command. Wide-band EFM PLL charge pump output. Digital power supply. Asymmetry circuit on/off (low = off, high = on). Digital Out on/off control (low = off, high = on). Digital Out output. D/A interface. LR clock output. f = Fs D/A interface. Serial data output (two's complement, MSB first). D/A interface. Bit clock output.

FRDR DVSS1 TEST TES1 VC FE SE TE CE RFDC ADIO AVSS0 IGEN AVDD0 ASYO ASYI RFAC AVSS1 CLTV FILO FILI PCO AVDD1 BIAS VCTL

V16M VPCO

DVDD2 ASYE MD2 DOUT LRCK PCMD BCK

Pin No.

Symbol I/O Description

– 6 –

CXD3068Q

Notes)

• PCMD is a MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)

• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync

protection.

• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide.

• The GFS signal goes high when the frame sync and the insertion protection timing match.

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs. (during normal speed)

• C2PO represents the data error status.

• XROF is generated when the 32K RAM exceeds the ±28F jitter margin.

68

69 70 71 72

73 74 75 76 77 78 79 80

O

I

—

I

O O O O O

I I

O

I

1, 0

—

1, 0 1, 0 1, 0 1, 0

1, 0

Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis.

Crystal selection input. Low when the crystal is 16.9344MHz; high when it is

33.8688MHz. Digital GND. Crystal oscillation circuit input. When the master clock is input externally,

input it from this pin. Crystal oscillation circuit output. Serial data output in servo block. Serial data readout clock output in servo block. Serial data latch output in servo block. Sub-Q 80-bit, PCM peak or level data outputs. CD TEXT data output. SQSO readout clock input. GRSCOR resynchronization input. Sub-Q P to W serial output. SBSO readout clock input.

EMPH

XTSL DVSS2 XTAI XTAO

SOUT SOCK XOLT SQSO SQCK SCSY SBSO EXCK

Combination of Monitor Pin Outputs

Command bit

Output data

MTSL1

MTSL0

XUGF

XPCK

GFS

C2PO

MNT0

MNT1

MNT2

MNT3

RFCK

XPCK

XROF

GTOP

0 0 1

0 1 0

No.

Symbol I/O Description

– 7 –

CXD3068Q

Electrical Characteristics

1. DC Characteristics

(VDD = AVDD = 3.3 ± 0.3V, Vss = AVss = 0V, Topr = –20 to +75°C)

Item

High level Low level High level Low level High level Low level

High level Low level High level Low level

Input voltage (1)

Input voltage (2)

Input voltage (3)

Input voltage (4)

Output voltage (1)

Output voltage (2)

Input leak current (1) Input leak current (2) Input leak current (3)

Input leak current (4)

Tri-state pin output leak current

VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VIN4 VOH1 VOL1 VOH2 VOL2

ILI1 ILI2 ILI3

ILI4

ILO

0.7VDD

0.8VDD

VSS

VDD – 0.4

0

VDD – 0.5

0 –10 –10 –40

–40

0.2VDD

0.2VDD VDD VDD

0.4

VDD

0.4 10 10 40

40

V V V V V V V V V V

V µA µA µA

µA

Conditions Min. Typ.

Max.

Unit

Applicable pins

VI ≤ 5.5V

VI ≤ 5.5V Schmitt input

Analog input IOH = –4mA

IOL = 4mA IOH = –0.28mA

IOH = 0.36mA VI = Vss or

VDD VI = 0 to 5.5V VI = Vss or

VDD VI = 0.25VDD

to 0.75VDD VI = Vss or

VDD

∗1, ∗9

∗2

∗3

∗4, ∗5 ∗6, ∗8,

∗9

∗7

∗1, ∗4 ∗2, ∗3 ∗9

∗5

∗8

1-1. Applicable pins and classification

∗1

CMOS level input pins:

TEST, TES1

∗2

CMOS level input pins:

MUTE, SCSY, PWMI, DATA, XLAT, SSTP, XTSL

∗3

CMOS Schmitt input pins:

ASYE, EXCK, V16M, SQCK, XRST, CLOK, SCLK

∗4

Analog input pins (1):

VCTL, ASYI, CLTV, FILI

∗5

Analog input pins (2):

VC, FE, SE, TE, CE, RFDC

∗6

Normal output pins (1):

V16M, SBSO, C4M, WDCK, FSTO, SOUT, SOCK, XOLT, SQSO, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, SFDR, SRDR, TFDR, TRDR, FRDR, ASYO, DOUT, LRCK, PCMD, BCK, EMPH

∗7

Normal output pin (2):

FILO

∗8

Tri-state output pins:

VPCO, SENS, MDP, FFDR, PCO

∗9

Normal input/output pins:

ATSK, COUT, MIRR, DFCT, FOK, LOCK

Note) When the external pull-down resistors are connected to the pins ∗2and ∗3, the resistance applied to

these pins should be 5kΩ or less in total.

– 8 –

CXD3068Q

2. AC Characteristics

(1) XTAI pin

(a) When using self-excited oscillation

(VDD = AVDD = 3.3 ± 0.3V, Topr = –20 to +75°C)

(b) When inputting pulses to XTAI pin

(VDD = AVDD = 3.3 ± 0.3V, Topr = –20 to +75°C)

(c) When inputting sine waves to XTAI pin via a capacitor

(VDD = AVDD = 3.3 ± 0.3V, Topr = –20 to +75°C)

Oscillation frequency

fMAX 7

34 MHz

Item Symbol

Min. Typ. Max. Unit

High level pulse width

tWHX 13 500

ns

Low level pulse width

tWLX 13 500

ns

Pulse cycle tCX 26

1000

ns

Input high level

VIHX

VDD – 1.0

V

Input low level

VILX 0.8 V

Rise time, fall time

tR, tF 10

ns

Item Symbol Min. Typ. Max. Unit

Input amplitude VI 2.0 VDD + 0.3

Vp-p

Item Symbol Min.

Typ. Max. Unit

tR tF

tWHX

tWLX

tCX

VILX

VIHX × 0.1

V

IHX × 0.9

V

IHX

XTAI

V

DD/2

– 9 –

CXD3068Q

(2) CLOK, DATA, XLAT, SQCK and EXCK pins

(VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width COUT frequency (for input)

∗

COUT pulse width (for input)

∗

fCK tWCK tSU tH tD tWL fT tWT fT tWT

750 300 300 300 750

750

Note)

7.5

0.65

Note)

65

MHz

ns ns ns ns ns

MHz

ns

kHz

µs

Item Symbol Min. Typ. Max. Unit

∗

Only when $44 and $45 are executed.

tWCK tWCK

1/fCK

tH

tSU

tWL

tD

1/fT

tWT

tH

tSU

CLOK

DATA

XLAT

EXCK SQCK COUT

SBSO

SQSO

Note) In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCK maximum

operating frequency is 300kHz and its minimum pulse width is 1.5µs.

– 10 –

CXD3068Q

(4) COUT, MIRR and DFCT pins Operating frequency (VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)

COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency

fCOUT fMIRR fDFCTH

40 40

5

kHz kHz kHz

∗1 ∗2 ∗3

Signal

Symbol Min. Typ.

Max. Unit

Conditions

∗1

When using a high-speed traverse TZC.

∗2

When the RF signal continuously satisfies the following conditions during the above traverse.

• A = 0.11VDD to 0.23VDD

• ≤ 25%

∗3

During complete RF signal omission. When settings related to DFCT signal generation are Typ.

(3) SCLK pin

SCLK frequency SCLK pulse width Delay time

fSCLK tSPW tDLS

31.3 15

16 MHz

ns µs

Item

Symbol Min. Typ. Max.

Unit

B

A + B

tSPWtDLS

1/fSCLK

MSB LSB

· · ·

XLAT

SCLK

Serial Read Out Data

(SENS)

A

B

– 11 –

CXD3068Q

Contents [1] CPU Interface

§ 1-1. CPU Interface Timing.................................................................................................................... 12

§ 1-2. CPU Interface Command Table .................................................................................................... 12

§ 1-3. CPU Command Presets................................................................................................................ 23

§ 1-4. Description of SENS Signals......................................................................................................... 30

[2] Subcode Interface

§ 2-1. P to W Subcode Readout.............................................................................................................. 57

§ 2-2. 80-bit Sub-Q Readout.................................................................................................................... 57

[3] Description of Modes

§ 3-1. CLV-N Mode.................................................................................................................................. 64

§ 3-2. CLV-W Mode................................................................................................................................. 64

§ 3-3. CAV-W Mode................................................................................................................................. 64

§ 3-4. VCO-C mode................................................................................................................................. 65

[4] Description of Other Functions

§ 4-1. Channel Clock Regeneration by Digital PLL Circuit...................................................................... 68

§ 4-2. Frame Sync Protection.................................................................................................................. 70

§ 4-3. Error Correction............................................................................................................................. 70

§ 4-4. DA Interface................................................................................................................................... 71

§ 4-5. Digital Out...................................................................................................................................... 73

§ 4-6. Servo Auto Sequence.................................................................................................................... 74

§ 4-7. Digital CLV..................................................................................................................................... 82

§ 4-8. Playback Speed............................................................................................................................. 83

§ 4-9. Asymmetry Correction................................................................................................................... 84

§ 4-10. CD TEXT Data Demodulation ....................................................................................................... 85

[5] Description of Servo Signal Processing System Functions and Commands

§ 5-1. General Description of Servo Signal Processing System.............................................................. 87

§ 5-2. Digital Servo Block Master Clock (MCK)....................................................................................... 88

§ 5-3. DC Offset Cancel [AVRG Measurement and Compensation]....................................................... 89

§ 5-4. E: F Balance Adjustment Function................................................................................................ 90

§ 5-5. FCS Bias Adjustment Function...................................................................................................... 90

§ 5-6. AGCNTL Function......................................................................................................................... 92

§ 5-7. FCS Servo and FCS Search ......................................................................................................... 94

§ 5-8. TRK and SLD Servo Control ......................................................................................................... 95

§ 5-9. MIRR and DFCT Signal Generation.............................................................................................. 96

§ 5-10. DFCT Countermeasure Circuit ...................................................................................................... 97

§ 5-11. Anti-Shock Circuit .......................................................................................................................... 97

§ 5-12. Brake Circuit .................................................................................................................................. 98

§ 5-13. COUT Signal ................................................................................................................................. 99

§ 5-14. Serial Readout Circuit.................................................................................................................... 99

§ 5-15. Writing to Coefficient RAM ............................................................................................................ 100

§ 5-16. PWM Output .................................................................................................................................. 100

§ 5-17. Servo Status Changes Produced by LOCK Signal........................................................................ 101

§ 5-18. Description of Commands and Data Sets ..................................................................................... 101

§ 5-19. List of Servo Filter Coefficients...................................................................................................... 124

§ 5-20. Filter Composition.......................................................................................................................... 126

§ 5-21. TRACKING and FOCUS Frequency Response ............................................................................ 132

[6] Application Circuit .................................................................................................................................. 133

Explanation of abbreviations AVRG: Average

AGCNTL: Auto gain control FCS: Focus TRK: Tracking SLD: Sled DFCT: Defect

– 12 –

CXD3068Q

[1] CPU Interface

§ 1-1. CPU Interface Timing

• CPU interface

This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below.

• The internal registers are initialized by a reset when XRST = 0. Note) Be sure to set SQCK to high when XLAT is low.

§ 1-2. CPU Interface Command Table

Total bit length for each register

Register

0 to 2

3

4 to 6

7 8 9 A B C D E

8 bits

8 to 24 bits

16 bits 20 bits 28 bits 28 bits 28 bits 24 bits 28 bits 20 bits 20 bits

Total bit length

750ns or more

D18 D19 D20 D21 D22 D23

750ns or more

Valid

CLOK

DATA

XLAT

Registers

D0 D1

– 13 –

CXD3068Q

FOCUS SERVO ON

(FOCUS GAIN NORMAL)

FOCUS SERVO ON

(FOCUS GAIN DOWN)

FOCUS SERVO OFF,

0V OUT

FOCUS SERVO OFF, FOCUS

SEARCH VOLTAGE OUT

FOCUS SEARCH

VOLTAGE DOWN

FOCUS SEACH

VOLTAGE UP

ANTI SHOCK ON

ANTI SHOCK OFF

BRAKE ON

BRAKE OFF

TRACKING GAIN NORMAL

TRACKING GAIN UP

FILTER SELECT 1

TRACKING GAIN UP

FILTER SELECT 2

1

0

1

0

—

0

1

—

0

—

1

0

—

0

1

—

0

1

—

0

1

—

1

0

—

0

1

0 0 0 0

0 0 0 1

FOCUS

CONTROL

TRACKING

CONTROL

Reg-

ister

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Command Table ($0X to 1X)

—: Don't care

– 14 –

CXD3068Q

TRACKING SERVO OFF

TRACKING SERVO ON

FORWARD TRACK JUMP

REVERSE TRACK JUMP

SLED SERVO OFF

SLED SERVO ON

FORWARD SLED MOVE

REVERSE SLED MOVE

SLED KICK LEVEL

(±1 × basic value) (Default)

SLED KICK LEVEL

(±2 × basic value)

SLED KICK LEVEL

(±3 × basic value)

SLED KICK LEVEL

(±4 × basic value)

0

1

—

0

1

0

1

0

1

—

0

1

0

1

—

0

1

—

0

1

0

1

—

2

3

0 0 1 0

0 0 1 1

TRACKING

MODE

SELECT

Reg-

ister

Command

Address

D23 to D20

Reg-

ister

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

—: Don't care

Command Table ($2X to 3X)

– 15 –

CXD3068Q

KRAM DATA (K00)

SLED INPUT GAIN

KRAM DATA (K01)

SLED LOW BOOST FILTER A-H

KRAM DATA (K02)

SLED LOW BOOST FILTER A-L

KRAM DATA (K03)

SLED LOW BOOST FILTER B-H

KRAM DATA (K04)

SLED LOW BOOST FILTER B-L

KRAM DATA (K05)

SLED OUTPUT GAIN

KRAM DATA (K06)

FOCUS INPUT GAIN

KRAM DATA (K07)

SLED AUTO GAIN

KRAM DATA (K08)

FOCUS HIGH CUT FILTER A

KRAM DATA (K09)

FOCUS HIGH CUT FILTER B

KRAM DATA (K0A)

FOCUS LOW BOOST FILTER A-H

KRAM DATA (K0B)

FOCUS LOW BOOST FILTER A-L

KRAM DATA (K0C)

FOCUS LOW BOOST FILTER B-H

KRAM DATA (K0D)

FOCUS LOW BOOST FILTER B-L

KRAM DATA (K0E)

FOCUS PHASE COMPENSATE FILTER A

KRAM DATA (K0F)

FOCUS DEFECT HOLD GAIN

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 0 0SELECT

Reg-

ister

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($340X)

– 16 –

CXD3068Q

KRAM DATA (K10)

FOCUS PHASE COMPENSATE FILTER B

KRAM DATA (K11)

FOCUS OUTPUT GAIN

KRAM DATA (K12)

ANTI SHOCK INPUT GAIN

KRAM DATA (K13)

FOCUS AUTO GAIN

KRAM DATA (K14)

HPTZC / AUTO GAIN HIGH PASS FILTER A

KRAM DATA (K15)

HPTZC / AUTO GAIN HIGH PASS FILTER B

KRAM DATA (K16)

ANTI SHOCK HIGH PASS FILTER A

KRAM DATA (K17)

HPTZC / AUTO GAIN LOW PASS FILTER B

KRAM DATA (K18)

FIX

KRAM DATA (K19)

TRACKING INPUT GAIN

KRAM DATA (K1A)

TRACKING HIGH CUT FILTER A

KRAM DATA (K1B)

TRACKING HIGH CUT FILTER B

KRAM DATA (K1C)

TRACKING LOW BOOST FILTER A-H

KRAM DATA (K1D)

TRACKING LOW BOOST FILTER A-L

KRAM DATA (K1E)

TRACKING LOW BOOST FILTER B-H

KRAM DATA (K1F)

TRACKING LOW BOOST FILTER B-L

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 0 1SELECT

Reg-

ister

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($341X)

– 17 –

CXD3068Q

KRAM DATA (K20)

TRACKING PHASE COMPENSATE FILTER A

KRAM DATA (K21)

TRACKING PHASE COMPENSATE FILTER B

KRAM DATA (K22)

TRACKING OUTPUT GAIN

KRAM DATA (K23)

TRACKING AUTO GAIN

KRAM DATA (K24)

FOCUS GAIN DOWN HIGH CUT FILTER A

KRAM DATA (K25)

FOCUS GAIN DOWN HIGH CUT FILTER B

KRAM DATA (K26)

FOCUS GAIN DOWN LOW BOOST FILTER A-H

KRAM DATA (K27)

FOCUS GAIN DOWN LOW BOOST FILTER A-L

KRAM DATA (K28)

FOCUS GAIN DOWN LOW BOOST FILTER B-H

KRAM DATA (K29)

FOCUS GAIN DOWN LOW BOOST FILTER B-L

KRAM DATA (K2A)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER A

KRAM DATA (K2B)

FOCUS GAIN DOWN DEFECT HOLD GAIN

KRAM DATA (K2C)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER B

KRAM DATA (K2D)

FOCUS GAIN DOWN OUTPUT GAIN

KRAM DATA (K2E)

Not used

KRAM DATA (K2F)

Not used

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 1 0SELECT

Reg-

ister

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($342X)

– 18 –

CXD3068Q

KRAM DATA (K30)

SLED INPUT GAIN (when TGup2 is accessed with SFSK = 1)

KRAM DATA (K31)

ANTI SHOCK LOW PASS FILTER B

KRAM DATA (K32)

Not used

KRAM DATA (K33)

ANTI SHOCK HIGH PASS FILTER B-H

KRAM DATA (K34)

ANTI SHOCK HIGH PASS FILTER B-L

KRAM DATA (K35)

ANTI SHOCK FILTER COMPARATE GAIN

KRAM DATA (K36)

TRACKING GAIN UP2 HIGH CUT FILTER A

KRAM DATA (K37)

TRACKING GAIN UP2 HIGH CUT FILTER B

KRAM DATA (K38)

TRACKING GAIN UP2 LOW BOOST FILTER A-H

KRAM DATA (K39)

TRACKING GAIN UP2 LOW BOOST FILTER A-L

KRAM DATA (K3A)

TRACKING GAIN UP2 LOW BOOST FILTER B-H

KRAM DATA (K3B)

TRACKING GAIN UP2 LOW BOOST FILTER B-L

KRAM DATA (K3C)

TRACKING GAIN UP PHASE COMPENSATE FILTER A

KRAM DATA (K3D)

TRACKING GAIN UP PHASE COMPENSATE FILTER B

KRAM DATA (K3E)

TRACKING GAIN UP OUTPUT GAIN

KRAM DATA (K3F)

Not used

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 1 1SELECT

Reg-

ister

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($343X)

– 19 –

CXD3068Q

KRAM DATA (K40)

TRACKING HOLD FILTER INPUT GAIN

KRAM DATA (K41)

TRACKING HOLD FILTER A-H

KRAM DATA (K42)

TRACKING HOLD FILTER A-L

KRAM DATA (K43)

TRACKING HOLD FILTER B-H

KRAM DATA (K44)

TRACKING HOLD FILTER B-L

KRAM DATA (K45)

TRACKING HOLD FILTER OUTPUT GAIN

KRAM DATA (K46)

TRACKING HOLD INPUT GAIN

(when TGup2 is accessed with THSK = 1)

KRAM DATA (K47)

Not used

KRAM DATA (K48)

FOCUS HOLD FILTER INPUT GAIN

KRAM DATA (K49)

FOCUS HOLD FILTER A-H

KRAM DATA (K4A)

FOCUS HOLD FILTER A-L

KRAM DATA (K4B)

FOCUS HOLD FILTER B-H

KRAM DATA (K4C)

FOCUS HOLD FILTER B-L

KRAM DATA (K4D)

FOCUS HOLD FILTER OUTPUT GAIN

KRAM DATA (K4E)

Not used

KRAM DATA (K4F)

Not used

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3

0 0 1 1 0 1 0 0

0 1 0 0

SELECT

Reg-

ister

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($344X)

– 20 –

CXD3068Q

Command Table ($348X to 34FX)

—: Don't care

0

1

0

PGFS, PFOK, RFAC

Booster Surf Brake

Booster

FCS Bias Limit

FCS Bias Data

Traverse Center Data

3

1

0

1

0

1

0

1

0

1

0

1

0

1

PGFS1

SFBK1

THBON

0

IDFSL3

1

0

PGFS0

SFBK2

FHBON

0

IDFSL2

0

1

0

PFOK1

0

TLB1ON

0

IDFSL1

FBL9

FB9

TV9

PFOK0

0

FLB1ON

0

IDFSL0

FBL8

FB8

TV8

0

TLB2ON

0

FBL7

FB7

TV7

0

FBL6

FB6

TV6

0

HBST1

0

IDFT1

FBL5

FB5

TV5

MRS

0

HBST0

0

IDFT0

FBL4

FB4

TV4

MRT1

0

LB1S1

0

FBL3

FB3

TV3

MRT0

0

LB1S0

0

FBL2

FB2

TV2

0

LB2S1

0

FBL1

FB1

TV1

0

LB2S0

0

—

TV0

SELECT

Reg-

ister

Command

Address 1

D23 to D20

D19

D18 D17 D16

Address 2

D15

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2

Data 3Data 2Data 1Address 2

D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

0 0 1 1

– 21 –

CXD3068Q

0 0 1 1

1

0

1

0

1

System GAIN

FOCUS SEARCH SPEED/

VOLTAGE/AUTO GAIN

DTZC/TRACK JUMP

VOLTAGE/AUTO GAIN

FZSL/SLED MOVE/

Voltage/AUTO GAIN

LEVEL/AUTO GAIN/

DFSW/ (Initialize)

SERIAL DATA READ

MODE/SELECT

FOCUS BIAS

Operation for MIRR/

DFCT/FOK

TZC/COUT

BOTTOM/MIRR

SLED FILTER

Filter

Others

3

0 0 1 1

1

1 1 1

0 0

0

SYG3 SYG2

SYG1 SYG0

FI

FZB3

FI

FZB2

FI

FZB1

FI

FZB0

FI

FZA3

FI

FZA2

FI

FZA1

FI

FZA0

0

1

0

1

0

1

0

1

0

1

0

1

SELECT

Register

Command

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15 D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

Address

D23 to D20 D19 D18 D17 D16

Data 1

D15 D14 D13 D12

Data 2

D11 D10 D9 D8

Data 3

D7 D6 D5 D4

Data 4

D3 D2 D1 D0

Command Table ($35X to 3FX)

FT1

TDZC

FZSH

VCLM

DAC

0

SFO2

COSS

SFID

F1NM

0

FT0

DTZC

FZSL

VCLC

SD6

FBON

SFO1

COTS

SFSK

F1DM

AGC4

FS5

TJ5

SM5

FLM

SD5

FBSS

SDF2

CETZ

THID

F3NM

XT4D

FS4

TJ4

SM4

FLC0

SD4

FBUP

SDF1

CETF

THSK

F3DM

XT2D

FS3

TJ3

SM3

RFLM

SD3

FBV1

MAX2

COT2

0

TINM

0

FS2

TJ2

SM2

RFLC

SD2

FBV0

MAX1

COT1

TLD2

TIUM

DRR2

FS1

TJ1

SM1

AGF

SD1

FIFZC

SFOX

MOT2

TLD1

T3NM

DRR1

FS0

TJ0

SM0

AGT

SD0

TJD0

BTF

0

TLD0

T3UM

DRR0

FTZ

SFJP

AGS

DFSW

0

FPS1

D2V2

BTS1

0

DF1S

0

FG6

TG6

AGJ

LKSW

0

FPS0

D2V1

BTS0

0

TLCD

ASFG

FG5

TG5

AGGF

TBLM

0

TPS1

D1V2

MRC1

0

FTQ

FG4

TG4

AGGT

TCLM

0

TPS0

D1V1

MRC0

0

LKIN

1

FG3

TG3

AGV1

FLC1

0

RINT

0

COIN

0

FG2

TG2

AGV2

TLC2

0

SJHD

0

MDFI

0

FG1

TG1

AGHS

TLC1

0

INBK

0

MIRI

AGHF

FG0

TG0

AGHT

TLC0

0

MTI0

0

XT1D

ASOT

– 22 –

CXD3068Q

Auto sequence

Blind (A, E),

Brake (B),

Overflow (C, G)

Sled KICK,

BRAKE (D),

KICK (F)

Auto sequence (N)

track jump count

setting

MODE

specification

Function

specification

Audio CTRL

EFM playability

reinforcement

setting

Sync expanding

specification

Sleep setting

Variable pitch

Traverse monitor

counter setting

Spindle servo

coefficient setting

CLV CTRL

SPD mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

AS3

TR3

SD3

32768

CD-

ROM

1

0

1

32768

Gain

MDP1

0

CM3

AS2

TR2

SD2

16384

DOUT

Mute

DSPB

ON/OFF

0

1

16384

Gain

MDP0

TB

CM2

AS1

TR1

SD1

8192

DOUT

Mute-F

ASEQ

ON/OFF

Mute

1

0

1

8192

Gain

MDS1

TP

CM1

AS0

TR0

SD0

4096

WSEL

1

ATT

1

0

1

0

4096

Gain

MDS0

CLVS

Gain

CM0

MT3

0

KF3

2048

VCO

SEL1

BiliGL

MAIN

PCT1

ARDTEN

AVW

ADCPS

VARI

ON

2048

Gain

DCLV1

VP7

EPWM

MT2

0

KF2

1024

ASHS

BiliGL

SUB

PCT2

1

0

DSP

SLEEP

VARI

USE

1024

Gain

DCLV0

VP6

SPDC

MT1

0

KF1

512

SOCT0

FLFC

0

1

SFP5

DSSP

SLEEP

0

512

PCC1

VP5

ICAP

MT0

0

KF0

256

VCO

SEL2

1

SOC2

1

SFP4

ASYM

SLEEP

0

256

PCC0

VP4

SFSL

LSSL

0

128

KSL3

0

1

SFP3

—

128

SFP3

VP3

VC2C

0

64

KSL2

0

SFP2

—

64

SFP2

VP2

HIFC

0

32

KSL1

0

1

SFP1

—

32

SFP1

VP1

LPWR

0

16

KSL0

0

SFP0

—

16

SFP0

VP0

VPON

—

8

0

1

0

—

8

SRP3

VP

CTL1

Gain

CAV1

—

4

VCO1

CS0

0

1

0

—

4

SRP2

VP

CTL0

Gain

CAV0

—

2

XVCO2

THRU

0

1

—

1

SRP1

0

—

1

0

1

0

—

1

SRP0

0

INV

VPCO

4

5

6

7

8

9

A

B

C

D

E

Reg-

ister

Command

Address

D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8

Data 1 Data 2 Data 3 Data 4

Command Table ($4X to EX)

—: Don't care

– 23 –

CXD3068Q

FOCUS SERVO OFF,

0V OUT

TRACKING GAIN UP

FILTER SELECT 1

TRACKING SERVO OFF

SLED SERVO OFF

SLED KICK LEVEL

(±1 × basic value) (Default)

KRAM DATA

($3400XX to $344fXX)

0

1

0

—

0

1

2

0 0 0 0

0 0 0 1

0 0 1 0

FOCUS

CONTROL

TRACKING

CONTROL

TRACKING

MODE

Reg-

ister

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Reg-

ister

Command

3 SELECT

Address

D23 to D20

0 0 1 1

0 0 1 1 0 1 0 0 0 See "Coefficient ROM Preset Values Table".

0 0 0 0 — — — — — — — — — — — — — — — —

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D0 D0

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15 D14 D13 D12

Address 3

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D0 D0

§ 1-3. CPU Command Presets

Command Preset Table ($0X to 34X)

—: Don't care

Command Table ($4X to EX) cont.

MODE

specification

1 0 0 0 ERC4

SCOR

SEL

SCSY SOCT1 TXON

TXOUT OUTL1 OUTL0

8

Function

specification

Audio CTRL

EFM playability

reinforcement setting

Traverse monitor

counter setting

Spindle servo

coefficient setting

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

0 0 ∗ ∗

1 0 1 1

0

1

0

EDC7

0

EDC6

0

MTSL1

EDC5

0

MTSL0

EDC4

0

—

EDC3

0

—

EDC2

0

—

EDC1

0

—

EDC0

9

A

B

C

Reg-

ister

Command

Address Data 1 Data 2 Data 3 Data 4

D7 D6 D5 D4 D3 D2 D1 D0

Data 5 Data 6

— — — —

—

1

—

0

—

0

—

0

—

D3 D2 D1 D0

Data 7

– 24 –

CXD3068Q

Command Preset Table ($348X to 34FX)

0010

PGFS, PFOK, RFAC

Booster Surf Brake

Booster

FCS Bias Limit

FCS Bias Data

Traverse Center Data

3

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

SELECT

Reg-

ister

Command

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2

Data 3Data 2Data 1Address 2

D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

0 0 1 1

– 25 –

CXD3068Q

Command Preset Table ($35X to 3FX)

0 0 1 1

1

0

1

0

1

System GAIN

FOCUS SEARCH SPEED/

VOLTAGE/AUTO GAIN

DTZC/TRACK JUMP

VOLTAGE/AUTO GAIN

FZSL/SLED MOVE/

Voltage/AUTO GAIN

LEVEL/AUTO GAIN/

DFSW/ (Initialize)

SERIAL DATA READ

MODE/SELECT

FOCUS BIAS

Operation for MIRR/

DFCT/FOK

TZC/COUT

BOTTOM/MIRR

SLED FILTER

Filter

Others

3

0 0 1 1

1

1 1 1

0 0

0

1 0

0 0 0 0 0 0

0

0 0 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

SELECT

Register

Command

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15 D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

Address

D23 to D20 D19 D18 D17 D16

Data 1

D15 D14 D13 D12

Data 2

D11 D10 D9 D8

Data 3

D7 D6 D5 D4

Data 4

D3 D2 D1 D0

– 26 –

CXD3068Q

Auto sequence

Blind (A, E),

Brake (B),

Overflow (C, G)

Sled KICK,

BRAKE (D),

KICK (F)

Auto sequence

(N) track jump

count setting

MODE

specification

Function

specification

Audio CTRL

EFM playability

reinforcement setting

Sync expanding

specification

Sleep setting

Variable pitch

Traverse monitor

counter setting

Spindle servo

coefficient setting

CLV CTRL

SPD mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

—

0

1

0

1

—

0

1

0

1

0

—

0

—

0

—

0

1

0

—

0

—

0

1

0

—

0

—

0

1

—

0

1

0

—

0

1

0

—

0

1

0

4

5

6

7

8

9

A

B

C

D

E

Reg-

ister

Command

Address

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Data 1 Data 2 Data 3 Data 4

Command Preset Table ($4X to EX)

—: Don't care

– 27 –

CXD3068Q

Command Preset Table ($4X to EX)

—: Don't care

MODE

specification

1 0 0 0 0 0 0 0 0 0 0 08

Function

specification

Audio CTRL

EFM playability

reinforcement setting

Traverse monitor

counter setting

Spindle servo

coefficient setting

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

0 0 ∗ ∗

1 0 1 1

0

1

0

—

0

—

0

—

0

—

0

—

1

—

0

—

0

—

0

—

9

A

B

C

Reg-

ister

Command

Address Data 1 Data 2

Data 3

Data 4

D3 D2 D1 D0 D3 D2 D1 D0

D3 D2 D1 D0

Data 5 Data 6

Data 7

– 28 –

CXD3068Q

ADDRESS

K00 K01 K02 K03 K04 K05 K06 K07 K08

K09 K0A K0B K0C K0D K0E

K0F

E0 81 23 7F 6A 10 14 30 7F 46 81 1C 7F 58 82 7F

SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19 K1A K1B K1C K1D K1E

K1F

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29 K2A K2B K2C K2D K2E

K2F

4E 32 20 30 80 77 80 77 00 F1 7F 3B 81 44 7F 5E

FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix

∗

TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L

82 44 18 30 7F 46 81 3A 7F 66 82 44 4E 1B 00 00

TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN Not used Not used

DATA CONTENTS

∗

Fix indicates that normal preset values should be used.

– 29 –

CXD3068Q

ADDRESS

K30 K31 K32 K33 K34 K35 K36 K37 K38 K39

K3A K3B K3C K3D K3E K3F

80 66 00 7F

6E

20 7F

3B

80 44 7F 77 86

0D

57 00

SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B Not used ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B TRACKING GAIN UP2 LOW BOOST FILTER A-H TRACKING GAIN UP2 LOW BOOST FILTER A-L TRACKING GAIN UP2 LOW BOOST FILTER B-H TRACKING GAIN UP2 LOW BOOST FILTER B-L TRACKING GAIN UP PHASE COMPENSATE FILTER A TRACKING GAIN UP PHASE COMPENSATE FILTER B TRACKING GAIN UP OUTPUT GAIN Not used

K40 K41 K42 K43 K44 K45 K46

K47 K48 K49 K4A K4B K4C K4D K4E K4F

04 7F 7F 79 17

6D

00 00

02 7F 7F 79 17 54 00 00

TRACKING HOLD FILTER INPUT GAIN TRACKING HOLD FILTER A-H TRACKING HOLD FILTER A-L TRACKING HOLD FILTER B-H TRACKING HOLD FILTER B-L TRACKING HOLD FILTER OUTPUT GAIN TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is accessed with THSK = 1.) Not used FOCUS HOLD FILTER INPUT GAIN FOCUS HOLD FILTER A-H FOCUS HOLD FILTER A-L FOCUS HOLD FILTER B-H FOCUS HOLD FILTER B-L FOCUS HOLD FILTER OUTPUT GAIN Not used Not used

DATA CONTENTS

– 30 –

CXD3068Q

§ 1-4. Description of SENS Signals

SENS output

Microcomputer

serial register

(latching not required)

$0X $1X $2X $30 to 37 $38 $38 $3904 $3908 $390C $391C $391D $391F $3A $3B to 3F $4X $5X $6X $AX $BX $CX $EX $7X, 8X, 9X,

DX, FX

Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z

GFS COMP COUT

OV64

Z

FZC

AS (Anti Shock)

TZC

SSTP

AGOK

∗

XAVEBSY

∗

TE Avrg Reg. FE Avrg Reg.

VC Avrg Reg.

TRVSC Reg.

FB Reg.

RFDC Avrg Reg.

FBIAS Count STOP

SSTP

XBUSY

FOK

0

GFS COMP COUT

OV64

0

— — — — —

— 9 bits 9 bits 9 bits 9 bits 9 bits 8 bits

—

ASEQ = 0 ASEQ = 1 Output data length

∗

$38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases.

– 31 –

CXD3068Q

Description of SENS Signals

The SENS pin is high impedance. Low while the auto sequencer is in operation, high when operation terminates. Outputs the same signal as the FOK pin.

High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks set with $B.

High when Reg.B is latched, low when the initial $B number is counted through COUT. Counts the number of tracks set with $B.

High when $B is latched, toggles each time the $B number is counted through COUT. While $44 and $45 are being executed, toggles with each COUT 8-count instead of the $B number.

Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter.

Z XBUSY

FOK GFS COMP

COUT

OV64

SENS output

– 32 –

CXD3068Q

The meaning of the data for each address is explained below.

$4X commands

Register name

4

Data 1

Command

Data 2

MAX timer value

Data 3

Timer range

AS3 AS2 AS1 AS0 MT3 MT2 MT1 MT0 LSSL 0 0 0

Command Cancel Fine Search Focus-On 1 Track Jump 10 Track Jump 2N Track Jump M Track Move

0 0 0 1 1 1 1

0 1 1 0 0 1 1

0 0 1 0 1 0 1

0

RXF

1 RXF RXF RXF RXF

AS3 AS2 AS1 AS0

RXF = 0 Forward

RXF = 1 Reverse

• When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.

• When the Track jump commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence

is interrupted.

• To disable the MAX timer, set the MAX timer value to 0.

$5X commands

MAX timer value

MT3

23.2ms

1.49s

11.6ms

0.74s

5.8ms

0.37s

2.9ms

0.18s

0 1

0 0

MT2 MT1 MT0 LSSL 0 0 0

Timer range

Timer TR3 TR2 TR1

TR0 Blind (A, E), Overflow (C, G) Brake (B)

0.18ms

0.36ms

0.09ms

0.18ms

0.045ms

0.09ms

0.022ms

0.045ms

– 33 –

CXD3068Q

Command

Data 1 Data 2

Data 3 Data 4

D3 D2 D1 D0

D3 D2 D1 D0 D3 D2

D1 D0

D3 D2 D1 D0

2152142132122112102928272625242322212

0

Auto sequence track jump count setting

This command is used to set N when a 2N-track jump is executed, to set M when an M-track move is executed and to set the jump count when fine search is executed for auto sequencer.

• The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system.

• When the track jump count is from 0 to 15, the COUT signal is counted for 2N-track jumps and M-track moves; when the count is 16 or over, the MIRR signal is counted. For fine search, the COUT signal is counted.

$7X commands

Auto sequencer track jump count setting

$6X commands

Register name

6

Data 1

KICK (D)

Data 2

KICK (F)

SD3

SD2 SD1 SD0 KF3

KF2 KF1 KF0

Timer SD3 SD2 SD1 SD0 When executing KICK (D) $44 or $45 When executing KICK (D) $4C or $4D

23.2ms

11.6ms

5.8ms

2.9ms

1.45ms

Timer KF3 KF2 KF1 KF0

KICK (F) 0.72ms 0.36ms 0.18ms

0.09ms

– 34 –

CXD3068Q

∗

See mute conditions (1), (2), and (4) to (6) under $AX commands for other mute conditions.

MD2

Other mute conditions

∗

DOUT Mute

D.out Mute F

DOUT output

OFF

0dB

–∞dB

DA output for 48-bit slot

0dB

–∞dB

0dB

–∞dB

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Command

Data 1

MODE specification

CD-

ROM

DOUT

Mute

DOUT

Mute-F

WSEL

D23

D22 D21 D20

Data 2

VCO

SEL1

ASHS SOCT0

VCO

SEL2

D19 D18 D17 D16

$8X commands

Command bit DOUT Mute = 1 DOUT Mute = 0

When Digital Out is on (MD2 pin = 1), DOUT output is muted. When Digital Out is on, DOUT output is not muted.

Processing

Command bit

D. out Mute F = 1 D. out Mute F = 0

When Digital Out is on (MD2 pin = 1), DA output is muted. DA output mute is not affected when Digital Out is either on or off.

Processing

Command bit

CDROM = 1 CDROM = 0

C2PO timing

1-3 1-3

CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed.

Processing

– 35 –

CXD3068Q

Command bit

Processing VCOSEL1 = 0 VCOSEL1 = 1

Multiplier PLL VCO1 is set to normal speed. Multiplier PLL VCO1 is set to approximately twice the normal speed.

Command bit

KSL3 KSL2

Processing

Output of multiplier PLL VCO1 is 1/1 frequency-divided. Output of multiplier PLL VCO1 is 1/2 frequency-divided. Output of multiplier PLL VCO1 is 1/4 frequency-divided. Output of multiplier PLL VCO1 is 1/8 frequency-divided.

0 0 1 1

0 1 0 1

See the previous page.

Command

Data 2

MODE specification

VCO

SEL1

ASHS SOCT0

VCO

SEL2

D3 D2 D1 D0

Data 3

KSL3 KSL2 KSL1 KSL0

D3 D2 D1 D0

Command bit

Sync protection window width WSEL = 1 WSEL = 0

±26 channel clock

±6 channel clock

Anti-rolling is enhanced. Sync window protection is enhanced.

Application

∗

In normal-speed playback, channel clock = 4.3218MHz.

Command bit

Function ASHS = 0 ASHS = 1

The command transfer rate to DSSP block from auto sequencer is set to normal speed. The command transfer rate to DSSP block from auto sequencer is set to half speed.

∗

See "§ 4-8. Playback Speed" for settings.

Command bit

SOCT0 SOCT1

Processing

Sub-Q is output from the SQSO pin. Each signal is output from the SQSO pin. Input the readout clock to SQCK.

(See Timing Chart 2-4.) The error rate is output from the SQSO pin. Input the readout clock to SQCK.

(See Timing Chart 2-6.)

0 1

1

—

0

1

—: Don't care

– 36 –

CXD3068Q

Command bit

Processing VCOSEL2 = 0 VCOSEL2 = 1

Wide-band PLL VCO2 is set to normal speed. Wide-band PLL VCO2 is set to approximately twice the normal speed.

Command bit

KSL1 KSL0

Processing

Output of wide-band PLL VCO2 is 1/1 frequency-divided. Output of wide-band PLL VCO2 is 1/2 frequency-divided. Output of wide-band PLL VCO2 is 1/4 frequency-divided. Output of wide-band PLL VCO2 is 1/8 frequency-divided.

0 0 1 1

0 1 0 1

Command

D3

0 0

VCO2 THRU

0 ERC4

SCOR

SEL

SCSY SOCT1 TXON TXOUT OUTL1 OUTL0

D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Data 4 Data 5

Mode specification

Data 6

Command bit

VCO2 THRU = 0

Processing

V16M is output. The wide-band EFM PLL clock can be input from the V16M pin.

∗

These bits select the internal or external connection for the VCO2 used in CAV-W or variable pitch mode.

VCO2 THRU = 1

Command bit

ERC4 = 0

Processing

C2 error double correction is performed when DSPB = 1. C2 error quadruple correction is performed even when DSPB = 1.ERC4 = 1

Command bit

SCOR SEL = 0

Processing

WDCK signal is output. GRSCOR (protected SCOR) is output.

∗

Used when outputting GRSCOR from the WDCK pin.

SCOR SEL = 1

– 37 –

CXD3068Q

Command bit

TXON = 0

Processing

When CD TEXT data is not demodulated, set TXON to 0. When CD TEXT data is demodulated, set TXON to 1.

∗

See "$4-10. CD TEXT Data Demodulation"

TXON = 1

Command bit

SCSY = 0

Processing

No processing. GRSCOR (protected SCOR) synchronization is applied again.

∗

Used to resynchronize GRSCOR.

The rising edge signal of this commnd bit is used internally. Therefore, when resynchronizing GRSCOR, first return the setting to 0 and then set to 1. GRSCOR achieves the crystal accuracy by removing the jitter components included in the SCOR signal. This signal is synchronized with PCMDATA. The resynchronization conditions are when GTOP = high or when the SCSY pin = high. (same as when SCSY = 1 is sent by the $8X command.)

SCSY = 1

Command bit

TXOUT = 0

Processing

Various signals except for CD TEXT is output from the SQSO pin. CD TEXT data is output from the SQSO pin.

∗

See "$4-10. CD TEXT Data Demodulation"

TXOUT = 1

Command bit

OUTL1 = 0

Processing

WFCK, XPCK C4M, WDCK and FSTO are output. V16M is output when VCO2 THRU = 0.

WFCK, XPCK C4M, WDCK and FSTO outputs are set to low. The V16M output is low when VCO2 THRU = 0.

OUTL1 = 1

Command bit

OUTL0 = 0 OUTL0 = 1

Processing PCMD, BCK, LRCK and EMPH are output. PCMD, BCK, LRCK and EMPH outputs are low.

Command

Data 1

Function specification

1

DSPB

ON-OFF

A.SEQ

ON-OFF

1

D3 D2

D1 D0

Data 2

BiliGL MAIN

BiliGL

SUB

FLFC

D3

D2

D1

1

D0

$9X commands

Command bit

DSPB = 0 DSPB = 1

Normal-speed playback, C2 error quadruple correction. Double-speed playback, C2 error double correction. (quadruple correction when ERC4 =

1)

Processing

FLFC is normally 0. FLFC is 1 in CAV-W mode, for any playback speed.

Command bit BiliGL SUB = 0 BiliGL SUB = 1

STEREO

SUB

MAIN

Mute

BiliGL MAIN = 0 BiliGL MAIN = 1

Definition of bilingual capable MAIN, SUB and STEREO

The left channel input is output to the left and right channels for MAIN. The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output to the left and right channels for STEREO.

– 38 –

CXD3068Q

Command bit

VCO1CS0 = 0

Processing Multiplier PLL VCO1 low speed is selected. Multiplier PLL VCO1 high speed is selected.

∗

The CXD3068Q has two VCO1s, and this command selects one of these VCO1s.

VCO1CS0 = 1

Selector

1/2

1/1

1/8

1/4

Selector

To DSP interior

KSL3, 2VCO1CS0

Low-speed

VCO1

High-speed

VCO1

VCO1SEL1

∗

Block Diagram of VCO Internal Path

VCO1 Internal Path

– 39 –

CXD3068Q

Command

Data 1

Audio CTRL 0 0 Mute ATT

D3 D2 D1 D0

Data 2

PCT1 PCT2

D3 D2

0 SOC2

D1 D0

$AX commands

Command bit

Mute = 0 Mute = 1

Mute off if other mute conditions are not set.

Mute on. Peak register reset.

Meaning

Command bit

ATT = 0 ATT = 1

Attenuation off. –12dB

Meaning

Mute conditions

(1) When register A mute = 1. (2) When Mute pin = 1. (3) When register 8 D.out Mute F = 1 and the Digital Out is on (MD2 pin = 1). (4) When GFS stays low for over 35 ms (during normal-speed). (5) When register 9 BiliGL MAIN = Sub = 1. (6) When register A PCT1 = 1 and PCT2 = 0.

(1) to (4) perform zero-cross muting with a 1ms time limit.

Command bit

PCT1

0 0 1 1

PCT2

0 1 0 1

Normal mode Level meter mode Peak meter mode Normal mode

× 0dB × 0dB

Mute

× 0dB

C1: double; C2: quadruple C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double

Meaning PCM Gain ECC error correction ability

Description of level meter mode (see Timing Chart 1-4.)

• When the LSI is set to this mode, it performs digital level meter functions.

• When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO.

The initial 80 bits are Sub-Q data (see "§ 2. Subcode Interface"). The last 16 bits are LSB first, which are 15bit PCM data (absolute values) and an L/R flag. The L/R flag is high when the 15-bit PCM data is from the left channel and low when the data is from the right channel.

• The PCM data is reset and the L/R flag is reversed after one readout. Then maximum value measuring continues until the next readout.

– 40 –

CXD3068Q

Description of peak meter mode (see Timing Chart 1-5.)

• When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the

left or right channel. The 96-bit clock must be input to SQCK to read out this data.

• When the 96-bit clock is input, 96 bits of data are output to SQSO and the value is set in the LSI internal register again. In other words, the PCM maximum value detection register is not reset by the readout.

• To reset the PCM maximum value register to zero, set PCT1 = PCT2 = 0 or set the $AX mute.

• The Sub-Q absolute time is automatically controlled in this mode.

In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in the memory. Normal operation is conducted for the relative time.

• The final bit (L/R flag) of the 96-bit data is normally 0.

• The pre-value hold and average value interpolation data are fixed to level (–∞) for this mode.

SENS output switching

• This command enables the SQSO pin signal to be output from the SENS pin. When SOC2 = 0, SENS output is performed as usual. When SOC2 = 1, the SQSO pin signal is output from the SENS pin. At this time, the readout clock is input to the SCLK pin.

Note) SOC2 should be switched when SQCK = SCLK = high.

Command bit

SOC2 = 0 SOC2 = 1

The SENS signal is output from the SENS pin as usual. The SQSO pin signal is output from the SENS pin.

Processing

Processing Normal playback is performed. EFM playability reinforcement function is turned on.

Command

Data 3

Command bit

ARDTEN = 0 ARDTEN = 1

$AB commands (preset: $AB 7A2808)

Data 1

D3 D2 D1 D0

Data 2

D3 D2 D1 D0 D3 D2 D1 D0

Data 4

D3 D2 D1 D0

Data 5

D3 D2 D1 D0

Data 6

D3 D2 D1 D0

Data 7

D3 D2 D1 D0

EFM playability reinforcement function

Command

EFM playability reinforcement function

1 1 1

1

10

0 0 0 0

00 1 0

0

1 00

01 0

0

1 0

1 1

ARDTEN

Note) Set these command bits when the disc is not played back.

– 41 –

CXD3068Q

$AC commands (preset: $AC 0C)

Command

Data 1

D3

1 1

0

0 AVW

0 SFP5 SFP4

Sync expanding bit

D2 D1 D0 D3 D2 D1 D0

Data 2

SFP3

SFP2 SFP1 SFP0

D3 D2 D1 D0

Data 3

∗

See "§4-2. Frame Sync Protection" for the protection of the frame sync.

Note) This command bit register is shared with the $CX commands and the command bit set last is valid.

When the command bit is used in the existing state, set to the $CX commands. When the command bit is used with the $AC address, make the settings same as for SFP3 to SFP0 set with the $CX commands.

Command bit

SFP5 to 0 Sets the frame sync forward protection times. The setting range is 1F to 3F (Hex).

Processing

∗

During the period from 16th forward protection to the GFS rise, the sync protection window width (±6 channel clocks when WSEL = 0 and ±26 channel clocks when WSEL = 1) expands by 32 channel clocks whenever the inserted sync is generated. GTOP rises when the window width becomes maximum (in excess of 588 channel clocks).

Note) The sync forward protection times are not affected by SFP5 to SFP0.

Command bit

AVW = 0

Processing

Automatic expanding function of sync protection window width is turned off. Automatic expanding function of sync protection window width is turned on.AVW = 1

– 42 –

CXD3068Q

$AD commands (preset: $AD0)

Data 1

D31D21D10D01D3

ADCPS

D2

DSP

SLEEP

D1

DSSP

SLEEP

D0

ASYM

SLEEP

AD

(Sleep setting)

Data 2

Command

ADCPS: This bit sets the operating mode of the DSSP block A/D converter.

When 0, the operating mode of the DSSP block A/D converter is set to normal. (default) When 1, the operating mode of the DSSP block A/D converter is set to power saving.

DSP SLEEP: This bit sets the operating mode of the DSP block.

When 0, the DSP block operates normally. (default) When 1, the DSP block clock is stopped. This makes it possible to reduce power consumption.

DSSP SLEEP: This bit sets the operating mode of the DSSP block.

When 0, the DSSP block operates normally. (default) When 1, the DSSP block clock is stopped. In addition, the A/D converter and operational amplifier in the DSSP block are set to standby mode. This makes it possible to reduce power consumption.

ASYM SLEEP: This bit sets the operating mode of the asymmetry correction circuit and VCO1.

When 0, the asymmetry correction circuit and VCO1 operate normally. (default) When 1, the operational amplifier in the asymmetry correction circuit is set to standby mode. In addition, the multiplier PLL VCO1 oscillation is stopped. This makes it possible to reduce power consumption.

– 43 –

CXD3068Q

$BX commands

This command sets the traverse monitor count.

Command

Data 1 Data 2

Data 3 Data 4

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

2152142132122112102928272625242322212

0

Traverse monitor count setting

• When the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off.

• The traverse monitor count is set to monitor the traverse status from the SENS output as COMP and COUT.

Command bit

MTSL1 MTSL0

Output data

XUGF MNT0 RFCK

XPCK MNT1 XPCK

GFS MNT2 XROF

C2PO MNT3

GTOP

0 0 1

0 1 0

Command

Data 5

Traverse monitor count setting

0 0 MTSL1 MTSL0

D3 D2 D1 D0

This command sets the monitor output switching.

Command

Data 1

Audio CTRL 1 1 1 0

D3 D2 D1 D0

Data 2

VARI

ON

VARI

USE

D3 D2

0 0

D1 D0

$AE commands (preset: $AE 0)

Command bit

VARION = 0

Processing

Variable pitch mode is turned off. (The crystal is the reference to the internal clock.) Variable pitch mode is turned on. (The VCO2 is the reference to the internal clock.)VARION = 1

Command bit

VARIUSE = 0

Processing

When the variable pitch mode is not used, set VARIUSE to 0. When the variable pitch mode is used, set VAIRUSE to 1.

∗

See "$DX commands" for the variable range and the usage example of the variable pitch.

VARIUSE = 1

– 44 –

CXD3068Q

Spindle servo coefficient setting

CLV CTRL ($DX)

Gain

MDP1

Gain

MDP0

Gain

MDS1

Gain

MDS0

Gain

CLVS

Gain

MDS1

0 0 0 0 1 1

Gain

MDS0

0 0 1 1 0 0

Gain

CLVS

0 1 0 1 0 1

GCLVS

–12dB

–6dB –6dB

0dB 0dB

+6dB

Command

D3

Data 1

D2

D1

D0

Gain

DCLV0

Gain

DCLV1

PCC1

PCC0

D3

Data 2

D2

D1

D0

$CX commands

• CLVS mode gain setting: GCLVS

Gain

MDP1

0 0 1

Gain

MDP0

0 1 0

GMDP

–6dB

0dB

+6dB

Gain

DCLV1

0 0 1

Gain

DCLV0

0 1 0

GDCLV

0dB

+6dB

+12dB

Gain

MDS1

0 0 1

Gain

MDS0

0 1 0

GMDS

–6dB

0dB

+6dB

• CLVP mode gain setting: GMDP : GMDS

• DCLV overall gain setting: GDCLV

Command bit

PCC1 PCC0

Processing

The VPCO signal is output. The VPCO pin output is high impedance. The VPCO pin output is low. The VPCO pin output is high.

0 0 1 1

0 1 0 1

• This command controls the VPCO pin signal.

The VPCO output can be controlled with this setting.

– 45 –

CXD3068Q

Command

Data 3

D3

SFP3

SFP2

SFP1

SFP0

SRP3

SRP2 SRP1

SRP0

Spindle servo coefficient setting

D2 D1 D0 D3 D2 D1 D0

Data 4

∗

See "§ 4-2. Frame Sync Protection" regarding frame sync protection.

Command bit

SRP3 to 0 Sets the frame sync backward protection times. The setting range is 1 to F (Hex).

Processing

Command bit

SFP3 to 0 Sets the frame sync forward protection times. The setting range is 1 to F (Hex).

Processing

• The CXD3068Q can serially output the 40 bits (10 BCD codes) of error monitor data selected by EDC0 to 7 from the SQSO pin and monitor this data using a microcomputer. The C1 and C2 error rate settings are sent one at a time by the $C commands by setting $8 commands SOCT0 and SOCT1 = 1. Then, the data can be read out from the SQSO pin by sending 40 SQCK pulses.

$CX commands

Command

Data 5

D3

EDC7

EDC6

EDC5

EDC4 EDC3

EDC2

EDC1 EDC0

Spindle servo coefficient setting

D2 D1 D0 D3 D2 D1 D0

Data 6

– 46 –

CXD3068Q

Command bit

EDC7 = 0 EDC6

EDC5 EDC4 EDC3 EDC2 EDC1

EDC0

EDC7 = 1 EDC6

EDC5 EDC4 EDC3 EDC2 EDC1 EDC0

The [No C1 errors, pointer reset] count is output when 0. The [One C1 error corrected, pointer reset] count is output when 0. The [No C1 errors, pointer set] count is output when 0. The [One C1 error corrected, pointer set] count is output when 0. The [Two C1 errors corrected, pointer set] count is output when 0. The [C1 correction impossible, pointer set] count is output when 0. 7350 frame count cycle mode∗1when 1.

73500 frame count cycle mode∗2when 0. The [No C2 errors, pointer reset] count is output when 0. The [One C2 error corrected, pointer reset] count is output when 0. The [Two C2 errors corrected, pointer reset] count is output when 0. The [Three C2 errors corrected, pointer reset] count is output when 0. The [Four C2 errors corrected, pointer reset] count is output when 0. The [C2 correction impossible, pointer copy] count is output when 0. The [C2 correction impossible, pointer set] count is output when 0.

Processing

Error monitor commands

∗1

The number selected by C1 (EDC1 to 6) and C2 (EDC0 to 6) is added to C1 and C2 and output every 7350 frames.

∗2

The number selected by C1 (EDC1 to 6) and C2 (EDC0 to 6) is added to C1 and C2 and output every 73500 frames.

$DX commands

See "$CX commands".

Command bit

TB = 0 TB = 1 TP = 0 TP = 1

Bottom hold at a cycle of RFCK/32 in CLVS mode. Bottom hold at a cycle of RFCK/16 in CLVS mode. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode.

Description

Command

Data 1

CLV CTRL

0 TB TP

Gain

CLVS

D3 D2 D1 D0

– 47 –

CXD3068Q

The rotational velocity R of the spindle can be expressed with the following equation.

R: Relative velocity at normal speed = 1

R = × l n: VP0 to 7 setting value

l: Multiple set by VPCTL0, 1

256 – n

32

∗

The above setting should be 0, 0 except for the CAV-W operating mode.

The settings are as follows in CAV-W mode.

Command bit

VPCTL1 VPCTL0

Processing

The setting of VP0 to 7 is multiplied by 1. The setting of VP0 to 7 is multiplied by 2. The setting of VP0 to 7 is multiplied by 3. The setting of VP0 to 7 is multiplied by 4.

0 0 1 1

0 1 0 1

Command

Data 2

CLV CTRL VP7 VP6 VP5 VP4

D3 D2 D1 D0

Data 3

VP3 VP2 VP1 VP0

D3 D2 D1 D0

Data 4

VP

CTL1VPCTL0

0 0

D3 D2 D1 D0

Command bit

Processing

VP0 to 7 The spindle rotational velocity is set.

Command bit

VP0 to 7 = F0 (H)

VP0 to 7 = E0 (H)

VP0 to 7 = C0 (H)

Playback at 1/2 (1) × speed

Playback at 1 (2) × speed

Playback at (4) × speed

Description

Notes)

1. Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high.

2. The values in parentheses are for when DSPB is 1.

……

2

R – Relative velocity [Multiple]

1.5

1

0.5

F0 E0

VP0 to VP7 setting value [HEX]

DSPB = 1

DSPB = 0

2.5

3

3.5

4

D0 C0

– 48 –

CXD3068Q

Command bit

Processing

VPCTL1 to 0, VP7 to 0 The pitch of variable pitch mode is set.

The setting in variable pitch mode is as shown below.

The setting of the pitch can be expressed with the equation below.

P = [%]

–n 10

P:Setting value of pitch n: Setting value for VPCTL1, VPCTL0 and VP7 to VP0 (two's complementary,

VPCTL1 is sign bit)

The setting range of the pitch is –48.7 to +51.2%. The pitch setting for + side should be within the playback speed of the recommended operating conditions.

The following is the example of the command in variable pitch mode.

$EX001 (Sets to CLV-N: INV VPCO = 1) $AE4XX (Sets to use variable pitch mode) $ACXXXXX (Variable pitch mode is turned on. The VCO2 is the reference to the internal clock.) WAIT (Wait time for VCO2 pull-in: until VCTL is stabilized) $D60A00 (The pitch is set to –1.0%) $D60000 (The pitch is set to 0.0%) $AE4XX (Variable pitch mode is turned off. The crystal is the reference to the internal clock.)

VPCTL1

1

0

VPCTL0

0

1

0

1

VP7 to 0

00 (H)

:

FF (H)

00 (H)

:

FF (H)

00 (H)

:

FF (H)

00 (H)

:

FF (H)

Setting value of pitch [%]

+51.2

: +25.7 +25.6

:

+0.1

0.0 :

–25.5 –25.6

:

–48.7

Example of command setting

$D60080

: $D6FF80 $D600C0

:

$D6FFC0

$D60000

: $D6FF00 $D60040

: $D6E740

Command bit

– 49 –

CXD3068Q

$EX commands

Command

Data 1

SPD mode CM3 CM2 CM1 CM0

D3 D2 D1 D0

Data 2

EPWM SPDC ICAP SFSL

D3 D2 D1 D0

Data 3

VC2C HIFC LPWR VPON

D3 D2 D1 D0

Command bit

CM3 CM2 CM1

Description

Spindle stop mode.

∗1

Spindle forward rotation mode.

∗1

Spindle reverse rotation mode. Valid only when LPWR = 0 in any mode.

∗1

Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range.

PLL servo mode. Automatic CLVS/CLVP switching mode.

Used for normal playback.

0 1

1

1 0

0 0

0

1

1 1

0 0

1

1 1

CM0

0 0

0

1 0

Mode

STOP

KICK

BRAKE

CLVS

CLVP CLVA

∗

1

See Timing Charts 1-6 to 1-12.

Command bit

EPWM SPDC ICAP

Description

Crystal reference CLV servo. Used for playback in CLV-W

mode.

∗2

Spindle control with VP0 to 7. Spindle control with the external

PWM. VCO control

∗3

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

SFSL

0 0 0 0 0

VC2C

0 1 0 0 0

HIFC

0 1 1 1 1

LPWR

0 0 0 0 0

VPON

0 0 1 1 1

INV

VPCO

0 0 0 0 1

Mode

CLV-N

CLV-W CAV-W CAV-W

VCO-C

∗2

Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode.

∗3

Fig. 3-3 shows the control flow with the microcomputer software in VCO-C mode.

– 50 –

CXD3068Q

Command

SPD mode

Data 4

• This sets the gain when controlling the spindle with the phase comparator in CAV-W mode.

D3 D2 D1 D0

Gain

CAV1

Gain

CAV0

0

INV

VPCO

Gain

CAV1

0 0 1 1

Gain

CAV0

0 1 0 1

Gain

0dB

–6dB –12dB –18dB

Mode

CLV-N

CLV-W

CAV-W

LPWR

0

1

0

1

Command

KICK

BRAKE

STOP

KICK

BRAKE

STOP

KICK

BRAKE

STOP

KICK

BRAKE

STOP

KICK

BRAKE

STOP

1-6 (a) 1-6 (b) 1-6 (c) 1-7 (a) 1-7 (b) 1-7 (c) 1-8 (a) 1-8 (b) 1-8 (c) 1-9 (a) 1-9 (b)

1-9 (c) 1-10 (a) 1-10 (b) 1-10 (c)

Timing chart

Mode

CLV-N

CLV-W

CAV-W

LPWR

0 0 1 0 1 0 1

1-11 1-12

1-13 1-14 (EPWM = 0) 1-15 (EPWM = 0) 1-16 (EPWM = 1) 1-17 (EPWM = 1)

Timing chart

– 51 –

CXD3068Q

Timing Chart 1-3

Rch 16bit C2 Pointer Lch 16bit C2 Pointer

If C2 Pointer = 1,

data is NG

C2 Pointer for upper 8bits C2 Pointer for lower 8bits

Rch C2 Pointer

C2 Pointer for upper 8bits C2 Pointer for lower 8bits

Lch C2 Pointer

LRCK

WDCK

CDROM = 0

C2PO

CDROM = 1

C2PO

48 bit slot

– 52 –

CXD3068Q

Timing Chart 1-4

Level Meter Timing

96 clock pulses

WFCK

1 2 3

96 clock pulses

CRCF CRCF

1 2 3

Peak data of this section

16 bit

R/LL/R

96 bit data

Hold section

1 2 3 80 81 96

CRCF

SQCK

D0 D1 D2 D3 D4 D5 D6 D13 D14 L/R

Peak data

L/R flag

Sub Q Data

See "Sub Code Interface"

15-bit peak-data

Absolute value display, LSB first

750ns to 120µs

SQCK

SQSO

– 53 –

CXD3068Q

Timing Chart 1-5

Measurement

Peak Meter Timing

96 clock pulses

CRCF

WFCK

1 2 3

Measurement Measurement

96 clock pulses

CRCF CRCF

1 2 3

SQCK

– 54 –

CXD3068Q

Timing Chart 1-6 CLV-N mode LPWR = 0

Timing Chart 1-7 CLV-W mode (when following the spindle rotational velocity) LPWR = 0

Timing Chart 1-8 CLV-W mode (when following the spindle rotational velocity) LPWR = 1

Timing Chart 1-9 CAV-W mode LPWR = 0

Timing Chart 1-10 CAV-W mode LPWR = 1

KICK

MDP

H

(a) KICK

BRAKE

MDP

(b) BRAKE

STOP

MDP

(c) STOP

Z

L

Z

KICK

MDP

H

(a) KICK

BRAKE

MDP

(b) BRAKE

STOP

MDP

(c) STOP

Z

L

Z

KICK

MDP

H

(a) KICK

BRAKE

MDP

(b) BRAKE

Z

STOP

MDP

(c) STOP

Z

KICK

MDP

H

(a) KICK

BRAKE

MDP

(b) BRAKE

STOP

MDP

(c) STOP

Z

L

KICK

MDP

H

(a) KICK

BRAKE

MDP

(b) BRAKE

Z

STOP

MDP

(c) STOP

Z

– 55 –

CXD3068Q

Timing Chart 1-14 CAV-W mode EPWM = LPWR = 0

Timing Chart 1-11 CLV-N mode LPWR = 0

Timing Chart 1-12 CLV-W mode LPWR = 0

Timing Chart 1-13 CLV-W mode LPWR = 1

Timing Chart 1-15 CAV-W mode EPWM = LPWR = 1

MDP

Acceleration

Z

Deceleration

264kHz

3.8µs

MDP

Acceleration

Z

Deceleration

132kHz

7.6µs

n · 236 (ns) n = 0 to 31

MDP

Acceleration

Z

Deceleration

264kHz

3.8µs

MDP

Acceleration

Z

264kHz

3.8µs

The BRAKE pulse is masked when LPWR = 1.

MDP

Acceleration

Z

264kHz

3.8µs

The BRAKE pulse is masked when LPWR = 1.

– 56 –

CXD3068Q

Timing Chart 1-16 CAV-W mode EPWM = 1, LPWR = 0

Timing Chart 1-17 CAV-W mode EPWM = LPWR = 1

PWMI

MDP

H

L

H

L

Acceleration

Deceleration

PWMI

MDP

H

L

H

Z

Acceleration

The BRAKE pulse is masked when LPWR = 1.

– 57 –

CXD3068Q

[2] Subcode Interface

There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK. Sub-Q can be read out after checking CRC of the 80 bits in the subcode frame. Sub-Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high.

§ 2-1. P to W Subcode Readout

Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.)

§ 2-2. 80-bit Sub-Q Readout

Fig. 2-2 shows the peripheral block of the 80-bit Sub-Q register.

• First, Sub-Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit.

• 96-bit Sub-Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC check) has been loaded.

• When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.

• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.

• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register.

• While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial register or the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others.

• The previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial register. For ring control 1, input and output are shorted during peak meter and level meter modes. For ring control 2, input and output are shorted during peak meter mode. This is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. As a result, the 96-bit clock must be input in peak meter mode.

• The absolute time after peak is stored in the memory in peak meter mode. (See Timing Chart 2-3.)

• The high and low intervals for SQCK should be between 750ns and 120µs.

– 58 –

CXD3068Q

Timing Chart 2-1

Internal PLL clock

4.3218 ± ∆MHz

WFCK

SCOR

EXCK

SBSO

750ns max

S0 · S1 Q R

WFCK

SCOR

EXCK

SBSO

S0·S1

Q R S T U V W

S0

·S1

P1 Q R S T U V W P1 P2 P3

Same Same

Subcode P.Q.R.S.T.U.V.W Read Timing

– 59 –

CXD3068Q

Block Diagram 2-2

888888888

Order

Inversion

16

Peak detection

LOAD CONTROL

Ring control 2

CRCF

Mix

Monostable

multivibrator

CRCC

ABS time load control

for peak value

16 bit P/S registerRing control 1

SO SI

SQSO

SQCKSHIFT

SHIFT

SUBQ

LD

SO

H G F E D C B A

A B C D E F G H

SI

80 bit P/S Register

80 bit S/P Register

(AFRAM) (ASEC) (AMIN) ADDRS CTRL

SIN

SUBQ

LD LD LD LD LD LD LD

– 60 –

CXD3068Q

Timing Chart 2-3

1

2

3

91 92 93 94

95 96 97

98

WFCK

SCOR

SQSO

SQCK

Monostable

Multivibrator

(Internal)

CRCF1

Determined by mode

CRCF2

80 or 96 Clock

Register load forbidder

270 to 400µs when SQCK = high.

750ns to 120µs

300ns max

CRCF

ADR0

ADR1

ADR2

ADR3

CTL0

CTL1

CTL2

CTL3

SQCK

SQSO

1

2

3

CRCF1

– 61 –

CXD3068Q

Timing Chart 2-4

Signal

PER0 to 7

FOK

GFS

LOCK

EMPH

ALOCK

VF0 to 9

RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.

Focus OK.

High when the frame sync and the insertion protection timing match.

GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low.

High when the playback disc has emphasis.

GFS is sampled at 460Hz; when GFS is high eight consecutive samples, this pin outputs a high signal. If GFS is low eight consecutive

samples, this pin outputs low.

Used in CAV-W mode. The result obtained by measuring the rotational velocity of the disc. (See Timing Chart 2-5.) VF0 = LSB, VF9 = MSB.

Description

C1F2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No C1 errors; C1 pointer reset

One C1 error corrected; C1 pointer reset

—

No C1 errors; C1 pointer set

One C1 error corrected; C1 pointer set

Two C1 errors corrected; C1 pointer set

C1 correction impossible; C1 pointer set

C1F1 C1F0 Description

C2F2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No C2 errors; C2 pointer reset

One C2 error corrected; C2 pointer reset

Two C2 errors corrected; C2 pointer reset

Three C2 errors corrected; C2 pointer reset

Four C2 errors corrected; C2 pointer reset

—

C2 correction impossible; C1 pointer copy

C2 correction impossible; C2 pointer set

C2F1 C2F0 Description

Example: $802000 latch

Set SQCK high during this interval.

Internal signal latch

PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 C1F0 C1F1 C1F2 C2F0 C2F1 C2F2 FOK GFS LOCK EMPH

750ns or more

XLAT

SQCK

SQSO

ALOCK VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF9VF7 VF8

– 62 –

CXD3068Q

Timing Chart 2-5

The relative velocity of the disc can be obtained with the following equation.

R = (R: Relative velocity, m: Measurement results)

VF0 to 9 is the result obtained by counting V16M/2 pulses while the reference signal (132.2kHz) generated from XTAL (XTAI, XTAO) (384Fs) is high. This value is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low).

(m + 1)

32

Measurement interval (approximately 3.8µs)

Reference window

(132.2kHz)

Measurement pulse

(V16M/2)

Measurement counter

VF0 to 9

Load

m

– 63 –

CXD3068Q

Timing Chart 2-6

18 17C1 MSB 19 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0537005370

C1 error rate C2 error rate

XLAT

SQCK

SQSO

– 64 –

CXD3068Q

[3] Description of Modes

This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below.

§ 3-1. CLV-N Mode

This mode is compatible with the CXD2510Q, and operation is the same as for conventional control. The PLL capture range is ±150kHz.

§ 3-2. CLV-W Mode

This is the wide capture range mode. This mode allows the PLL to follow the rotational velocity of the disc. This rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below. (When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external VCO, and input the oscillation from the VCO to the V16M pin.) When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is stopped, CAV-W mode should be used. Specifically, first send $E665X to set CAV-W mode and kick the disc, then send $E60CX to set CLV-W mode if ALOCK is high, which can be read out serially from the SQSO pin. CLV-W mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software in CLV-W mode is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set high, deceleration pulses are not output, thereby achieving low power consumption mode.

Note) The capture range for this mode is theoretically up to the signal processing limit.

§ 3-3. CAV-W Mode

This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to the desired rotational velocity. The rotational velocity is determined by the VP0 to VP7 setting values or the external PWM. When controlling the spindle with VP0 to VP7, setting CAV-W mode with the $E665X command and controlling VP0 to VP7 with the $DX commands allows the rotational velocity to be varied from low speed to 4× speed. (See "$DX commands".) Also, when controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using V16M. The reference frequency for the velocity measurement is a signal of 132.3kHz obtained by dividing XTAL (XTAI, XTAO) (384Fs) by 128. The velocity is obtained by counting the half of V16M pulses while the reference is high, and the result is output from the new CPU interface as 10 bits (VP0 to VP9). These measurement results are 31 when the disc is rotating at normal speed or 127 when it is rotating at 4× speed. These values match those of the 256 - n for control with VP0 to VP7. (See Table 2-5 and Fig. 2-6.) In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and others output from this LSI change according to the rotational velocity of the disc.

Note) The capture range for this mode is theoretically up to the signal processing limit. Note) Set FLFC to 1 for this mode

– 65 –

CXD3068Q

§ 3-4. VCO-C Mode

This is VCO control mode. In this mode, the V16M oscillation frequency can be controlled by setting $D commands VP0 to VP7 and VPCTL0, 1. The V16M oscillation frequency can be expressed by the following equation.

n: VP0 to 7 setting value l: VPCTL0, 1 setting value

The VCO1 oscillation frequency is determined by V16M. The VCO1 frequency can be expressed by the following equation.

• When DSPB = 0

• When DSPB = 1

l (256 – n)

V16M =

32

49

VCO1 = V16M ×

24

49

VCO1 = V16M ×

16

– 66 –

CXD3068Q

Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode

CLV-W Mode

Fig. 3-2. CLV-W Mode Flow Chart

CAV-W

CLVS

CLV-W

CLVP

Rotational velocity

Target speed

Operation mode

Spindle mode

Time

KICK

LOCK

ALOCK

NO

YES

KICK $E8000 Mute OFF $A00XXXX

ALOCK = H ?

NO

YES

ALOCK = L ?

CLV-W MODE

START

CAV-W $E665X

(CLVA)

CLV-W $E60CX

(CLVA)

(WFCK PLL)

– 67 –

CXD3068Q

VCO-C Mode

Fig. 3-3. Access Flow Chart Using VCO Control

R?

(How many minutes

of absolute time?)

Access START

Transfer

$E00510

n?

(Calculate n)

Transfer

$DX XX

Track Jump

Subroutine

Transfer

$E66500

Access END

What is the ultimate speed multiple?

Calculate VP0 to VP7.

Switch to VCO control mode. EPWM = SPDC = ICAP = SFSL = VC2C = LPWR = 0 HIFC = VPON = 1

Transfer VP0 to VP7. ( corresponds to VP0 to VP7.)

Switch to normal-speed playback mode. EPWM = SFSL = VC2C = LPWR = 0 SPDC = ICAP = HIFC = VPON = 1

– 68 –

CXD3068Q

[4] Description of other functions

§ 4-1. Channel Clock Regeneration by Digital PLL Circuit

• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.

Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, a PLL is necessary for regenerating the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses.

The block diagram of this PLL is shown in Fig. 4-1. The CXD3068Q has a built-in three-stage PLL.

• The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are necessary. The output of this first-stage PLL is used as a reference for all clocks within the LSI.

• The second-stage PLL regenerates the high-frequency clock needed by the third-stage digital PLL.

• The third-stage PLL is a digital PLL that regenerates the actual channel clock.

• The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the

secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency components such as 3T and 4T may contain deviations. In such cases, turning the secondary loop off yields better playability. However, in this case the capture range becomes ±50kHz.

• A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition to the conventional secondary loop.

– 69 –

CXD3068Q

Block Diagram 4-1

XTSL

1/2 1/32

1/n

1/2

Microcomputer control

n = 1 to 256

(VP7 to 0)

1/K

(KSL1, 0)

CLV-W CAV-W

Spindle rotation information

CLV-N

CLV-W CAV-W

/CLV-N

Phase comparator

Selector

LPF

2/1 MUX

VPON

1/M

1/N

VCOSEL2

VCO2

Phase comparator

VCO1

VCOSEL1

1/K

(KSL3, 2)

Digital PLL

RFPLL

VPCO

VCTL

V16M

PCO

FILI

FILO

CLTV

XTAI

Clock input

1/l

l = 1, 2, 3, 4

(VPCTL0, 1)

– 70 –

CXD3068Q

§ 4-2. Frame sync protection

• In normal speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is

used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability.

• In the CXD3068Q, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is set to 13∗, and the backward protection counter to 3∗. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately.

∗

Default values. These values can be set as desired by $C commands SFP0 to SFP3 and SRP0 to SRP3.

§ 4-3. Error Correction

• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code

is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5.

• The CXD3068Q uses refined super strategy to achieve double correction for C1 and quadruple correction for C2.

• In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the

C1 error status, the playback status of the EFM signal, and the operating status of the player.

• The correction status can be monitored externally. See Table 4-2.

• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data.

MNT3

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

No C1 errors; C1 pointer reset One C1 error corrected; C1 pointer reset

—

— No C1 errors; C1 pointer set One C1 error corrected; C1 pointer set Two C1 errors corrected; C1 pointer set C1 correction impossible; C1 pointer set No C2 errors; C2 pointer reset One C2 error corrected; C2 pointer reset Two C2 errors corrected; C2 pointer reset Three C2 errors corrected; C2 pointer reset Four C2 errors corrected; C2 pointer reset

— C2 correction impossible; C1 pointer copy C2 correction impossible; C2 pointer set

MNT2 MNT1 MNT0 Description

Table 4-2

– 71 –

CXD3068Q

Timing Chart 4-3

§ 4-4. DA Interface

• The CXD3068Q supports the 48-bit slot interface as the DA interface.

48-bit slot interface

This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel.

Normal-speed PB

400 to 500ns

RFCK

MNT3

MNT1

MNT0

t = Dependent on error

condition

C1 correction C2 correction

Strobe

MNT2

– 72 –

CXD3068Q

Timing Chart 4-4

LRCK

(44.1K)

DA15

(2.12M)

WDCK

DA16

LRCK

(88.2K)

DA15

(4.23M)

WDCK

DA16

48-bit slot Normal-Speed Playback PSSL = L

1

24

R0

Lch MSB (15)

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB

Lch MSB (15)

24

Rch MSB

2 3 4 5 6 7 8 9 10 11 12

48-bit slot Double-Speed Playback

1 2

L0

R0

– 73 –

CXD3068Q

§ 4-5. Digital Out

There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD3068Q supports type 2 form 1. The channel status clock accuracy is automatically set to level II when using the crystal clock and to level III in CAV-W mode or variable pitch mode. In addition, Sub-Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3). DOUT is output when the crystal is 34MHz and DSPB is set to 1 with XTSL high in CLV-N or CLV-W mode. Therefore, set MD2 to 0 and turn DOUT off.

Table 4-5

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0

0

ID0

ID1

COPY

Emph

0 0 0 0 1 0 0 0 0 0 0 0

From sub Q

0

16

32

48

176

Sub-Q control bits that matched twice with CRCOK

Digital Out C bit

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

VPON or VARION: 1 X'tal: 0

bit0 to 3 bit29

– 74 –

CXD3068Q

§ 4-6. Servo Auto Sequence

This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump, fine search and M-track move are executed automatically. The servo block operates according to the built-in program during the auto sequence execution (when XBUSY = low), so that commands from the CPU, that is $0, 1, 2 and 3 commands, are not accepted. ($4 to E commands are accepted.) In addition, when using the auto sequence, turn the A.SEQ of register 9 on. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µs after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low). In addition, a MAX timer is built into this LSI as a countermeasure against abnormal operation due to external disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like $40). See [1] "$4X commands" concerning the timer value and range. Also, the MAX timer is invalidated by inputting $4X0. Although this command is explained in the format of $4X in the following command descriptions, the timer value and timer range are actually sent together from the CPU.

(a) Auto focus ($47)

Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-6. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search-down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E.

(b) Track jump

1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not involved in this sequence.

• 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 4-7. Set blind A and brake B with register 5.

• 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed an accordance with Fig. 4-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on.

– 75 –

CXD3068Q

• 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 4-9. The track jump count N is set with register 7. Although N can be set to 216tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps when N is less than 16, and MIRR is used with N is 16 or more. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.

• Fine search When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed in accordance with Fig. 4-10. The differences from a 2N-track jump are that a higher precision is achieved by controlling the traverse speed, and a longer distance jump is achieved by controlling the sled. The track jump count is set with register 7. N can be set to 216tracks. After kicking the actuator and sled, the traverse speed is controlled based on the overflow G. Set kick D and F with register 6 and overflow G with register 5. Also, sled speed control during traverse can be turned off by causing COMP to fall. Set the number of tracks during which COMP falls with register B. After N tracks have been counted through COUT, the brake is applied to the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and by kicking the sled in the opposite direction during the time for kick D set with register 6.) Then, the tracking and sled servos are turned on. Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For example, set the target track count N – α for the traverse monitor counter which is set with register B, and COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be reset.

• M-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) M-track move is performed in accordance with Fig. 4-11. M can be set to 216tracks. Like the 2N-track jump, COUT is used for counting the number of moves when M is less than 16, and MIRR is used when M is 16 or more. The M-track move is executed by moving only the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. In addition, the track and sled servos are turned off after M tracks have been counted through COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator has stabilized.

– 76 –

CXD3068Q

Fig. 4-6-(a). Auto Focus Flow Chart

Fig. 4-6-(b). Auto Focus Timing Chart

Auto focus

Focus search up

FOK = H

NO

YES

FZC = H

NO

YES

FZC = L

NO

YES

END

Focus servo ON

Check whether FZC is continuously high for the period of time E set with register 5.

XLAT

$47 Latch

$03

Blind E

$08

FOK

FZC

BUSY

Command for

DSSP

– 77 –

CXD3068Q

Fig. 4-7-(a). 1-Track Jump Flow Chart

Fig. 4-7-(b). 1-Track Jump Timing Chart

1 Track

NO

YES

END

Track FWD kick

sled servo OFF

WAIT

(Blind A)

COUT =

Track REV

kick

WAIT

(Brake B)

Track, sled

servo ON

(FWD kick for REV jump)

(REV kick for REV jump)

XLAT

COUT

BUSY

Command for

DSSP

$48 (REV = $49) Latch

$28 ($2C)

Blind A

Brake B

$2C ($28)

$25

– 78 –

CXD3068Q

Fig. 4-8-(a). 10-Track Jump Flow Chart

Fig. 4-8-(b). 10-Track Jump Timing Chart

10 Track

NO

YES

END

Track, sled

FWD kick

WAIT

(Blind A)

COUT = 5 ?

Track, REV

kick

Track, sled

servo ON

Checks whether the COUT cycle is longer than overflow C.

(Counts COUT × 5)

NO

YES

C = Overflow ?

COUT

$4A (REV = $4B) Latch

Blind A

$2A ($2F)

COUT 5 count

$2E ($2B)

Overflow C

$25

XLAT

BUSY

Command for

DSSP

– 79 –

CXD3068Q

Fig. 4-9-(a). 2N-Track Jump Flow Chart

Fig. 4-9-(b). 2N-Track Jump Timing Chart

2N Track

NO

YES

END

Track, sled

FWD kick

WAIT

(Blind A)

COUT (MIRR) = N

Track REV

kick

Track servo

ON

NO

YES

C = Overflow

WAIT

(Kick D)

Sled servo

ON

Counts COUT for the first 16 times and MIRR for more times.

XLAT

Blind A

$2A ($2F)

COUT (MIRR)

N count

$2E ($2B)

Overflow C

Kick D

$26 ($27)

$25

$4C (REV = $4D) Latch

COUT

(MIRR)

BUSY

Command for

DSSP

– 80 –

CXD3068Q

Fig. 4-10-(a). Fine Search Flow Chart

Fig. 4-10-(b). Fine Search Timing Chart

Track Servo ON

Sled FWD Kick

Fine Search

WAIT

(Kick D)

Track Sled

FWD Kick

WAIT

(Kick F)

Traverse

Speed Ctrl

(Overflow G)

COUT = N?

Track Servo ON

Sled REV Kick

WAIT

(Kick D)

Track Sled

Servo ON

END

YES

NO

Traverse Speed Control (Overflow G)

&

COUT N count

Kick FKick D

$26 ($27)

$2A ($2F)

$27 ($26)

$25

$44 (REV = $45) latch

XLAT

COUT

Kick D

BUSY

Command for

DSSP

– 81 –

CXD3068Q

Fig. 4-11-(a). M-Track Move Flow Chart

Fig. 4-11-(b). M-Track Move Timing Chart

M Track Move

NO

YES

END

Track Servo OFF

Sled FWD Kick

WAIT

(Blind A)

COUT (MIRR) = M

Track, Sled

Servo OFF

Counts COUT for M < 16. Counts MIRR for M ≥ 16.

XLAT

Blind A

$22 ($23)

COUT (MIRR)

M count

$20

$4E (REV = $4F) Latch

COUT

(MIRR)

BUSY

Command for

DSSP

– 82 –

CXD3068Q

§ 4-7. Digital CLV

Fig. 4-12 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable.

Fig. 4-12. Block Diagram

CLVS U/D: Up/down signal from CLVS servo MDS error: Frequency error for CLVP servo MDP error: Phase error for CLVP servo PWMI: Spindle drive signal from the microcomputer for CAV servo

MDP

Digital CLV

CLVS U/D

MDS Error

MDP Error

CLV P/S

Measure

2/1 MUX

Over Sampling

Filter-1

Gain MDS

1/2

Mux

CLV P/S

Over Sampling

Filter-2

Noise Shape

Modulation

KICK, BRAKE, STOP

Mode Select

Gain DCLV

Gain MDP

LPWR

PWMI

– 83 –

CXD3068Q

§ 4-8. Playback Speed

In the CXD3068Q, the following playback modes can be selected through different combinations of XTAI, XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode.

Mode

1 2 3 4 5 6 7

XTAI

768Fs 768Fs 768Fs 768Fs 384Fs 384Fs 384Fs

XTSL

1 1 0 0 0 0 1

DSPB

0 1 0 1 0 1 1

VCOSEL1

∗1

0/1 0/1

1

1 0/1 0/1 0/1

ASHS

0 0 1 1 0 0 0

Playback speed

1× 2× 2× 4× 1× 2× 1×

Error correction

∗2

C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double

∗1

Actually, the optimal value should be used together with KSL3 and KSL2.

∗2

When $8 ERC4 = 1, C2 is for quadruple correction with DSPB = 1.

The playback speed can be varied by setting VP0 to VP7 in CAV-W mode. See "[3] Description of Modes" for details.

– 84 –

CXD3068Q

§ 4-9. Asymmetry Correction

Fig. 4-13 shows the block diagram and circuit example.

Fig. 4-15. Asymmetry Correction Application Circuit

ASYE

RFAC

R1

ASYO

ASYI

R1 2 R2 5

=

BIAS

R1

R2

– 85 –

CXD3068Q

§4-10. CD TEXT Data Demodulation

• In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to 1. During TXON = 1,

connect EXCK to low and do not use the data output from SBSO because the CD TEXT demodulation circuit uses EXCK and the SBSO pin exclusively. It requires 26.7ms (max.) to demodulate the CD TEXT data correctly after TXON is set to 1.

• The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is enabled by setting the command $8 Data 6 D2 TXOUT to 1. To read data, the readout clock should be input to SQCK.

• The readable data are the CRC counting results for the each pack and the CD TEXT data (16 bytes) except for CRC data.

• When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.

• Data which can be stored in the LSI is 1 packet (4 packs).

Fig. 4-14. Block Diagram of CD TEXT Demodulation Circuit

SQCK

SQSO

TXOUT

Subcode

Decoder

CD TEXT

Decoder

TXON

SBSO

EXCK

– 86 –

CXD3068Q

Fig. 4-15. CD TEXT Data Timing Chart

CRC

4

CRC

3

CRC

2

CRC

1

0

0 0 0

S2 R2 W1 V1 U1 T1 S1 R1 U3 T3 S3 R3 W2 V2 U2 T2 W4 V4 U4 T4 S4

CRC Data

ID1 (Pack1)

ID2 (Pack1)

ID3 (Pack1)

16Byte

4bit

Subcode Q Data

SCOR

TXOUT

(command)

SQCK

SQSO

SQCK

TXOUT

(command)

LSB

MSB

LSB MSB

LSB

CRC

0

Pack1

Pack2

Pack3

Pack4

CRCF

80 Clock

SQSO

520 Clock

– 87 –

CXD3068Q

[5] Description of Servo Signal Processing System Functions and Commands

§5-1. General Description of Servo Signal Processing System (VDD: Supply voltage)

Focus servo

Sampling rate: 88.2kHz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Output format: 7-bit PWM Other: Offset cancel

Focus bias adjustment Focus search Gain-down function Defect countermeasure Auto gain control

Tracking servo

Sampling rate: 88.2kHz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Output format: 7-bit PWM Other: Offset cancel

E:F balance adjustment Track jump Gain-up function Defect countermeasure Drive cancel Auto gain control Vibration countermeasure

Sled servo

Sampling rate: 345Hz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Output format: 7-bit PWM Other: Sled move

FOK, MIRR, DFCT signal generation

RF signal sampling rate: 1.4MHz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Other: RF zero level automatic measurement

– 88 –

CXD3068Q

§5-2. Digital Servo Block Master Clock (MCK)

The clock with the 2/3 frequency of the crystal is supplied to the digital servo block. XT4D and XT2D are $3F commands, and XT1D is $3E command. (Default = 0) The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical.

Mode

1 2 3 4 5 6 7

384Fs 384Fs 384Fs 768Fs 768Fs 768Fs 768Fs

256Fs 256Fs 256Fs 512Fs 512Fs 512Fs 512Fs

∗ ∗

0

∗ ∗ ∗

1

∗ ∗

0

∗ ∗

1 0

∗

1 0

∗

1 0 0

1 0 0 1 0 0 0

1 1/2 1/2

1 1/2 1/4 1/4

256Fs 128Fs 128Fs 512Fs 256Fs 128Fs 128Fs

XTAI FSTO XTSL XT4D XT2D XT1D Frequency division ratio MCK

Fs = 44.1kHz, ∗: Don’t care

Table 5-1

– 89 –

CXD3068Q

§ 5-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.)

The CXD3068Q can measure the average of RFDC, VC, FE and TE and compensate these signals using the measurement results to control the servo effectively. This AVRG measurement and compensation is necessary to initialize the CXD3068Q, and is able to cancel the DC offset. AVRG measurement takes the levels applied to the VC, FE, RFDC and TE pins as the digital average of 256 samples, and then loads these values into each AVRG register. The AVRG measurement commands are D15 (VCLM), D13 (FLM), D11 (RFLM) and D4 (TLM) of $38. Measurement is on when the respective command is set to 1. AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received. The completion of AVRG measurement operation can be monitored by the SENS pin. (See Timing Chart 5-2.) Monitoring requires that the upper 8 bits of the command register are 38 (Hex).

Timing Chart 5-2

VC AVRG: The VC DC offset (VC AVRG) which is the center voltage for the system is measured and used to

compensate the FE, TE and SE signals. FE AVRG: The FE DC offset (FE AVRG) is measured and used to compensate the FE and FZC signals. TE AVRG: The TE DC offset (TE AVRG) is measured and used to compensate the TE and SE signals. RF AVRG: The RF DC offset (RF AVRG) is measured and used to compensate the RFDC signal.

RFLC: (RF signal – RF AVRG) is input to the RF In register.

"00" is input when the RF signal is lower than RF AVRG. TLC0: (TE signal – VC AVRG) is input to the TRK In register. TLC1: (TE signal – TE AVRG) is input to the TRK In register. VCLC: (FE signal – VC AVRG) is input to the FCS In register. FLC1: (FE signal – FE AVRG) is input to the FCS In register. FLC0: (FE signal – FE AVRG) is input to the FZC register.

Two methods of canceling the DC offset are assumed for the CXD3068Q. These methods are shown in Figs. 5-3a and 5-3b. An example of AVRG measurement and compensation commands is shown below. $38 08 00 (RF AVRG measurement) $38 20 00 (FE AVRG measurement) $38 00 10 (TE AVRG measurement) $38 14 0A (Compensation on [RFLC, FLC0, FLC1, TLC1], corresponds to Fig. 5-3a.)

See the description of $38 for these commands.

XLAT

SENS ( = XAVEBSY)

Max. 1µs

AVRG measurement completed

2.9 to 5.8ms

– 90 –

CXD3068Q

§ 5-4. E:F Balance Adjustment Function (See Fig. 5-3.)

When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search), the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1. The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to "0". Next, setting D2 (TLC2) of $38 to 1 compensates the values obtained from the TE and SE input pins with the TRVSC register value (subtraction), allowing the E:F balance offset to be adjusted. (See Fig. 5-3.)

§ 5-5. FCS Bias (Focus Bias) Adjustment Function

The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 5-3.) When D11 = 0 and D10 = 1 is set by $34F, the FBIAS register value can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the $8 command SOCT to 1. (See "DSP Block Timing Chart".)

The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0. The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A.

When using the FBIAS register as a counter, the counter stops when the value set beforehand in FBL9 to FBL1 of $34 matches the FCSBIAS value. Also, if the upper 8 bits of the command register are $3A at this time, SENS goes to high and the counter stop can be monitored.

Here, assume the FBIAS setting value FB9 to FB1 and the FBIAS LIMIT value FBL9 to FBL1 are set in status A. For example, if command registers FBUP = 0, FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from this status, down count starts from status A and approaches the set LIMIT value. When the LIMIT value is reached and the FBIAS value matches FBL9 to FBL1, the counter stops and the SENS pin goes to high. Note that the up/down counter counts at each sampling cycle of the focus servo filter. The number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to 1/512 × VDD × 0.4.

A B C

FBIAS setting value (FB9 to FB1)

LIMIT value (FBL9 to FBL1)

SENS pin

A: Register mode B: Counter mode C: Counter mode (when stopped)

– 91 –

CXD3068Q

Fig. 5-3a.

Fig. 5-3b.

TE AVRG

register

TLC1

TRVSC

register

TLC2

– –

To TRK In register

TE from A/D

FE AVRG

register

FLC1

FBIAS

register

FBON

–

To FCS In register

FLC0

To FZC register

FE from A/D

–

RFLC

–

To RF In registerRFDC from A/D

RF AVRG

register

– –

Tp SLD In registerSE from A/D

TLC1 · TLD1 TLC2 · TLD2

+

VC AVRG

register

TLC0

TRVSC register

TLC2

– –

To TRK In register

TE from A/D

FBIAS

register

FBON

To FCS In register

VCLC

To FZC register

FE from A/D

–

RFLC

–

To RF In registerRFDC from A/D

RF AVRG

register

–

To SLD In registerSE from A/D

TLC0 · TLD0 TLC2 · TLD2

–

+

FE AVRG

register

FLC0

– 92 –

CXD3068Q

§ 5-6. AGCNTL (Automatic Gain Control) Function

The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate servo loop gain. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the command register are 38 (Hex), the completion of AGCNTL operation can be confirmed by monitoring the SENS pin. (See Timing Chart 5-4 and "Description of SENS Signals".) Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation.

Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described

hereafter) must be disabled.

Timing Chart 5-4

Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written externally. After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter).

AGCNTL related settings

The following settings can be changed with $35, $36 and $37. FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex) TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during rough adjustment) AGV2; AGCNTL sensitivity 2 (during fine adjustment) AGHS; Rough adjustment on/off AGHT; Fine adjustment time

Note) Converging servo loop gain values can be changed with the FG6 to FG0 and TG6 to TG0 setting values. In

addition, these setting values must be within the effective setting range. The default settings aim for 0dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary.

XLAT

SENS ( = AGOK)

Max. 11.4µs

AGCNTL completion

– 93 –

CXD3068Q

AGCNTL and default operation have two stages. In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient is finely adjusted with relatively low sensitivity to further approach the appropriate value. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD3068Q confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self stop mode) This self-stop mode can be canceled by setting AGS to 0. In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. An example of AGCNTL coefficient transitions during AGCNTL operation with various settings is shown in Fig. 5-5.

Fig. 5-5

Note) Fig. 5-5 shows the case where the AGCNTL coefficient converges from the initial value to a smaller

value.

Initial value

SENS

AGCNTL start

AGCNTL completion

Convergence value

AGCNTL coefficient value

Slope AGV1

AGHT

AGJ

Slope AGV2

– 94 –

CXD3068Q

§ 5-7. FCS Servo and FCS Search (Focus Search)

The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.)

Register name

Command

D23 to D20

D19 to D16

1 0 ∗ ∗ 1 1 ∗ ∗ 0 ∗ 0 ∗ 0 ∗ 1 ∗ 0 ∗ 1 0 0 ∗ 1 1

FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP

0 0 0 0

FOCUS CONTROL

0

Table 5-6

FCS Search

FCS search is required in the course of turning on the FCS servo.

Fig. 5-7 shows the signals for sending commands $00 → $02 → $03 and performing only FCS search operation. Fig. 5-8 shows the signals for sending $08 (FCS on) after that.

Fig. 5-7 Fig. 5-8

∗: Don't care

FCSDRV

RF

FOK

FE

FZC

FZC comparator level

$00 $02 $03

0

FCSDRV

RF

FOK

FE

FZC

$00 $02 $03

0

$08

– 95 –

CXD3068Q

§ 5-8. TRK (Tracking) and SLD (Sled) Servo Control

The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.) When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin.

Register name

Command

D23 to D20

D19 to D16

TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE

0 0 1 0

TRACKING MODE

2

Table 5-9

TRK Servo

The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36. In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode. The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. The CXD3068Q has 2 types of gain-up filter structures in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 5-17.)

SLD Servo

The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by multiplying this value by 1×, 2×, 3×, or 4× magnification set using D17 and D16 when D18 = D19 = 0 is set with $3. (See Table 5-10.) SLD MOV must be performed continuously for 50µs or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off.

Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off.

These operations are disabled by setting D6 (LKSW) of $38 to 1.

Register name

Command

D23 to D20

D19 to D16

0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1

SLED KICK LEVEL (basic value × ±1) SLED KICK LEVEL (basic value × ±2) SLED KICK LEVEL (basic value × ±3) SLED KICK LEVEL (basic value × ±4)

0 0 1 1

SELECT

3

Table 5-10

∗: Don't care

0 0 ∗ ∗ 0 1 ∗ ∗ 1 0 ∗ ∗ 1 1 ∗ ∗

∗ ∗ 0 0 ∗ ∗ 0 1 ∗ ∗ 1 0 ∗ ∗ 1 1

– 96 –

CXD3068Q

§ 5-9. MIRR and DFCT Signal Generation

The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and loaded. The MIRR and DFCT signals are generated from this RF signal.

MIRR Signal Generation

The loaded RF signal is applied to peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of this envelope waveform. The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value from the peak hold value with this MIRR comparator level. (See Fig. 5-11.) The bottom hold speed and mirror sensitivity can be selected from 4 values using D7 and D6, and D5 and D4, respectively, of $3C.

Fig. 5-11

DFCT Signal Generation

The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 5-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B.

Fig. 5-12

RF

Peak Hold

Bottom Hold

Peak Hold

– Bottom Hold

MIRR

MIRR Comp (Mirror comparator level)

H L

RF

Peak Hold1

Peak Hold2

– Peak Hold1

DFCT

(Defect comparator level)

H L

SDF

– 97 –

CXD3068Q

§ 5-10. DFCT Countermeasure Circuit

The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, these operations are achieved by detecting scratches and defects with the DFCT signal generation circuit, and when DFCT goes high, applying the low frequency component of the error signal before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.) In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to 1.

Fig. 5-13

§ 5-11. Anti-Shock Circuit

When vibrations occur in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures. Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 5-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level is practically variable by adjusting the value of the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 5-17.) This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up mode by inputting high level to the ATSK pin. When the upper 4 bits of the command register are 1 (Hex), vibration detection can be monitored from the SENS pin. It also can be monitored from the ATSK pin by setting the ASOT command of $3F to 0.

Fig. 5-14

Input register

Hold register EN

Hold Filter

Servo Filter

Error signal

DFCT

TE

Anti Shock

Filter

TRK Gain Up

Filter

TRK Gain Normal

Filter

TRK

PWM Gen

ATSK

SENS

Comparator

– 98 –

CXD3068Q

§ 5-12. Brake Circuit

Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. In principle, the brake circuit uses the tracking drive as a brake by cutting the unnecessary portions utilizing the 180° offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.) Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Fig. 5-17.) In addition, the low frequency for the tracking drive after masking can be boosted. (SFBK1, 2 of $34B)

Fig. 5-15 Fig. 5-16

Register name

Command

D23 to D20

D19 to D16

1 0 ∗ ∗ 0 ∗ ∗ ∗

∗ 1 ∗ ∗ ∗ 0 ∗ ∗ ∗ ∗ 0 ∗ ∗ ∗ 1 ∗ ∗ ∗ ∗ 1 ∗ ∗ ∗ 0

ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2

0 0 0 1

TRACKING CONTROL

1

Table 5-17

∗: Don't care

TRK DRV

FWD

JMP

REV JMP

Servo ON

RF Trace

MIRR

TE 0

TZC Edge

TRKCNCL

0

TRK DRV (SFBK OFF)

SENS TZC out

Inner track Outer track

0

TRK DRV (SFBK ON)

TRK DRV

REV JMP

FWD

JMP

Servo ON

RF Trace

MIRR

TE 0

TZC Edge

TRKCNCL

0

TRK DRV (SFBK OFF)

SENS TZC out

Outer track Inner track

0

TRK DRV (SFBK ON)

– 99 –

CXD3068Q

§ 5-13. COUT Signal

The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among three different phases according to the COUT signal application.

• HPTZC: For 1-track jumps Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a cutoff 1kHz digital HPF; when MCK = 128Fs.)

• STZC:

For COUT generation when MIRR is externally input and for applications other than COUT generation. This is generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)

• DTZC: For high-speed traverse Reliable COUT signal generation with a delayed phase STZC signal.

Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D15 and D14 of $3C.

When D15 = 1: STZC When D15 = 0 and D14 = 0: HPTZC When D15 = 0 and D14 = 1: DTZC When DTZC is selected, the delay can be selected from two values with D14 of $36.

§ 5-14. Serial Readout Circuit

The following measurement and adjustment results can be read out from the SENS pin by inputting the readout clock to the SCLK pin by $39. (See Fig. 5-18, Table 5-19 and "Description of SENS Signals".)

Specified commands

$390C: VC AVRG measurement result $3953: FCS AGCNTL coefficient result $3908: FE AVRG measurement result $3963: TRK AGCNTL coefficient result $3904: TE AVRG measurement result $391C: TRVSC adjustment result $391F: RF AVRG measurement result $391D: FBIAS register value

Item

Symbol

Min.

Typ.

Max.

Unit SCLK frequency SCLK pulse width Delay time

fSCLK

tSPW tDLS

31.3 15

16

MHz

ns µs

Table 5-19

During readout, the upper 8 bits of the command register must be 39 (Hex).

Fig. 5-18

· · ·

tDLS

tSPW

1/fSCLK

MSB LSB

XLAT

SCLK

Serial Readout Data (SENS pin)

– 100 –

CXD3068Q

§ 5-15. Writing to Coefficient RAM

The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40µs (when MCK = 128Fs) after the XRST pin rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is received. When rewriting multiple coefficients, be sure to wait 11.3µs (when MCK = 128Fs) before sending the next rewrite command.

§ 5-16. PWM Output

FCS, TRK and SLD PWM format outputs are described below. In particular, FCS and TRK use a double oversampling noise shaper. Timing Chart 5-20 and Fig. 5-21 show examples of output waveforms and drive circuits.

tMCK = ≈180ns

Timing Chart 5-20

Fig. 5-21. Drive Circuit

1

5.6448MHz

64tMCK

64tMCK 64tMCK

AtMCK

SFDR

SRDR

SLD

32tMCK 32tMCK 32tMCK 32tMCK32tMCK32tMCK

FCS/TRK

FFDR/ TFDR

FRDR/ TRDR

Output value +A Output value –A Output value 0

t

MCK

A 2

tMCK

A 2

tMCK

A 2

tMCK

A 2

MCK (5.6448MHz) ↑ ↑ ↑ ↑ ↑ ↑ ↑

R

VEE

DRV

V

CC

RDR FDR