Datasheet CXD3017Q Datasheet (Sony)

CXD3017Q

CD Digital Signal Processor with Built-in Digital Servo and DAC

Description

The CXD3017Q is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter, zero detection circuit, 1-bit DAC and analog low-pass filter.

Features Digital Signal Processor (DSP) Block

• 1×, 2×, 4× speed playback supported

• 16K-RAM

• EFM data demodulation

• Enhanced EFM frame sync signal protection

• SEC strategy-based error correction

• Subcode demodulation and Sub Q data error

detection

• Digital spindle servo

• 16-bit traverse counter

• Asymmetry compensation circuit

• CPU interface on serial bus

• Error correction monitor signal, etc. output from a

new CPU interface

• Servo auto sequencer

• Digital audio interface outputs

• Digital level meter, peak meter

• CD TEXT data demodulation Digital Servo (DSSP) Block

• Microcomputer software-based flexible servo control

• Offset cancel function for servo error signal

• Auto gain control function for servo loop

• E:F balance, focus bias adjustment function

• Surf jump function supporting micro two-axis

• Tracking filter: 6 stages, focus filter: 5 stages Digital Filter, DAC and Analog Low-pass Filter Blocks

• DBB (digital bass boost) function

• Double-speed playback supported

• Digital de-emphasis

• Digital attenuation

• 8Fs oversampling filter

Applications

CD players

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings

• Supply voltage VDD –0.5 to +4.6 V

• Input voltage VI –0.5 to +4.6 V

(VSS – 0.5V to VDD + 0.5V)

• Output voltage VO –0.5 to +4.6 V (VSS – 0.5V to VDD + 0.5V)

• Storage temperature Tstg –55 to +150 °C

• Supply voltage difference

VSS – AVSS –0.3 to +0.3 V VDD – AVDD –0.3 to +0.3 V

Note) AVDD includes XVDD and AVSS includes XVSS.

Recommended Operating Conditions

• Supply voltage VDD 2.7 to 3.6 V

• Operating temperature

Topr –20 to +75 °C

I/O Capacitance

• Input pin CI 9 (Max.) pF

• Output pin CO 11 (Max.) pF

• I/O pin CI/O 11 (Max.) pF

Note) Measurement conditions VDD = VI = 0V

fM = 1MHz

– 1 –

E99Y24-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

80 pin LQFP (Plastic)

Playback speed

CD-DSP block

DAC block

4×

2.7 to 3.6

2×

2.7 to 3.6 2.7 to 3.6

1×

2.7 to 3.6 2.7 to 3.6

VDD [V]

– 2 –

CXD3017Q

Block Diagram

PWM PWM

AOUT1

AIN1 LOUT1 AOUT2

AIN2 LOUT2

3rd-Order

Noise Shaper

Over Sampling

Digital Filter

Serial-In Interface

LMUT

RMUT

XTAO

XTAI

Timing

Logic

XRST

TEST

TES1

D/A

Interface

DOUT

EFM

demodurator

Error

Corrector

16K

RAM

Digital

OUT

Sub Code Processor

Clock

Generator

Asymmetry

Corrector

Digital

PLL

Digital

CLV

CPU

Interface

Servo

Auto

Sequencer

Signal Processor Block

DAC Block

SYSM

BCK

PCMD

LRCK

C2PO

WFCK

EMPH

GFS

XUGF

XTSL

RFAC

ASYI

ASYO

BIAS

XPCK

FILO

FILI

PCO

CLTV

MDP LOCK SENS DATA

XLAT CLOK SPOA SPOB XLON

SCOR SQSO SQCK

Servo Block

SERVO

Interface

SCLK COUT SSTP ATSK

MIRR DFCT

FOK

MIRR DFCT FOK

SERVO DSP

FOCUS SERVO

TRACKING

SERVO

SLED SERVO

PWM GENERATOR

FOCUS PWM GENERATOR

TRACKING PWM

GENERATOR

SLED PWM

GENERATOR

FFDR FRDR TFDR TRDR SFDR SRDR

RFDC

CE

TE

SE

FE

VC

IGEN

OPAmp

Analog SW

A/D

Converter

ADIO

– 3 –

CXD3017Q

Pin Configuration

21

22

23

24

25

26

27

28

29

30

40 39

38 37 36 35

34

31

32

33

4142

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70

69

68

67

63 64 65 66

61 62

71

72 73

74 75 76 77 78 79 80

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

1

LRCK

PCMD

BCK

EMPH

XV

DD

XTAI

XTAO

XV

SS

AVDD1

AOUT1

AIN1

LOUT1

AV

SS1

AV

SS2

LOUT2

AIN2

AOUT2

AV

DD2

RMUT

LMUT

SE FE

VC XTSL TES1 TEST V

SS

FRDR

COUT

FFDR TRDR TFDR SRDR SFDR SSTP MDP LOCK

MIRR

DOUT

V

DD

V

SS

FILI

CLTV

AV

SS

3

TE

ASYO

AV

DD

0

IGEN

AV

SS

0

ADIO

RFDC

AV

DD

3

PCO

BIAS

ASYI

FILO

RFAC

CE

SQCK

XLAT

SENS

DATA

XRST

SYSM

CLOK

V

DD

SQSO

SCLK

SCOR

ATSK

SPOA

SPOB

XLON

WFCK

XUGF

XPCK

GFS

C2PO

FOK DFCT

– 4 –

CXD3017Q

Pin Description

No.

Symbol I/O

Output values

Description

Sub Q 80-bit, PCM peak and level data outputs. CD TEXT data output. SQSO readout clock input. System reset. Reset when low. Mute input. Muted when high. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. SENS output to CPU. SENS serial data readout clock input. Digital power supply. Anti-shock input/output. Microcomputer extension interface (input A) Microcomputer extension interface (input B) Microcomputer extension interface (output) WFCK output. XUGF output. MINT1 or RFCK is output by switching with the command. XPCK output. MNT0 is output by switching with the command. GFS output. MNT3 or XROF is output by switching with the command. C2PO output. GTOP is output by switching with the command. Outputs a high signal when either subcode sync S0 or S1 is detected. Track count signal input/output. Mirror signal input/output. Defect signal input/output. Focus OK signal input/output. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS

is low eight consecutive samples, this pin outputs low. Or input when LKIN = 1. Spindle motor servo control output. Disc innermost track detection signal input. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. Digital GND.

1, 0

—

1, 0

1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0

1, 0

1, Z, 0

1, 0 1, 0 1, 0 1, 0 1, 0 1, 0

—

O

I I I I I I

O

I

—

I/O

I

I O O O O O O O

I/O I/O I/O I/O

I/O

O

I O O O O O O

—

SQSO SQCK XRST SYSM DATA XLAT CLOK SENS SCLK VDD ATSK SPOA SPOB XLON WFCK XUGF XPCK GFS C2PO SCOR COUT MIRR DFCT FOK

LOCK MDP

SSTP SFDR SRDR TFDR TRDR FFDR FRDR VSS

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

25 26

27 28 29 30 31 32 33 34

– 5 –

CXD3017Q

Pin No.

Symbol I/O

Output values

Description

Test pin. Normally, GND. Test pin. Normally, GND. Crystal selection input. Low when the crystal is 16.9344MHz; high when the

crystal is 33.8688MHz. Center voltage input. Focus error signal input. Sled error signal input. Tracking error signal input. Center servo analog input. RF signal input. Test pin. No connected. Analog GND. Operational amplifier constant current input. Analog power supply. EFM full-swing output. (low = Vss, high = VDD) Asymmetry comparator voltage input. Asymmetry circuit constant current input. EFM signal input. Analog GND. Multiplier VCO1 control voltage input. Master PLL filter output. (slave = digital PLL) Master PLL filter input. Master PLL charge pump output. Analog power supply. Digital GND. Digital power supply. Digital Out output. D/A interface. LR clock output f = Fs. D/A interface. Serial data output. (two's complement, MSB first) D/A interface. Bit clock output. Outputs a high signal when the playback disc has emphasis, and a low

signal when there is no emphasis. Master clock power supply. Crystal oscillation circuit input. Master clock is externally input from this pin. Crystal oscillation circuit output. Master clock GND.

Analog

—

1, 0

—

Analog

1, Z, 0

— —

— 1, 0 1, 0 1, 0 1, 0

1, 0

—

I I

I I I I I

O

—

I

—

O

I I I

—

I

O

I

O — — —

O

O —

I

O —

TEST TES1

XTSL VC

FE SE TE CE RFDC ADIO AVSS0 IGEN AVDD0 ASYO ASYI BIAS RFAC AVSS3 CLTV FILO FILI PCO AVDD3 VSS VDD DOUT LRCK PCMD BCK

EMPH XVDD

XTAI XTAO XVSS

35 36

37 38

39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

64 65

66 67 68

– 6 –

CXD3017Q

Pin No.

Symbol I/O

Output values

Description

Analog power supply. L ch analog output. L ch operational amplifier input. L ch LINE output. Analog GND. Analog GND. R ch LINE output. R ch operational amplifier output. R ch analog output. Analog power supply. R ch zero detection flag. L ch zero detection flag.

—

— —

— 1, 0 1, 0

—

O

I

O — —

O

I

O —

O

AVDD1 AOUT1 AIN1 LOUT1 AVSS1 AVSS2 LOUT2 AIN2 AOUT2 AVDD2 RMUT LMUT

69 70 71 72 73 74 75 76 77 78 79 80

Notes) • PCMD is a MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)

• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before

sync protection.

• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide.

• The GFS signal goes high when the frame sync and the insertion timing match.

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.

• C2PO represents the data error status.

• XROF is generated when the 16K RAM exceeds the ±4F jitter margin.

Monitor Pin Output Combinations

Command bit

Output data

MTSL1

0 0 1

0 1 0

XUGF MNT1 RFCK

XPCK MNT0 XPCK

GFS

MNT3

XROF

C2PO C2PO GTOP

MTSL0

– 7 –

CXD3017Q

Electrical Characteristics

1. DC Characteristics

(VDD = AVDD = 3.3 ± 0.3V, Vss = AVss = 0V, Topr = –20 to +75°C)

Item

High level Low level High level Low level High level Low level

High level Low level High level Low level

Input voltage (1)

Input voltage (2)

Input voltage (3)

Input voltage (4)

Output voltage (1)

Output voltage (2)

Input leak current (1) Input leak current (2) Input leak current (3)

Input leak current (4)

Tri-state pin output leak current

VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VIN4 VOH1 VOL1 VOH2 VOL2

ILI1 ILI2 ILI3

ILI4

ILO

0.7VDD

0.8VDD

VSS

VDD – 0.4

0

VDD – 0.5

0 –10 –10 –40

–40

0.2VDD

0.2VDD VDD VDD

0.4

VDD

0.4 10 10 40

40

V V V V V V V V V V

V µA µA µA

µA

Conditions Min. Typ.

Max.

Unit

Applicable pins

VI ≤ 5.5V

VI ≤ 5.5V Schmitt input

Analog input IOH = –4mA

IOL = 4mA IOH = –0.28mA

IOH = 0.36mA VI = Vss or

VDD VI = 0 to 5.5V VI = Vss or

VDD VI = 0.25VDD

to 0.75VDD VI = Vss or

VDD

∗1, ∗9

∗2

∗3

∗4, ∗5 ∗6, ∗8,

∗9

∗7

∗1, ∗4 ∗2, ∗3 ∗9

∗5

∗8

1-1. Applicable pins and classification

∗1

CMOS level input pins (1):

TEST, TES1

∗2

CMOS level input pins (2):

SYSM, DATA, XLAT, SSTP, XTSL

∗3

CMOS Schmitt input pins:

SQCK, XRST, CLOK, SCLK, SPOA, SPOB

∗4

Analog input pins (1):

ASYI, CLTV, FILI

∗5

Analog input pins (2):

VC, FE, SE, TE, CE, RFDC

∗6

Normal output pins (1):

SQSO, XLON, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, SFDR, SRDR, TFDR, TRDR, FRDR, ASYO, DOUT, LRCK, PCMD, BCK, EMPH, RMUT, LMUT

∗7

Normal output pin (2):

FILO

∗8

Tri-state output pins:

SENS, MDP, FFDR, PCO

∗9

Normal input/output pins:

ATSK, COUT, MIRR, DFCT, FOK, LOCK

Note) When the external pull-down resistors are connected to the pins ∗2and ∗3, the resistance applied to

these pins should be 5kΩ or less in total.

– 8 –

CXD3017Q

2. AC Characteristics

(1) XTAI pin

(a) When using self-excited oscillation

(Topr = –20 to +75°C, VDD = AVDD = 3.3 ± 0.3V)

(b) When inputting pulses to XTAI pin

(Topr = –20 to +75°C, VDD = AVDD = 3.3 ± 0.3V)

(c) When inputting sine waves to XTAI pin via a capacitor

(Topr = –20 to +75°C, VDD = AVDD = 3.3 ± 0.3V)

Oscillation frequency

fMAX 7

34

MHz

Item Symbol Min. Typ. Max.

Unit

High level pulse width

tWHX

13 500

ns

Low level pulse width

tWLX

13 500

ns

Pulse cycle

tCX

26 1000

ns

Input high level VIHX

0.7VDD

V

Input low level VILX 0.2VDD

V

Rise time, fall time

tR, tF

10

ns

Item Symbol Min. Typ. Max. Unit

Input amplitude VI 0.5VDD VDD + 0.3 Vp-p

Item Symbol Min. Typ. Max. unit

tR tF

tWHX

tWLX

tCK

VILX

VIHX × 0.1

V

IHX × 0.9

V

IHX

XTAI

V

DD/2

– 9 –

CXD3017Q

(2) CLOK, DATA, XLAT and SQCK pin

(VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width SQCK frequency SQCK pulse width

fCK

tWCK tSU tH tD tWL

fT

tWT

750 300 300 300 750

750

Note)

0.65

Note)

MHz

ns ns ns ns ns

MHz

ns

Item Symbol Min. Typ. Max. Unit

tWCK tWCK

1/fCK

tH

tSU

tWL

tD

1/fT

tWT tWT

tH

tSU

CLOK

DATA

XLAT

SQCK

SQSO

Note) In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCK maximum

operating frequency is 300kHz and its minimum pulse width is 1.5µs.

– 10 –

CXD3017Q

(4) COUT, MIRR and DFCT pins

Operating frequency

(VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)

COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency

fCOUT fMIRR fDFCTH

40 40

5

kHz kHz kHz

∗1 ∗2 ∗3

Item Symbol Min. Typ. Max. Unit

Conditions

∗

1

When using a high-speed traverse TZC.

∗

2

When the RF signal continuously satisfies the following conditions during the above traverse.

• A = 0.11VDD to 0.23VDD

• ≤ 25%

∗

3

During complete RF signal omission. When settings related to DFCT signal generation are Typ.

(3) SCLK pin

SCLK frequency SCLK pulse width Delay time

fSCLK

tSPW tDLS

31.3 15

16 MHz

ns µs

Item Symbol Min. Typ. Max. Unit

tSPWtDLS

1/fSCLK

MSB LSB

XLAT

SCLK

Serial Read Out Data

(SENS)

. . .

A

B

A + B

– 11 –

CXD3017Q

1-bit DAC and LPF Block Analog Characteristics

Analog characteristics (VDD = AVDD = 3.3V, VSS = AVSS = 0V, Ta = 25°C)

Fs = 44.1kHz in all cases. The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.

Note) The external load capacitance connect to the LPF block should be 30pF or less in total.

LPF external circuit diagram

Block diagram of analog characteristics measurement

Item

Total harmonic distortion

Signal-to-noise ratio

Symbol

THD

S/N

Conditions

1kHz, 0dB data

Crystal

1kHz, 0dB data when AMUT ON (Using A-weighting filter)

384Fs 768Fs 384Fs 768Fs

98 98

0.0080

0.0080 102 102

0.0120

Min.

Typ.

Max.

Unit

%

dB

Audio Analyzer

SHIBASOKU (AM51A)

100k

22µ

330pF

27k

68pF

AOUT1 (2)

AIN1 (2)

LOUT1 (2)

Audio Analyzer

CXD3017Q

Rch A

Lch B

DATA RF

TEST DISC

768Fs/384Fs

(VDD = AVDD = 3.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Output voltage Load resistance Load capacitance

VOUT RL CL

30

∗1 ∗1

∗1, ∗2

Vrms

kΩ

pF

Item Symbol

20

Min.

Max.

0.71

Typ.

Applicable pins

Unit

∗

Measurement is conducted for the LPF external circuit diagram with the sine wave output of 1kHz and 0dB.

Applicable pins

∗1

LOUT1, LOUT2

∗2

AOUT1, AOUT2

– 12 –

CXD3017Q

Contents

§1. CPU Interface

§1-1. CPU Interface Timing ........................................................................................................................ 13

§1-2. CPU Interface Command Table ........................................................................................................ 13

§1-3. CPU Command Presets .................................................................................................................... 24

§1-4. Description of SENS Signals and Commands ................................................................................... 30

§2. Subcode Interface

§2-1. 80-bit Sub Q Readout ........................................................................................................................ 46

§3. Description of Other Functions

§3-1. Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 49

§3-2. Frame Sync Protection ......................................................................................................................50

§3-3. Error Correction ................................................................................................................................. 50

§3-4. DA Interface ....................................................................................................................................... 51

§3-5. Digital Out .......................................................................................................................................... 53

§3-6. Servo Auto Sequence ....................................................................................................................... 53

§3-7. Digital CLV ......................................................................................................................................... 60

§3-8. CD-DSP Block Playback Speed ........................................................................................................61

§3-9. DAC Block Playback Speed .............................................................................................................. 61

§3-10. Description of DAC Block Functions .................................................................................................. 62

§3-11. LPF Block .......................................................................................................................................... 65

§3-12. Asymmetry Compensation ................................................................................................................ 66

§3-13. CD TEXT Data Demodulation ........................................................................................................... 67

§4. Description of Servo Signal Processing System Functions and Commands

§4-1. General Description of Servo Signal Processing System .................................................................. 69

§4-2. Digital Servo Block Master Clock (MCK) ...........................................................................................70

§4-3. DC Offset Cancel [AVRG Measurement and Compensation] ........................................................... 71

§4-4. E:F Balance Adjustment Function ..................................................................................................... 72

§4-5. FCS Bias Adjustment Function .......................................................................................................... 72

§4-6. AGCNTL Function ............................................................................................................................. 74

§4-7. FCS Servo and FCS Search ............................................................................................................. 76

§4-8. TRK and SLD Servo Control ............................................................................................................. 77

§4-9. MIRR and DFCT Signal Generation ..................................................................................................78

§4-10. DFCT Countermeasure Circuit .......................................................................................................... 79

§4-11. Anti-Shock Circuit .............................................................................................................................. 79

§4-12. Brake Circuit ...................................................................................................................................... 80

§4-13. COUT Signal ..................................................................................................................................... 81

§4-14. Serial Readout Circuit ........................................................................................................................ 81

§4-15. Writing to the Coefficient RAM .......................................................................................................... 82

§4-16. PWM Output ...................................................................................................................................... 82

§4-17. Servo Status Changes Produced by the LOCK Signal ..................................................................... 83

§4-18. Description of Commands and Data Sets ......................................................................................... 83

§4-19. List of Servo Filter Coefficients ........................................................................................................ 107

§4-20. Filter Composition ............................................................................................................................ 109

§4-21. TRACKING and FOCUS Frequency Response .............................................................................. 115

§5. Application Circuit .................................................................................................................................. 116

Explanation of abbreviations AVRG: Average

AGCNTL: Auto gain control FCS: Focus TRK: Tracking SLD: Sled DFCT: Defect

– 13 –

CXD3017Q

§1. CPU Interface

§1-1. CPU Interface Timing

• CPU interface

This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below.

• The internal registers are initialized by a reset when XRST = 0.

Note) Be sure to set SQCK to high when XLAT is low.

§1-2. CPU Interface Command Table

Total bit length for each register

Register

0 to 2

3

4 to 6

7 8 9 A B C D E

8 bits

8 to 24 bits

8 bits 20 bits 28 bits 24 bits 28 bits 16 bits

8 bits 16 bits 20 bits

Total bit length

750ns or more

D18 D19 D20 D21 D22 D23

750ns or more

Valid

CLOK

DATA

XLAT

Registers

D0 D1

– 14 –

CXD3017Q

FOCUS SERVO ON

(FOCUS GAIN

NORMAL)

FOCUS SERVO ON

(FOCUS GAIN

DOWN)

FOCUS SERVO OFF,

0V OUT

FOCUS SERVO OFF,

FOCUS SEARCH

VOLTAGE OUT

FOCUS SEARCH

VOLTAGE DOWN

FOCUS SEACH

VOLTAGE UP

ANTI SHOCK ON

ANTI SHOCK OFF

BRAKE ON

BRAKE OFF

TRACKING GAIN

NORMAL

TRACKING GAIN UP

FILTER SELECT 1

TRACKING GAIN UP

FILTER SELECT 2

1

0

1

0

—

0

1

—

0

—

1

0

—

0

1

—

0

1

—

0

1

—

1

0

—

0

1

0 0 0 0

0 0 0 1

FOCUS

CONTROL

TRACKING

CONTROL

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Command Table ($0X to 1X)

—: Don’t care

– 15 –

CXD3017Q

TRACKING SERVO OFF

TRACKING SERVO ON

FORWARD TRACK JUMP

REVERSE TRACK JUMP

SLED SERVO OFF

SLED SERVO ON

FORWARD SLED MOVE

REVERSE SLED MOVE

SLED KICK LEVEL

(±1 × basic value) (Default)

SLED KICK LEVEL

(±2

×

basic value)

SLED KICK LEVEL

(±3

×

basic value)

SLED KICK LEVEL

(±4

×

basic value)

0

1

—

0

1

0

1

0

1

—

0

1

0

1

—

0

1

—

0

1

0

1

—

2

3

0 0 1 0

0 0 1 1

TRACKING

MODE

SELECT

Register

Command

Address

D23 to D20

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

—: Don’t care

Command Table ($2X to 3X)

– 16 –

CXD3017Q

Command Table ($340X)

KRAM DATA (K00)

SLED INPUT GAIN

KRAM DATA (K01)

SLED LOW BOOST FILTER A-H

KRAM DATA (K02)

SLED LOW BOOST FILTER A-L

KRAM DATA (K03)

SLED LOW BOOST FILTER B-H

KRAM DATA (K04)

SLED LOW BOOST FILTER B-L

KRAM DATA (K05)

SLED OUTPUT GAIN

KRAM DATA (K06)

FOCUS INPUT GAIN

KRAM DATA (K07)

SLED AUTO GAIN

KRAM DATA (K08)

FOCUS HIGH CUT FILTER A

KRAM DATA (K09)

FOCUS HIGH CUT FILTER B

KRAM DATA (K0A)

FOCUS LOW BOOST FILTER A-H

KRAM DATA (K0B)

FOCUS LOW BOOST FILTER A-L

KRAM DATA (K0C)

FOCUS LOW BOOST FILTER B-H

KRAM DATA (K0D)

FOCUS LOW BOOST FILTER B-L

KRAM DATA (K0E)

FOCUS PHASE COMPENSATE FILTER A

KRAM DATA (K0F)

FOCUS DEFECT HOLD GAIN

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 0 0SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 17 –

CXD3017Q

Command Table ($341X)

KRAM DATA (K10)

FOCUS PHASE COMPENSATE FILTER B

KRAM DATA (K11)

FOCUS OUTPUT GAIN

KRAM DATA (K12)

ANTI SHOCK INPUT GAIN

KRAM DATA (K13)

FOCUS AUTO GAIN

KRAM DATA (K14)

HPTZC / AUTO GAIN HIGH PASS FILTER A

KRAM DATA (K15)

HPTZC / AUTO GAIN HIGH PASS FILTER B

KRAM DATA (K16)

ANTI SHOCK HIGH PASS FILTER A

KRAM DATA (K17)

HPTZC / AUTO GAIN LOW PASS FILTER B

KRAM DATA (K18)

FIX

KRAM DATA (K19)

TRACKING INPUT GAIN

KRAM DATA (K1A)

TRACKING HIGH CUT FILTER A

KRAM DATA (K1B)

TRACKING HIGH CUT FILTER B

KRAM DATA (K1C)

TRACKING LOW BOOST FILTER A-H

KRAM DATA (K1D)

TRACKING LOW BOOST FILTER A-L

KRAM DATA (K1E)

TRACKING LOW BOOST FILTER B-H

KRAM DATA (K1F)

TRACKING LOW BOOST FILTER B-L

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 0 1SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 18 –

CXD3017Q

Command Table ($342X)

KRAM DATA (K20)

TRACKING PHASE COMPENSATE FILTER A

KRAM DATA (K21)

TRACKING PHASE COMPENSATE FILTER B

KRAM DATA (K22)

TRACKING OUTPUT GAIN

KRAM DATA (K23)

TRACKING AUTO GAIN

KRAM DATA (K24)

FOCUS GAIN DOWN HIGH CUT FILTER A

KRAM DATA (K25)

FOCUS GAIN DOWN HIGH CUT FILTER B

KRAM DATA (K26)

FOCUS GAIN DOWN LOW BOOST FILTER A-H

KRAM DATA (K27)

FOCUS GAIN DOWN LOW BOOST FILTER A-L

KRAM DATA (K28)

FOCUS GAIN DOWN LOW BOOST FILTER B-H

KRAM DATA (K29)

FOCUS GAIN DOWN LOW BOOST FILTER B-L

KRAM DATA (K2A)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER A

KRAM DATA (K2B)

FOCUS GAIN DOWN DEFECT HOLD GAIN

KRAM DATA (K2C)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER B

KRAM DATA (K2D)

FOCUS GAIN DOWN OUTPUT GAIN

KRAM DATA (K2E)

Not used

KRAM DATA (K2F)

Not used

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 1 0SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 19 –

CXD3017Q

Command Table ($343X)

KRAM DATA (K30)

SLED INPUT GAIN (when SFSK = 1 TG up2)

KRAM DATA (K31)

ANTI SHOCK LOW PASS FILTER B

KRAM DATA (K32)

Not used

KRAM DATA (K33)

ANTI SHOCK HIGH PASS FILTER B-H

KRAM DATA (K34)

ANTI SHOCK HIGH PASS FILTER B-L

KRAM DATA (K35)

ANTI SHOCK FILTER COMPARATE GAIN

KRAM DATA (K36)

TRACKING GAIN UP2 HIGH CUT FILTER A

KRAM DATA (K37)

TRACKING GAIN UP2 HIGH CUT FILTER B

KRAM DATA (K38)

TRACKING GAIN UP2 LOW BOOST FILTER A-H

KRAM DATA (K39)

TRACKING GAIN UP2 LOW BOOST FILTER A-L

KRAM DATA (K3A)

TRACKING GAIN UP2 LOW BOOST FILTER B-H

KRAM DATA (K3B)

TRACKING GAIN UP2 LOW BOOST FILTER B-L

KRAM DATA (K3C)

TRACKING GAIN UP PHASE COMPENSATE FILTER A

KRAM DATA (K3D)

TRACKING GAIN UP PHASE COMPENSATE FILTER B

KRAM DATA (K3E)

TRACKING GAIN UP OUTPUT GAIN

KRAM DATA (K3F)

Not used

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 1 1SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 20 –

CXD3017Q

Command Table ($344X)

KRAM DATA (K40)

TRACKING HOLD FILTER INPUT GAIN

KRAM DATA (K41)

TRACKING HOLD FILTER A-H

KRAM DATA (K42)

TRACKING HOLD FILTER A-L

KRAM DATA (K43)

TRACKING HOLD FILTER B-H

KRAM DATA (K44)

TRACKING HOLD FILTER B-L

KRAM DATA (K45)

TRACKING HOLD FILTER OUTPUT GAIN

KRAM DATA (K46)

TRACKING HOLD INPUT GAIN (when THSK = 1 TG up2)

KRAM DATA (K47)

Not used

KRAM DATA (K48)

FOCUS HOLD FILTER INPUT GAIN

KRAM DATA (K49)

FOCUS HOLD FILTER A-H

KRAM DATA (K4A)

FOCUS HOLD FILTER A-L

KRAM DATA (K4B)

FOCUS HOLD FILTER B-H

KRAM DATA (K4C)

FOCUS HOLD FILTER B-L

KRAM DATA (K4D)

FOCUS HOLD FILTER OUTPUT GAIN

KRAM DATA (K4E)

Not used

KRAM DATA (K4F)

Not used

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 1 0 0SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 21 –

CXD3017Q

PFOK, RFAC

Booster Surf Brake

Booster

DFCT

FCS Bias Limit

FCS Bias Data

Traverse Center Data

3

1

0

1

0

1

0

1

0

1

0

1

0

SFBK1

THBON

IDFS3

1

0

SFBK2

FHBON

IDFS2

0

1

0

PFOK1

0

TLB10N

IDFS1

FBL9

FB9

TV9

PFOK0

0

FLB1ON

IDFS0

FBL8

FB8

TV8

0

TLB2ON

0

FBL7

FB7

TV7

0

FBL6

FB6

TV6

0

HBST1

IDFT1

FBL5

FB5

TV5

MRS

0

HBST0

IDFT0

FBL4

FB4

TV4

MRT1

0

LB1S1

0

FBL3

FB3

TV3

MRT0

0

LB1S0

0

FBL2

FB2

TV2

0

LB2S1

0

FBL1

FB1

TV1

0

LB2S0

INVRFDC

—

TV0

SELECT

Register

Command

Address 1 Address 2

D23 to D20

Address 3

D15

D15 D14

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2

Data 3Data 2Data 1Address 3

D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

Command Table ($348X to 34FX)

0 0 1 1

D19 to D16

0 1 0 0

– 22 –

CXD3017Q

0 0 1 1

1

0

1

0

1

System GAIN

FOCUS SEARCH SPEED/

VOLTAGE/AUTO GAIN

DTZC/TRACK JUMP

VOLTAGE/AUTO GAIN

FZSL/SLED MOVE/

Voltage/AUTO GAIN

LEVEL/AUTO GAIN/

DFSW/ (Initialize)

SERIAL DATA READ

MODE/SELECT

FOCUS BIAS

Operation for MIRR/

DFCT/FOK

TZC/COUT

BOTTOM/MIRR

SLED FILTER

Filter

Others

3

0 0 1 1

1

1 1 1

0 0

0

SYG3 SYG2

SYG1 SYG0

FI

FZB3

FI

FZB2

FI

FZB1

FI

FZB0

FI

FZA3

FI

FZA2

FI

FZA1

FI

FZA0

0

1

0

1

0

1

0

1

FT1

0

FZSH

VCLM

DAC

0

SFO2

FT0

DTZC

FZSL

VCLC

SD6

FBON

SFO1

FS5

TJ5

SM5

FLM

SD5

0

SDF2

FS4

TJ4

SM4

FLC0

SD4

0

SDF1

FS3

TJ3

SM3

RFLM

SD3

0

MAX2

FS2

TJ2

SM2

RFLC

SD2

0

MAX1

FS1

TJ1

SM1

AGF

SD1

FI

FZC

SFOX

FS0

TJ0

SM0

AGT

SD0

0

BTF

FTZ

SFJP

AGS

DFSW

0

FPS1

D2V2

FG6

TG6

AGJ

LKSW

0

FPS0

D2V1

FG5

TG5

AGGF

TBLM

0

TPS1

D1V2

FG4

TG4

AGGT

TCLM

0

TPS0

D1V1

FG3

TG3

AGV1

FLC1

0

SVDA

0

FG2

TG2

AGV2

TLC2

0

FG1

TG1

AGHS

TLC1

0

FG0

TG0

AGHT

TLC0

0

1

0

1

F1NM

0

F1DM

AGG4

F3NM

XT4D

F3DM

XT2D

T1NM

AGSD

T1UM

DRR2

T3NM

DRR1

T3UM

DRR0

DFIS

0

TLCD

ASFG

0

FTQ

LKIN

1

COIN

SRO1

MDFI

0

MIRI

AGHF

XT1D

ASOT

1

0

1

COSS

SFID

COTS

SFSK

CETZ

THID

CETF

THSK

COT2

ABEF

COT1

TLD2

MOT2

TLD1

0

TLD0

BTS1

0

BTS0

0

MRC1

0

MRC0

0

SELECT

Register

Command

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15 D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

Address

D23 to D20 D19 D18 D17 D16

Data 1

D15 D14 D13 D12

Data 2

D11 D10 D9 D8

Data 3

D7 D6 D5 D4

Data 4

D3 D2 D1 D0

Command Table ($35X to 3FX)

—: Don’t care

– 23 –

CXD3017Q

Instruction Table

Register

4

5

6

7

8

9

A

B

C

D

E

Auto sequence

Blind (A, E),

Overflow (C)

Brake (B)

Kick (D)

Auto sequence

(N) track jump

count

Mode

specification

Function

specification

Audio CTRL

Sleep setting

Serial bus

CTRL

Spindle servo

coefficient

setting

CLV CTRL

CLV mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

2048

VCO

SEL1

0

ADCPS

TRMI

—

1

0

—

1024

0

DSP

SLEEP

TRMO

—

1

0

—

512

SOCT

0

OPSL20OPSL2

1

DSSP

SLEEP

MTSL1

—

1

0

—

256

0

EMPH

ASYM

SLEEP

MTSL0

—

0

—

128

KSL3

OPSL10OPSL1

1

SMUT

0

—

0

—

64

KSL2

MCSL

AD10

LPF

SLEEP

0

—

0

—

32

1

0

AD9

0

—

0

—

16

0

AD8

0

—

0

—

8

0

ZDPL

AD7

—

0

—

4

VCO1

CS0

ZMUT

AD6

—

0

—

2

0

—

0

AD5

—

0

—

1

0

—

0

AD4

—

0

—

0

—

0

AD3

—

0

—

DCOF

AD2

—

0

—

0

AD1

—

0

—

DAC

PWDN

AD0

—

TXON

—

FMUT

—

TXOUT

—

LRWO

—

OUTL1

—

BSBST

—

OUTL0

—

BBSL

—

AS3

0.18ms

0.36ms

11.6ms

32768

CDROM

0

1

SL1

Gain

MDP1

0

CM3

AS2

0.09ms

0.18ms

5.8ms

16384

DOUT

Mute

DSPB

ON/OFF

DSPB

ON/OFF

0

1

SL0

Gain

MDP0

TB

CM2

AS1

0.05ms

0.09ms

2.9ms

8192

DOUT

ON/OFF

0

Mute

0

CPUSR

Gain

MDS1

TP

CM1

AS0

0.02ms

0.05ms

1.45ms

4096

WSEL

0

ATT

1

0

Gain

MDS0

Gain

CLVS

CM0

Command

Address

D3 D2 D1 D0

Data 1

D3 D2 D1 D0

Data 2

D3 D2 D1 D0

Data 3

D3 D2 D1 D0

Data 4

D3 D2 D1 D0

Data 5

D3 D2 D1 D0

Data 6

D3 D2 D1 D0

– 24 –

CXD3017Q

FOCUS SERVO OFF,

0V OUT

TRACKING GAIN UP

FILTER SELECT 1

TRACKING SERVO OFF

SLED SERVO OFF

SLED KICK LEVEL

(±1 × basic value) (Default)

KRAM DATA

($3400XX to $344fXX)

0

1

0

—

0

1

2

0 0 0 0

0 0 0 1

0 0 1 0

FOCUS

CONTROL

TRACKING

CONTROL

TRACKING

MODE

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Register

Command

3 SELECT

Address

D23 to D20

0 0 1 1

0 0 1 1 0 1 0 0 0 See "Coefficient ROM Preset Values Table".

0 0 0 0 — — — — — — — — — — — — — — — —

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D0 D0

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15 D14 D13 D12

Address 3

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D0 D0

§1-3. CPU Command Presets

Command Preset Table ($0X to 34X)

—: Don’t care

– 25 –

CXD3017Q

Command Preset Table ($348X to 34FX)

PFOK, RFAC

Booster Surf Brake

Booster

Servo DAC output

DFCT

FCS Bias Limit

FCS Bias Data

Traverse Center Data

3

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

0

SELECT

Register

Command

Address 1

Address 2

D23 to D20

Address 3

D15

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2

Data 3Data 2Data 1Address 3

D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

0 0 1 1

D19 to D16

0 1 0 0

—: Don’t care

– 26 –

CXD3017Q

0 0 1 1

1

0

1

0

1

System GAIN

FOCUS SEARCH SPEED/

VOLTAGE AUTO GAIN

DTZC/TRACK JUMP

VOLTAGE AUTO GAIN

FZSL/SLED MOVE/

Voltage/AUTO GAIN

LEVEL/AUTO GAIN/

DFSW/ (Initialize)

SERIAL DATA READ

MODE/SELECT

FOCUS BIAS

Operation for MIRR/

DFCT/FOK

TZC/COUT

BOTTOM/MIRR

SLED FILTER

3

0 0 1 1

1

1 1 1

0

1 0

0

0 0

0

0 0 0

0 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Filter

Others

1

0

1

0

1

0

SELECT

Register

Command

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15 D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

Address

D23 to D20 D19 D18 D17 D16

Data 1

D15 D14 D13 D12

Data 2

D11 D10 D9 D8

Data 3

D7 D6 D5 D4

Data 4

D3 D2 D1 D0

Command Preset Table ($35X to 3FX)

—: Don’t care

– 27 –

CXD3017Q

Reset Initialization

Register

4

5

6

7

8

9

A

B

C

D

E

Auto sequence

Blind (A, E),

Overflow (C)

Brake (B),

Kick (D)

Auto sequence (N)

track jump

count setting

MODE

specification

Function

specification

Audio CTRL

Sleep setting

Serial bus

CTRL

Spindle servo

coefficient setting

CLV CTRL

CLV mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

0

—

1

0

—

0

1

—

1

0

—

0

—

1

0

—

1

0

—

0

—

0

—

0

—

0

1

0

—

0

—

0

1

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

Command

Address

D3 D2 D1 D0

Data 1

D3 D2 D1 D0

Data 2

D3 D2 D1 D0

Data 3

D3 D2 D1 D0

Data 4

D3 D2 D1 D0

Data 5

D3 D2 D1 D0

Data 6

D3 D2 D1 D0

– 28 –

CXD3017Q

ADDRESS

K00 K01 K02 K03 K04 K05 K06 K07 K08

K09 K0A K0B K0C K0D K0E K0F

E0 81 23 7F 6A 10 14 30 7F 46 81

1C

7F 58 82 7F

SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19 K1A K1B K1C K1D K1E K1F

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29 K2A K2B K2C K2D K2E K2F

4E 32 20 30 80 77 80 77 00 F1 7F 3B 81 44 7F 5E

FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix

∗

TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L

82 44 18 30 7F 46 81 3A 7F 66 82 44 4E 1B 00 00

TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN Not used Not used

DATA CONTENTS

∗

Fix indicates that normal preset values should be used.

– 29 –

CXD3017Q

ADDRESS

K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K3A

K3B K3C K3D K3E K3F

80 66 00 7F 6E 20 7F 3B 80 44 7F 77 86

0D

57 00

SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B Not used ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B TRACKING GAIN UP2 LOW BOOST FILTER A-H TRACKING GAIN UP2 LOW BOOST FILTER A-L TRACKING GAIN UP2 LOW BOOST FILTER B-H TRACKING GAIN UP2 LOW BOOST FILTER B-L TRACKING GAIN UP PHASE COMPENSATE FILTER A TRACKING GAIN UP PHASE COMPENSATE FILTER B TRACKING GAIN UP OUTPUT GAIN Not used

K40

K41

K42

K43

K44

K45

K46

K47

K48

K49 K4A K4B K4C K4D K4E K4F

04 7F 7F 79 17

6D

00 00 02 7F 7F 79 17 54 00 00

TRACKING HOLD FILTER INPUT GAIN TRACKING HOLD FILTER A-H TRACKING HOLD FILTER A-L TRACKING HOLD FILTER B-H TRACKING HOLD FILTER B-L TRACKING HOLD FILTER OUTPUT GAIN TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is accessed with THSK = 1.) Not used FOCUS HOLD FILTER INPUT GAIN FOCUS HOLD FILTER A-H FOCUS HOLD FILTER A-L FOCUS HOLD FILTER B-H FOCUS HOLD FILTER B-L FOCUS HOLD FILTER OUTPUT GAIN Not used Not used

DATA CONTENTS

– 30 –

CXD3017Q

Description of SENS Signals

Low while the auto sequencer is in operation, high when the operation terminates. Outputs the same signal as the FOK pin.

High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks with frequeny division ratio set by $B. High when $B is

latched, and toggles each time COUT is counted just for the frequency diviison ratio set by $B.

Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter.

XBUSY FOK GFS

COUT

OV64

SENS output

§1-4. Description of SENS Signals and Commands SENS output

Notes) • The SENS output can be read from the SQSO pin when SOCT = 0, SL1 = 1 and SL0 = 0.

$38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases.

• The signals output by $0X to $3X in the table above cannot be read during the auto sequence operation.

Microcomputer serial register (latching not required)

$0X $1X $2X $30 to 37 $38 $38 $3904 $3908 $390C $391C $391D $391F $3A $3B to 3F $4X $5X $6X, 7X, 8X, 9X $AX $BX $CX $DX $EX $FX

FZC

AS (Anti Shock)

TZC

SSTP

AGOK

XAVEBSY TE Avrg Reg. FE Avrg Reg.

VC Avrg Reg.

TRVSC Reg.

FB Reg.

RFDC Avrg Reg.

FBIAS count STOP

SSTP

XBUSY

FOK

0

GFS

0

COUT frequency division

0

OV64

0

— — — — —

— 9 bit 9 bit 9 bit 9 bit 9 bit 8 bit

—

SENS output Output data length

– 31 –

CXD3017Q

The meaning of the data for each address is explained below. $4X commands

RXF = 0 FORWARD RXF = 1 REVERSE

• When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.

• When the Track jump/move commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is

interrupted.

$5X commands

Auto sequence timer setting Setting timers: A, E, C, B

Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset)

A = E = C = 0.11ms B = 0.23ms

$6X commands

Auto sequence timer setting Setting timer: D

Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset)

D = 10.15ms

$7X commands

Auto sequence track jump/move count setting (N)

This command is used to set N when a 2N-track jump and an N-track move are executed for auto sequence.

• The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system.

• The number of tracks jumped is counted according to the COUT signals.

CANCEL FOCUS-ON 1 TRACK JUMP 10 TRACK JUMP 2N TRACK JUMP N TRACK MOVE

0 0 1 1 1 1

0 1 0 0 1 1

0 1 0 1 0 1

0

1 RXF RXF RXF RXF

Command

AS3

AS2

AS1

AS0

Blind (A, E), Over flow (C) Brake (B)

0.18ms

0.36ms

0.09ms

0.18ms

0.05ms

0.09ms

0.02ms

0.05ms

Command

D3

D2

D1

D0

KICK (D)

11.6ms

5.8ms

2.9ms

1.45ms

Command

Data 1 Data 2

Data 3 Data 4

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

2152142132122112102928272625242322212

0

Auto sequence track jump count setting

D3

D2

D1

D0

– 32 –

CXD3017Q

Command

D3

CDROM

DOUT

Mute

DOUT

ON/OFF

WSEL

VCO

SEL1

0

SOCT 0 KSL3 KSL2 1 0

D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Data 1

Data 2

MODE specification

Data 3

Command bit

C2PO timing

CDROM = 1

CDROM = 0

See Timing Chart 1-1.

CDROM mode; average value interpolation and pre-value hold are not performed.

Audio mode; average value interpolation and pre-value hold are performed.

Processing

Command bit DOUT Mute = 1 DOUT Mute = 0

Digital Out output is muted. (DA output is not muted.) When no other mute conditions are set, Digital Out output is not muted.

Processing

$8X commands

Command bit

DOUT ON/OFF = 1 DOUT ON/OFF = 0

Digital Out is output from the DOUT pin. Digital Out is not output from the DOUT pin.

Processing

Command bit

Sync protection window width WSEL = 1 WSEL = 0

±26 channel clock

∗1

±6 channel clock

Anti-rolling is enhanced. Sync window protection is enhanced.

Application

See the $BX commands.

∗

1

In normal-speed playback, channel clock = 4.3218MHz.

D3

0

VCO1

CS0

0 0

D2 D1 D0

Data 4

D3

0 0 0 0

D2 D1 D0

Data 5

D3

TXON

TXOUT

OUTL1 OUTL0

D2 D1 D0

Data 6

– 33 –

CXD3017Q

Command bit

VCOSEL1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Multiplier PLL VCO1 is set to 1× speed, and the output is 1/1 frequency-divided.

Multiplier PLL VCO1 is set to 1× speed, and the output is 1/2 frequency-divided.

Multiplier PLL VCO1 is set to 1× speed, and the output is 1/4 frequency-divided.

Multiplier PLL VCO1 is set to 1× speed, and the output is 1/8 frequency-divided.

Multiplier PLL VCO1 is set to about 2× speed, and the output is 1/1 frequency-divided.

Multiplier PLL VCO1 is set to about 2× speed, and the output is 1/2 frequency-divided.

Multiplier PLL VCO1 is set to about 2× speed, and the output is 1/4 frequency-divided.

Multiplier PLL VCO1 is set to about 2× speed, and the output is 1/8 frequency-divided.

KSL3 KSL2

Processing

Command bit

VCO1CS0 = 0

Processing Multiplier PLL VCO1 low speed is selected. Multiplier PLL VCO1 high speed is selected.

∗

The CXD3017Q has two VCO1s, and this command selects one of these VCO1s.

VCO1CS0 = 1

Selector

1/2

1/1

1/8

1/4

Selector

To DSP interior

KSL3, 2VCO1CS0

Low-speed

VCO1

High-speed

VCO1

VCO1SEL1

∗

Block Diagram of VCO Internal Path

VCO1 Internal Path

Command bit

TXON = 0

Processing

When CD TEXT data in not demodulated, set TXON to 0. When CD TEXT data in demodulated, set TXON to 1.

∗

See "$3-13. CD TEXT Data Demodulation"

TXON = 1

– 34 –

CXD3017Q

Command bit

TXOUT = 0

Processing

Various signals except for CD TEXT is output from the SQSO pin. CD TEXT data is output from the SQSO pin.

∗

See "§3-13. CD TEXT Data Demodulation"

TXOUT = 1

Command bit

OUTL1 = 0

Processing

WFCK and XPCK are output. WFCK and XPCK outputs are low.OUTL1 = 1

Command bit

OUTL0 = 0 OUTL0 = 1

Processing

PCMD, BCK, LRCK and EMPH are output. PCMD, BCK, LRCK and EMPH outputs are low.

– 35 –

CXD3017Q

Timing Chart 1-1

Rch 16-bit C2 Pointer Lch 16-bit C2 Pointer

If C2 Pointer = 1,

data is NG

C2 Pointer for upper 8bits C2 Pointer for lower 8bits

Rch C2 Pointer

C2 Pointer for upper 8bits C2 Pointer for lower 8bits

Lch C2 Pointer

LRCK

CDROM = 0

CDROM = 1

C2PO

– 36 –

CXD3017Q

$9X commands (OPSL1= 0)

∗

Data 2 D0 and subsequent data are for DF/DAC function settings.

Command bit

DSPB = 1 DSPB = 0

Double-speed playback (CD-DSP block) Normal-speed playback (CD-DSP block)

Processing

Command bit

OPSL1 = 1 OPSL1 = 0

DCOF can be set. DCOF cannot be set.

Processing

Command bit

MCSL = 1 MCSL = 0

DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz) DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz)

Processing

Command

Data 1

D3

0

DSPB

ON/OFF

0

0 0 MCSL 0 0

ZDPL

ZMUT — —

D2 D1 D0 D3

D2

D1 D0 D3 D2 D1 D0

Data 3

Data 4

Data 2

Function specification

000 0

D3 to D1

D0

OPSL1

D3

—

— — —

D2 D1 D0

Data 5

$9X commands (OPSL1= 1)

∗

Data 2 D0 and subsequent data are for DF/DAC function settings.

Command

Data 1

D3

0

DSPB

ON/OFF

0

1 MCSL 0 0 ZDPL ZMUT 0 0

D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Data 3

Data 4Data 2

Function specification

000 0

D3 to D1

D0

OPSL1

D3

0 DCOF 0

DAC

PWDN

D2 D1 D0

Data 5

Command bit

ZDPL = 1 ZDPL = 0

LMUT and RMUT pins are high when muted. LMUT and RMUT pins are low when muted.

Processing

∗

See "Mute flag output" for the mute flag output conditions.

– 37 –

CXD3017Q

Command bit

DCOF = 1 DCOF = 0

DC offset is off. DC offset is on.

Processing

∗

DCOF can be set when OPSL1 = 1.

∗

Set DC offset to off when zero detection mute is on.

Command bit

ZMUT = 1 ZMUT = 0

Zero detection mute is on. Zero detection mute is off.

Processing

$AX commands (OPSL2 = 0)

∗

Data 2 and subsequent data are for DF/DAC function settings.

Command

Data 1

D3

0

0 Mute ATT 0 0 0 EMPH

D2 D1 D0 D3

D2 D1

D0

Data 2

Data 3

Audio CTRL

SMUT AD10

D3 D2

OPSL2

Data 4

D3

AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

— — — —

D2

D1 D0

D3 D2 D1

D0

D3 D2 D1 D0

Data 5

Data 6Data 3

AD9 AD8

D1 D0

$AX commands (OPSL2 = 1)

∗

Data 2 and subsequent data are for DF/DAC function settings.

Command

Data 1

D3

0 0 Mute

ATT 0 0 1 EMPH

D2 D1 D0 D3 D2 D1 D0

Data 2

Data 3

Audio CTRL

SMUT

AD10

D3 D2

OPSL2

Data 4

D3

AD7 AD6

AD5 AD4

AD3 AD2 AD1 AD0 FMUT LRWO

BSBST

BBSL

D2 D1 D0

D3

D2

D1

D0

D3 D2

D1 D0

Data 5

Data 6

Data 3

AD9

AD8

D1 D0

Command bit DACPWDN = 0 DACPWDN = 1

Normal operation. DAC block clock is stopped. This makes it possible to reduce power consumption.

Processing

– 38 –

CXD3017Q

The attenuation data consists of 11 bits, and is set as follows.

Attenuation data

400h

3FEh 3FDh

:

001h 000h

0dB

–0.0085dB –0.0170dB

–60.206dB

– ∞

Audio output

Command bit

EMPH = 1 EMPH = 0

De-emphasis is on. De-emphasis is off.

Processing

∗

If either the EMPHI pin or EMPH is high, de-emphasis is on.

∗

If either the SMUT pin or SMUT is high, soft mute is on.

Command bit

SMUT = 1 SMUT = 0

Soft mute is on. Soft mute is off.

Processing

Command bit

AD10 to 0 Attenuation data.

Meaning

Command bit

Mute = 1 Mute = 0

CD-DSP block mute is on. 0 data is output from the CD-DSP block. CD-DSP block mute is off.

Processing

Command bit

ATT = 1 ATT = 0

CD-DSP block output is attenuated (–12dB). CD-DSP block output attenuation is off.

Processing

Command bit

OPSL2 = 1 OPSL2 = 0

FMUT, LRWO, BSBST and BBSL can be set. FMUT, LRWO, BSBST and BBSL cannot be set.

Meaning

The attenuation data (AD10 to AD0) consists of 11bits, and can be set in 1024 different ways in the range of 000h to 400h. The audio output from 001h to 400h is obtained using the following equation.

Audio output = 20log [dB]

Attenuation data

1024

– 39 –

CXD3017Q

Command bit

FMUT = 1 FMUT = 0

Forced mute is on. Forced mute is off.

Meaning

∗

FMUT can be set when OPSL2 = 1.

Command bit

BSBST = 1 BSBST = 0

Bass boost is on. Bass boost is off.

Processing

∗

BSBST can be set when OPSL2 = 1.

Command bit

BBSL = 1 BBSL = 0

Bass boost is Max. Bass boost is Mid.

Processing

∗

BBSL can be set when OPSL2 = 1.

Command bit

LRWO = 1 LRWO = 0

Forced synchronization mode

Note)

Normal operation.

Meaning

∗

LRWO can be set when OPSL2 = 1.

Note) Synchronization is performed at the first falling edge of LRCK during reset, so there is normally no need

to set this mode. However, synchronization can be forcibly performed by setting LRWO = 1.

– 40 –

CXD3017Q

$AD commands (preset: $AD00)

Data 1

D31D21D10D01D3

ADCPS

D2

DSP

SLEEP

D1

DSSP

SLEEP

D0

ASYM

SLEEP

D30D2

LPF

SLEEP

D10D00D3 D2 D1 D0

AD

(Sleep setting)

Data 2 Data 3 Data 4

Command

ADCPS: This bit sets the operating mode of the DSSP block A/D converter.

When 0, the operating mode of the DSSP block A/D converter is set to normal. (default) When 1, the operating mode of the DSSP block A/D converter is set to power saving.

DSP SLEEP: This bit sets the operating mode of the DSP block.

When 0, the DSP block operates normally. (default) When 1, the DSP block clock is stopped. This makes it possible to reduce power consumption.

DSSP SLEEP: This bit sets the operating mode of the DSSP block.

When 0, the DSSP block operates normally. (default) When 1, the DSSP block clock is stopped. In addition, the A/D converter and operational amplifier in the DSSP block are set to standby mode. This makes it possible to reduce power consumption.

ASYM SLEEP: This bit sets the operating mode of the asymmetry correction circuit and VCO1.

When 0, the asymmetry correction circuit and VCO1 operate normally. (default) When 1, the operational amplifier in the asymmetry correction circuit is set to standby mode. In addition, the multiplier PLL VCO1 oscillation is stopped. This makes it possible to reduce power consumption.

LPF SLEEP: This bit sets the operating mode of the analog low-pass filter block.

When 0, the analog low-pass filter block operates normally. (default) When 1, the analog low-pass filter block is set to standby mode. This makes it possible to reduce power consumption.

∗

The DAC block clock can be stopped by setting $9 command DACPWDN (when OPSL1 = 1).

– 41 –

CXD3017Q

Command

D3

SL1

SL0

CPUSR

0

D2

D1 D0

TRM1

D3

TRM0

D2

MTSL1

D1

MTSL0

D0

Data 1 Data 2

Serial bus

CTRL

$BX commands

SOCT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SubQ

Peak meter

SENSDSubQAB

C

SL1 SL0 mode

The SQSO pin output can be switched to the various

signals by setting the SOCT command of $8X and the SL1

and SL0 commands of $BX. Set SQCK to high at the

falling edge of XLAT.

Except for Sub Q and peak meter, the signals are loaded

to the register when they are set at the falling edge of

XLAT. Sub Q is loaded to the register with each SCOR,

and Peak meter is loaded when a peak is detected.

mode A

XLAT

SQCK

mode B

mode C

mode D

Peak meter

PER1 PER2 PER3 PER4 PER5 PER6 PER7 C1F1 0C1F2 C2F1 0C2F2 FOK LOCKGFS EMPH —ALOCK — — — — — — —

— — — — — — — — ALOCK C1F1 C1F2 0 C2F1 0C2F2 FOK LOCKGFS EMPH

PER1 PER2 PER3 PER4 PER5 PER6 PER7PER0 C1F1 C1F2 0 C2F1 0C2F2 FOK LOCKGFS EMPH0

PER0

SPOA C1F1 C1F2 C2F1 C2F2XRAOFFOKGFS

L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7

LOCKEMPH RFCKWFCK SCOR00SPOB GTOP

—

: don't care

– 42 –

CXD3017Q

Signal

PER0 to 7

FOK GFS

LOCK

EMPH

ALOCK

SPOA, B

WFCK

SCOR GTOP

RFCK

XRAOF

L0 to L7,

R0 to R7

RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. Focus OK High when the frame sync and the insertion protection timing match. GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight

consecutive samples, a low signal is output. High when the playback disc has emphasis. GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is

output. If GFS is low eight consecutive samples, a low signal is output. SPOA and B pin inputs. Write frame clock output. High when either subcode sync S0 or S1 is detected. High when the sync protection window is open. Read frame clock output. Low when the built-in 16K RAM exceeds the ±4 frame jitter margin. Peak meter register output. L0 to 7 are the left-channel and R0 to 7 are the right-channel peak

data. L0 and R0 are LSB.

Description

C1F1

0 1 1

0 0 1

No Error Single Error Correction Irretrievable Error

C1F2 C1 correction status C2F1

0 1 1

0 0 1

No Error Single Error Correction Irretrievable Error

C2F2 C2 correction status

Command bit

CPUSR = 1 CPUSR = 0

XLON pin is high. XLON pin is low.

Processing

– 43 –

CXD3017Q

Peak meter

SQSO

XLAT

SQCK

(Peak meter)

L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7

Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively, results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data values (absolute value, upper 8bits) for the left and right channels can be read from SQSO by inputting 16 clocks to SQCK. Peak detection is not performed during SQCK input, and the peak register does not change during readout. This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant of 270µs to 400µs. The time during which SQCK input is high should be 270µs or less. Also, peak detection is restarted 270µs to 400µs after SQCK input.

The peak register is reset with each readout (16 clocks input to SQCK). The maximum value in peak detection mode is detected and held in this status until the next readout. When switching to peak detection mode, readout should be performed one time initially to reset the peak register.

Peak detection can also be performed for previous value hold and average value interpolation data.

Traverse monitor count value setting

These bits are set when monitoring the traverse condition of the SENS output according to the COUT frequency division.

Command bit

0 0 1 1

0 1 0 1

1/64 frequency division 1/128 frequency division 1/256 frequency division 1/512 frequency division

TRM1

XUGF MNT1 RFCK

XUGF

XPCK MNT0 XPCK

XPCK

GFS

MNT3

XROF

GFS

C2PO C2PO

GTOP

C2PO

MTSL1

0 0 1

Command bit

MTSL0

0 1 0

Symbol

TRM0

Processing

Output data

Monitor output switching

The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B.

∗

It is necessary for the SRO1 command of $3F to be set to 0.

– 44 –

CXD3017Q

$CX commands

• CLV mode gain setting: GCLVS

• CLVP mode gain setting: GMDP: GMDS

Servo coefficient setting

CLV CTRL ($DX)

Gain

MDP1

Gain

MDP0

Gain

MDS1

Gain

MDS0

Gain

CLVS

Gain

MDS1

0 0 0 0 1 1

Gain

MDS0

0 0 1 1 0 0

Gain

CLVS

0 1 0 1 0 1

GCLVS

–12dB

–6dB –6dB

0dB 0dB

+6dB

Command

D3

D2

D1

D0

Gain

MDP1

0 0 1

Gain

MDP0

0 1 0

GMDP

–6dB

0dB

+6dB

Gain

MDS1

0 0 1

Gain

MDS0

0 1 0

GMDS

–6dB

0dB

+6dB

$DX commands

Command bit Description

TB = 0 TB = 1 TP = 0 TP = 1

Bottom hold at a cycle of RFCK/32 in CLVS mode. Bottom hold at a cycle of RFCK/16 in CLVS mode. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode.

Command

D3

0

TB TP

Gain

CLVS

1 1 1 0

0 0 0

0

D2 D1 D0 D3 D2 D1 D0 D3 D2

D1 D0

Data 1

Data 2

CLV CTRL

Data 3

See the $CX commands.

– 45 –

CXD3017Q

$EX commands

Command

Data 1

CLV mode CM3 CM2 CM1 CM0

D3 D2 D1

D0

Data 2

0 0 0 0

D3

D2 D1 D0

Data 3

0 0 0 0

D3

D2 D1

D0

Command bit

CM3

CM2 CM1

Description

Spindle stop mode.

∗1

Spindle forward rotation mode.

∗1

Spindle reverse rotation mode. Valid only when LPWR = 0 in any mode.

∗1

Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range.

PLL servo mode. Automatic CLVS/CLVP switching mode.

Used for normal playback.

0 1

1

1 0

0 0

0

1

1 1

0 0

1

1 1

CM0

0 0

0

1 0

Mode

STOP

KICK

BRAKE

CLVS

CLVP CLVA

∗1

See Timing Charts 1-2 and 1-3.

Data 4

0 0 0 0

D3 D2 D1 D0

Timing Chart 1-3

MDP

Acceleration

Z

Deceleration

132kHz

7.6µs

n · 236 (ns) n = 0 to 31

Timing Chart 1-2

KICK

MDP

H

KICK

BRAKE

MDP

BRAKE

STOP

MDP

STOP

Z

L

Z

– 46 –

CXD3017Q

§2. Subcode Interface

In the CXD3017Q, only SubQ can be readout. The subcodes P and R to W cannot be readout. Sub Q can be read out after checking CRC of the 80 bits in the subcode frame. Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high.

§2-1. 80-bit Sub Q Readout

Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register.

• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit.

• 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high 400µs (monostable multivibrator time constant) or more after subcode readout, the CPU determines that the new data (which passed the CRC check) has been loaded.

• The CRCF reset is performed by inputting SQCK. When the subcode data is discontinuous after track jump, etc. CRCF is reset by inputting SQCK. Then, if CRCF =1, the CPU determines that the new data has been loaded.

• When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.

• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.

• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register.

• While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others. (See Timing Chart 2-2.)

• The high and low intervals for SQCK should be between 750ns and 120µs.

– 47 –

CXD3017Q

Block Diagram 2-1

SUBQ

SIN

A B C D E F G H

(AFRAM)

H G F E D C B A

(ASEC)

(AMIN)

80bit S/P Register

ADDRS CTRL

8

Order

Inversion

8

SI

LD

80bit P/S Register

SO

SHIFT

SQCK

CRCF

Mix

SQSO

Mono/Multi

CRCC

SUBQ

SHIFT

– 48 –

CXD3017Q

Timing Chart 2-2

1

2

3

91 92 93 94

95 96 97

98

WFCK

SCOR

SQSO

SQCK

Mono/multi (Internal)

Order

Inversion

CRCF1

Determined by mode

L

CRCF2

80 Clock

Registere load forbidder

270 to 400µs when SQCK = high.

750ns to 120µs

300ns max

CRCF

ADR0

ADR1

ADR2

ADR3

CTL0

CTL1

CTL2

CTL3

SQCK

SQSO

1

2

3

– 49 –

CXD3017Q

§3. Description of Other Functions

§3-1. Channel Clock Regeneration by the Digital PLL Circuit

• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.

Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, a PLL is necessary for regenerating the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses.

The block diagram of this PLL is shown in Fig. 3-1. The CXD3017Q has a built-in three-stage PLL.

• The first-stage PLL regenerates the high-frequency clock needed by the second-stage digital PLL.

• The second-stage PLL is a digital PLL that regenerates the actual channel clock.

Block Diagram 3-1

X'tal

XTSL

OSC

1/M

1/N

Phase comparator

VCO1

VCOSEL1

1/K

(KSL3, 2)

Digital PLL

RFPLL

PCO

FILI

FILO

CLTV

CXD3017Q

– 50 –

CXD3017Q

§3-2. Frame Sync Protection

• In normal-speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is

used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability.

• In the CXD3017Q, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately.

§3-3. Error Correction

• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code

is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5.

• The CXD3017Q's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to achieve high playability.

• The correction status can be monitored externally. See Table 3-2.

• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an

average value interpolation was made for the data.

MNT3

0 0 0 1 1 1

MNT1

0 0 1 0 0 1

MNT0

0 1 1 0 1 0

Description No C1 errors One C1 error corrected C1 correction impossible No C2 errors One C2 error corrected C2 correction impossible

Table 3-2

– 51 –

CXD3017Q

Timing Chart 3-3

Normal-speed PB

MNT3

MNT1

MNT0

t = Dependent on error

condition

C1 correction C2 correction

Strobe

§3-4. DA Interface

• The CXD3017Q's DA interface is as follows:

Interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel.

– 52 –

CXD3017Q

Timing Chart 3-4

LRCK

(44.1k)

BCK

(2.12M)

PCMD

LRCK

(88.2k)

BCK

(4.23M)

PCMD

48-bit slot Normal-Speed Playback

1

24

R0

Lch MSB (15)

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 RMSB

R0

Lch MSB (15)

24

Rch MSB

2 3 4 5 6 7 8 9 10 11 12

48-bit slot Double-Speed Playback

1 2

L0

– 53 –

CXD3017Q

§3-5. Digital Out

There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD3017Q supports type 2 form 1. Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3) of the channel status. When Mute = 1 in $AX commands, the channel status is pre-value hold.

Table 3-5

§3-6. Servo Auto Sequence

This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump and N-track move are executed automatically. The commands which enable transfer to the CXD3017Q during the execution of auto sequence are $4X to $EX. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µs after that point.

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0

ID0

ID1

COPY

Emph

0 0 0 0 1 0 0 0 0 0 0 0

From sub Q

0

16

32

48

176

Bits 0 to 3 Sub Q control bits that matched twice with CRCOK

Digital Out C bit

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

– 54 –

CXD3017Q

(a) Auto focus ($47)

Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 3-6. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E.

Auto focus

Focus search up

FOK = H

NO

YES

FZC = H

NO

YES

FZC = L

NO

YES

END

Focus servo ON

(Check whether FZC is continuously high for the period of time E set with register 5.)

Fig. 3-6-(a). Auto Focus Flow Chart

– 55 –

CXD3017Q

Fig. 3-6-(b). Auto Focus Timing Chart

(b) Track jump

1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on should be sent beforehand because they are not involved in this sequence.

• 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 3-7. Set blind A and brake B with register 5.

• 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 3-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on.

• 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 3-9. The track jump count N is set with register 7. Although N can be set to 2

16

tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.

• N-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) N-track move is performed in accordance with Fig. 3-10. N can be set to 216tracks. COUT is used for counting the number of jumps. The N-track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks.

XLAT

FOK

(FZC)

BUSY

Command for

DSSP

$47latch

$03

Blind E

$08

– 56 –

CXD3017Q

Fig. 3-7-(a). 1-Track Jump Flow Chart

Track

NO

YES

END

Track FWD kick

sled servo OFF

WAIT

(Blind A)

COUT =

Track REV

kick

WAIT

(Brake B)

Track, sled

servo ON

(FWD kick for REV jump)

(REV kick for REV jump)

Fig. 3-7-(b). 1-Track Jump Timing Chart

XLAT

COUT

BUSY

Command for

DSSP

$48 (REV = $49) latch

$28 ($2C)

Blind A

Brake B

$2C ($28)

$25

– 57 –

CXD3017Q

Fig. 3-8-(a). 10-Track Jump Flow Chart

10 Track

NO

YES

END

Track, sled

FWD kick

WAIT

(Blind A)

COUT = 5 ?

Track, REV

kick

Track, sled

servo ON

(Check whether the COUT cycle is longer than overflow C.)

(Counts COUT × 5)

NO

YES

C = Overflow ?

Fig. 3-8-(b). 10-Track Jump Timing Chart

XLAT

COUT

BUSY

Command for

DSSP

$4A (REV = $4B) latch

Blind A

$2A ($2F)

COUT 5 counts

$2E ($2B)

Overflow C

$25

– 58 –

CXD3017Q

Fig. 3-9-(b). 2N-Track Jump Timing Chart

Fig. 3-9-(a). 2N-Track Jump Flow Chart

2N Track

NO

YES

END

Track, sled

FWD kick

WAIT

(Blind A)

COUT = N

Track REV

kick

Track servo

ON

NO

YES

C = Overflow

WAIT

(Kick D)

Sled servo

ON

XLAT

BUSY

Command for

DSSP

Blind A

$2A ($2F)

COUT N counts

$2E ($2B)

Overflow C

Kick D

$26 ($27)

$25

$4C (REV = $4D) latch

COUT

– 59 –

CXD3017Q

Fig. 3-10-(a). N-Track Move Flow Chart

N Track move

NO

YES

END

Track servo OFF

Sled FWD kick

WAIT

(Blind A)

COUT = N

END

Track, sled

servo OFF

Fig. 3-10-(b). N-Track Move Timing Chart

XLAT

BUSY

Command for

DSSP

$22 ($23)

Blind A

COUT N counts

$20

$4E (REV = $4F) latch

COUT

– 60 –

CXD3017Q

§3-7. Digital CLV

Fig. 3-11 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable.

Digital CLV

CLVS U/D

MDS Error

MDP Error

CLV P/S

Measure

2/1 MUX

Oversampling

Filter-1

Gain MDS

1/2

MUX

CLV P/S

Oversampling

Filter-2

Noise Shape

Modulation

KICK, BRAKE, STOP

MDP

Gain MDP

CLVS U/D: Up/down signal from CLVS servo MDS error: Frequency error for CLVP servo MDP error: Phase error for CLVP servo

Fig. 3-11. Block Diagram

– 61 –

CXD3017Q

§3-8. CD-DSP Block Playback Speed

In the CXD3017Q, the following playback modes can be selected through different combinations of the crystal, XTSL pin and the DSPB command of $9X.

CD-DSP block playback speed

Crystal

768Fs 768Fs 768Fs 384Fs 384Fs 384Fs

0 1 1 0 0 1

1 0 1 0 1 1

4×

∗1

1× 2× 1× 2×

1×

∗2

XTSL DSPB CD-DSP block playback speed

Fs = 44.1kHz.

∗1

In 4× speed playback, the timer value for the auto sequence is halved.

∗2

Low power consumption mode. The CD-DSP processing speed is halved, allowing power consumption to be reduced.

§3-9. DAC Block Playback Speed

The operation speed for the DAC block is determined by the crystal and the MCSL command of $9X regardless of the CD-DSP operating conditions noted above. This allows the playback modes for the DAC and CD-DSP blocks to be set independently.

1-bit DAC block playback speed

Crystal

768Fs 768Fs 384Fs

1 0 0

1× 2× 1×

MCSL DAC block playback speed

Fs = 44.1kHz.

– 62 –

CXD3017Q

§3-10. Description of DAC Block Functions

Zero data detection

When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or all "1" has continued about for 300ms, zero data is detected. Zero data detection is performed independently for the left and right channels.

Mute flag output

The LMUT and RMUT pins go active when any one of the following conditions is met. The polarity can be selected with the ZDPL command of $9X.

• When zero data is detected

• When a high signal is input to the SYSM pin

• When the SMUT command of $AX is set

Attenuation operation

Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and Y3 (Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1 continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then approaches Y3 from the value (B or C in the figure) at that point.

A

Y1

B

Y3

C

Y2

23.2 [ms]

– ∞ 000 (H)

0dB

3FF (H)

– 63 –

CXD3017Q

DAC block mute operation

Soft mute

Soft mute results and the input data is attenuated to zero when any one of the following conditions is met.

• When attenuation data of "000" (high) is set

• When the SMUT command of $AX is set to 1

• When a high signal is input to the SYSM input pin

Forced mute

Forced mute results when the FMUT command of $AX is set to 1. Forced mute fixes the PWM output that is input to the LPF block to low.

∗

When setting FMUT, set OPSL2 to 1. (See the $AX commands.)

Zero detection mute

When the ZMUT command of $9X is set to 1 and the zero data is detected for the left or right channel, the analog mute is applied to the each channel. (See "Zero data detection".) When the ZMUT command of $9X is set to 1, the analog mute is applied even if the mute flag output condition is met. When the zero detection mute is on, set the DCOF command of $9X to 1.

Soft mute on Soft mute offSoft mute off

23.2 [ms] 23.2 [ms]

0dB

– ∞dB

– 64 –

CXD3017Q

Normal DBB MID DBB MAX

10.00

–4.00

6.00

4.00

2.00

0.00

–2.00

8.00

–6.00

–8.00 –10.00 –12.00 –14.00

10 30 100 300 1k 3k 10k 30k

Digital Bass Boost Frequency Response [Hz]

[dB]

Graph 3-12

LRCK Synchronization

Synchronization is performed at the first falling edge of the LRCK input during reset. After that, synchronization is lost when the LRCK input frequency changes and resynchronization must be performed. The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed changes such as the following cases.

• When the XTSL pin switches between high and low

• When the DSPB command of $9X setting changes

• When the MCSL command of $9X setting changes

LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC block. Resynchronization must be performed in this case as well. For resynchronization, set the LRWO command of $AX to 1, wait for one LRCK cycle or more, and then set LRWO to 0.

∗

When setting LRWO, set OPSL2 to 1. (See the $AX commands.)

Digital Bass Boost

Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels: Mid. and Max. BSBST and BBSL of address A are used for the setting. See Graph 3-12 for the digital bass boost frequency response.

– 65 –

CXD3017Q

Analog out

C2

330p

27k

C1

68p

AOUT1 (2)

AIN1 (2)

LOUT1 (2)

Vc

100

27k

Fig. 3-13. LPF External Circuit

§3-11. LPF Block

The CXD3017Q contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly. The reference voltage (VC) is (AVDD – AVSS) × 0.45.

The LPF block application circuit is shown below. In this circuit, the cut-off frequency is fc ≈ 40kHz.

LPF Block Application Circuit

– 66 –

CXD3017Q

§3-12. Asymmetry Compensation

Fig. 3-14 shows the block diagram and circuit example.

RFAC

R1

ASYO

ASYI

R1 2 R2 5

=

BIAS

R1

R2

CXD3017Q

Fig. 3-14. Asymmetry Compensation Application Circuit

– 67 –

CXD3017Q

§3-13. CD TEXT Data Demodulation

• In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to 1.

It requires 26.7ms (max.) to demodulate the CD TEXT data correctly after TXON is set to 1.

• The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is enabled by setting the command $8 Data 6 D2 TXOUT to 1. To read data, the readout clock should be input to SQCK.

• The readable data are the CRC counting results for the each pack and the CD TEXT data (16 bytes) except for CRC data.

• When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.

• Data which can be stored in the LSI is 1 packet (4 packs).

Fig. 3-15. Block Diagram of CD TEXT Demodulation Circuit

SQCK

SQSO

TXOUT

Subcode

Decoder

CD TEXT

Decoder

– 68 –

CXD3017Q

CRC

4

CRC

3

CRC

2

CRC

1

0

0 0 0

S2 R2 W1 V1 U1 T1 S1 R1 U3 T3 S3 R3 W2 V2 U2 T2 W4 V4 U4 T4 S4

CRC Data

ID1 (Pack1)

ID2 (Pack1)

ID3 (Pack1)

16 Bytes

4 bits

Subcode Q Data

SCOR

TXOUT

(command)

SQCK

SQSO

SQCK

TXOUT

(command)

LSB

MSB

LSB MSB

LSB

CRC

0

Pack1

Pack2

Pack3

Pack4

CRCF

80 clocks

SQSO

520 clocks

Fig. 3-16. CD TEXT DATA Timing Chart

– 69 –

CXD3017Q

§4. Description of Servo Signal Processing System Functions and Commands

§4-1. General Description of Servo Signal Processing System (VDD: Supply voltage)

Focus servo

Sampling rate: 88.2kHz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Output format: 7-bit PWM Other: Offset cancel

Focus bias adjustment Focus search Gain-down function Defect countermeasure Auto gain control

Tracking servo

Sampling rate: 88.2kHz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Output format: 7-bit PWM Other: Offset cancel

E:F balance adjustment Track jump Gain-up function Defect countermeasure Drive cancel Auto gain control Vibration countermeasure

Sled servo

Sampling rate: 345Hz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Output format: 7-bit PWM Other: Sled move

FOK, MIRR, DFCT signal generation

RF signal sampling rate: 1.4MHz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Other: RF zero level automatic measurement

– 70 –

CXD3017Q

§4-2. Digital Servo Block Master Clock (MCK)

The clock with 2/3 frequency of the crystal is supplied to the digital servo block. XT4D and XT2D are $3F commands, and XT1D is a $3E command. (Default is 0 for each command) The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical.

Mode

1 2 3 4 5 6 7

384Fs 384Fs 384Fs 768Fs 768Fs 768Fs 768Fs

256Fs 256Fs 256Fs 512Fs 512Fs 512Fs 512Fs

∗ ∗

0

∗ ∗ ∗

1

∗ ∗

0

∗ ∗

1 0

∗

1 0

∗

1 0 0

1 0 0 1 0 0 0

1 1/2 1/2

1 1/2 1/4 1/4

256Fs 128Fs 128Fs 512Fs 256Fs 128Fs 128Fs

XTAI

FSTO

XTSL XT4D XT2D XT1D Frequency division ratio MCK

Fs = 44.1kHz, ∗: don't care

Table 4-1

– 71 –

CXD3017Q

§4-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 4-3.)

The CXD3017Q can measure the averages of RFDC, VC, FE and TE and compensate these signals using the measurement results to control the servo effectively. This AVRG measurement and compensation is necessary to initialize the CXD3017Q, and is able to cancel the DC offset. AVRG measurement takes the levels applied to the VC, FE, RFDC and TE pins as the digital average values of 256 samples, and then loads these values into each AVRG register. The AVRG measurement commands are D15 (VCLM), D13 (FLM), D11 (RFLM) and D4 (TLM) of $38. Measurement is on when the respective command is set to 1. AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received. The completion of AVRG measurement operation can be monitored by the SENS pin. (See Timing Chart 4-2.) Monitoring requires that the upper 8 bits of the command register are 38 (h).

XLAT

SENS (= XAVEBSY)

Max. 1µs

AVRG measurement completed

2.9 to 5.8ms

Timing Chart 4-2

VC AVRG: The VC DC offset (VC AVRG) which is the center voltage for the system is measured and used to

compensate the FE, TE and SE signals. FE AVRG: The FE DC offset (FE AVRG) is measured and used to compensate the FE and FZC signals. TE AVRG: The TE DC offset (TE AVRG) is measured and used to compensate the TE and SE signals. RF AVRG: The RF DC offset (RF AVRG) is measured and used to compensate the RFDC signal.

RFLC: (RF signal – RF AVRG) is input to the RF In register.

"00" is input when the RF signal is lower than RF AVRG. TCL0: (TE signal – VC AVRG) is input to the TRK In register. TCL1: (TE signal – TE AVRG) is input to the TRK In register. VCLC: (FE signal – VC AVRG) is input to the FCS In register. FLC1: (FE signal – FE AVRG) is input to the FCS In register. FLC0: (FE signal – FE AVRG) is input to the FZC register.

Two methods of canceling the DC offset are assumed for the CXD3017Q. These methods are shown in Figs. 4-3a and 4-3b. An example of AVRG measurement and compensation commands is shown below. $38 08 00 (RF AVRG measurement) $38 20 00 (FE AVRG measurement) $38 00 10 (TE AVRG measurement) $38 14 0A (Compensation on [RFLC, FLC0, FLC1, TLC1]; corresponds to Fig. 4-3a.)

See the description of $38 for these commands.

– 72 –

CXD3017Q

§4-4. E:F Balance Adjustment Function (See Fig. 4-3.)

When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS search, the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1. The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to 0. Next, setting D2 (TLC2) of $38 to 1 compensates the values obtained from the TE and SE input pins with the TRVSC register value (subtraction), allowing the E:F balance offset to be adjusted. (See Fig. 4-3.)

§4-5. FCS Bias (Focus Bias) Adjustment Function

The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 4-3.) When D11 = 0 and D10 = 1 is set by $34F, the FBIAS register value can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the $8 command SOCT to 1. (See "DSP Block Timing Chart".)

– 73 –

CXD3017Q

Fig. 4-3b

Fig. 4-3a

TE AVRG

register

TLC1

TRVSC register

TLC2

– –

to TRK In register

TE from A/D

FE AVRG

register

FLC1

FBIAS

register

FBON

–

to FCS In register

FLC0

to FZC register

FE from A/D

–

RFLC

–

to RF In registerRFDC from A/D

RF AVRG

register

– –

to SLD In registerSE from A/D

TLC1 • TLD1 TLC2 • TLD2

+

VC AVRG

register

TLC0

TRVSC register

TLC2

– –

to TRK In register

TE from A/D

FBIAS

register

FBON

to FCS In register

VCLC

to FZC register

FE from A/D

–

RFLC

–

to RF In registerRFDC from A/D

RF AVRG

register

– –

to SLD In registerSE from A/D

TLC0 • TLD0 TLC2 • TLD2

–

+

FE AVRG

register

FLC0

– 74 –

CXD3017Q

§4-6. AGCNTL (Automatic Gain Control) Function

The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate servo loop gain. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the command register are 38 (h), the completion of AGCNTL operation can be confirmed by monitoring the SENS pin. (See Timing Chart 4-4 and "Description of SENS Signals".) Setting D9 and D8 of $38 to 1 sets FCS (focus) and TRK (tracking) respectively to AGCNTL operation.

Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described

hereafter) must be disabled.

XLAT

SENS (= AGOK)

Max. 11.4µs

AGCNTL completion

Timing Chart 4-4

Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (h), and they must also be set within this range when written externally. After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter).

AGCNTL related settings

The following settings can be changed with $35, $36 and $37. FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (h) TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (h) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during rough adjustment) AGV2; AGCNTL sensitivity 2 (during fine adjustment) AGHS; Rough adjustment on/off AGHT; Fine adjustment time

Note) Converging servo loop gain values can be changed with the FG6 to FG0 and TG6 to TG0 setting values.

In addition, these setting values must be within the effective setting range. The default settings aim for 0 dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary.

– 75 –

CXD3017Q

AGCNTL default operation has two stages. In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient is finely adjusted with relatively low sensitivity to further approach the appropriate value. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD3017Q confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode) This self-stop mode can be canceled by setting AGS to 0. In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. An example of AGCNTL coefficient transitions during AGCNTL operation with various settings is shown in Fig. 4-5.

Initial value

SENS

AGCNTL Start

AGCNTL completion

Convergence value

AGCNTL coefficient value

Slope AGV1

AGHT

AGJ

Slope AGV2

Fig. 4-5

Note) Fig. 4-5 shows the case where the AGCCNTL coefficient converges from the initial value to a smaller

value.

– 76 –

CXD3017Q

§4-7. FCS Servo and FCS Search (Focus Search)

The FCS servo is controlled by the 8-bit serial command $0X. (See Table 4-6.)

Register name

Command

D23 to D20

D19 to D16

1 0 ∗ ∗ 1 1 ∗ ∗ 0 ∗ 0 ∗ 0 ∗ 1 ∗ 0 ∗ 1 0 0 ∗ 1 1

FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP

0 0 0 0

FOCUS CONTROL

0

Table 4-6

FCS Search

FCS search is required in the course of turning on the FCS servo.

Fig. 4-7 shows the signals for sending commands $00 → $02 → $03 and performing only FCS search operation. Fig. 4-8 shows the signals for sending $08 (FCS on) after that.

FCSDRV

RF

FOK

FE

FZC

FZC comparator level

$00 $02 $03

0

FCSDRV

RF

FOK

FE

FZC

$00 $02 $03

0

$08

Fig. 4-7 Fig. 4-8

∗: don't care

– 77 –

CXD3017Q

§4-8. TRK (Tracking) and SLD (Sled) Servo Control

The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 4-9.) When the upper 4 bits of the serial data are 2 (h), TZC is output to the SENS pin.

Register name

Command

D23 to D20

D19 to D16

0 0 ∗ ∗ 0 1 ∗ ∗ 1 0 ∗ ∗ 1 1 ∗ ∗

∗ ∗ 0 0 ∗ ∗ 0 1 ∗ ∗ 1 0 ∗ ∗ 1 1

TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE

0 0 1 0

TRACKING MODE

2

Table 4-9

TRK Servo

The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36. In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode. The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. The CXD3017Q has 2 types of gain-up filter structures in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 4-17.)

SLD Servo

The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by multiplying this value by 1×, 2×, 3×, or 4× set using D17 and D16 when D18 = D19 = 0 is set with $3. (See Table 4-10.) SLD MOV must be performed continuously for 50µs or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off.

Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off.

These operations are disabled by setting D6 (LKSW) of $38 to 1.

Register name

Command

D23 to D20

D19 to D16

0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1

SLED KICK LEVEL (basic value × ±1) SLED KICK LEVEL (basic value × ±2) SLED KICK LEVEL (basic value × ±3) SLED KICK LEVEL (basic value × ±4)

0 0 1 1

SELECT

3

Table 4-10

∗: don't care

– 78 –

CXD3017Q

§4-9. MIRR and DFCT Signal Generation

The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and loaded. The MIRR and DFCT signals are generated from this RF signal.

MIRR Signal Generation

The loaded RF signal is applied to peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of this envelope waveform. The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value from the peak hold value with this MIRR comparator level. (See Fig. 4-11.) The bottom hold speed and mirror sensitivity can be selected from four values using D7 and D6, and D5 and D4, respectively, of $3C.

RF

Peak Hold

Bottom Hold

Peak Hold

– Bottom Hold

MIRR

MIRR Comp (Mirror comparator level)

H L

RF

Peak Hold1

Peak Hold2

Peak Hold

– Bottom Hold

DFCT

(Defect comparator level)

H L

SDF

Fig. 4-11

DFCT Signal Generation

The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 4-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B.

Fig. 4-12

– 79 –

CXD3017Q

Fig. 4-14

§4-10. DFCT Countermeasure Circuit

The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, this operation is achieved by detecting scratches and defects with the DFCT signal generation circuit, and when DFCT goes high, applying the low-frequency component of the error signal before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 4-13.) In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to 1.

Input register

Hold register EN

Hold filter

Servo filter

Error signal

DFCT

Fig. 4-13

§4-11. Anti-Shock Circuit

When vibrations occur in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures. Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 4-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level is practically variable by adjusting the value of the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 4-17.) This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up mode by inputting high level to the ATSK pin. When the upper 4 bits of the command register are 1 (h), vibration detection can be monitored from the SENS pin. It can also be monitored from the ATSK pin by setting $3F command ASOT to 1.

TE

Anti shock

filter

TRK Gain Up

filter

TRK Gain Normal

filter

TRK

PWM Gen.

ATSK

SENS

Comparator

– 80 –

CXD3017Q

§4-12. Brake Circuit

Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. In principle, the brake circuit uses the tracking drive as a brake by cutting the unnecessary portions utilizing the 180° offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 4-15 and 4-16.) Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Table 4-17.) In addition, the low frequency for the tracking drive after masking can be boosted. (SFBK1, 2 of $34B)

TRK DRV

FWD

JMP

REV

JMP

Servo ON

RF Trace

MIRR

TE 0

TZC Edge

TRKCNCL

0

TRK DRV (SFBK OFF)

SENS TZC out

Inner track → Outer track

0

TRK DRV (SFBK ON)

TRK DRV

REV JMP

FWD

JMP

Servo ON

RF Trace

MIRR

TE 0

TZC Edge

TRKCNCL

0

TRK DRV (SFBK OFF)

SENS TZC out

Outer track → Inner track

0

TRK DRV (SFBK ON)

Fig. 4-15 Fig. 4-16

Register name

Command

D23 to D20

D19 to D16

1 0 ∗ ∗ 0 ∗ ∗ ∗

∗ 1 ∗ ∗ ∗ 0 ∗ ∗ ∗ ∗ 0 ∗ ∗ ∗ 1 ∗ ∗ ∗ ∗ 1 ∗ ∗ ∗ 0

ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2

0 0 0 1

TRACKING CONTROL

1

Table 4-17

∗: don't care

– 81 –

CXD3017Q

§4-13. COUT Signal

The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among three different phases according to the COUT signal application.

• HPTZC: For 1-track jumps Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a cut-off 1kHz digital HPF; when MCK = 128Fs.)

• STZC: For COUT generation when MIRR is externally input and for applications other than COUT generation. This is generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)

• DTZC: For high-speed traverse Reliable COUT signal generation with a delayed phase STZC signal.

Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D15 and D14 of $3C.

When D15 = 1: STZC When D15 = 0 and D14 = 0: HPTZC When D15 = 0 and D14 = 1: DTZC

When DTZC is selected, the delay can be selected from two values with D14 of $36.

§4-14. Serial Readout Circuit

The following measurement and adjustment results specified beforehand by serial command $39 can be read out from the SENS pin by inputting the readout clock to the SCLK pin. (See Fig. 4-18, Table 4-19 and "Description of SENS Signals".)

Specified commands

$390C: VC AVRG measurement result $3953: FCS AGCNTL coefficient result $3908: FE AVRG measurement result $3963: TRK AGCNTL coefficient result $3904: TE AVRG measurement result $391C: TRVSC adjustment result $391F: RF AVRG measurement result $391D: FBIAS register value

tDLS

tSPW

1/fSCLK

MSB LSB

XLAT

SCLK

Serial Readout Data (SENS pin)

...

Item

Symbol

Min.

Typ.

Max.

Unit SCLK frequency SCLK pulse width Delay time

fSCLK

tSPW tDLS

31.3 15

16

MHz

ns µs

Table 4-19

During readout, the upper 8 bits of the command register must be 39 (h).

Fig. 4-18

– 82 –

CXD3017Q

§4-16. PWM Output

FCS, TRK and SLD PWM format outputs are described below. In particular, FCS and TRK use a double oversampling noise shaper. Timing Chart 4-20 and Fig. 4-21 show examples of output waveforms and drive circuits.

tMCK = ≈ 180ns

Timing Chart 4-20

Fig. 4-21. Drive Circuit

64tMCK 64tMCK 64tMCK

AtMCK

SFDR

SRDR

SLD

32tMCK 32tMCK 32tMCK 32tMCK32tMCK32tMCK

FCS/TRK

FFDR/ TFDR

FRDR/ TRDR

Output value +A Output value –A Output value 0

t

MCK

A

2

tMCK

A 2

tMCK

A 2

tMCK

A

2

MCK (5.6448MHz) ↑ ↑ ↑ ↑ ↑ ↑ ↑

1

5.6448MHz

R

VEE

DRV

V

CC

RDR

FDR

§4-15. Writing to Coefficient RAM

The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40µs (when MCK = 128Fs) after the XRST pin rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as the data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is received. When rewriting multiple coefficients continuously, be sure to wait 11.3µs (when MCK = 128Fs) before sending the next rewrite command.

– 83 –

CXD3017Q

§4-17. Servo Status Changes Produced by LOCK Signal

When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to 1 deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control.

§4-18. Description of Commands and Data Sets

$34

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 KA6 KA5 KA4 KA3 KA2 KA1 KA0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 0

PFOK1 PFOK0

0 0 0 MRS

MRT1 MRT0

0 0

When D15 = 0.

KA6 to KA0: Coefficient address KD7 to KD0: Coefficient data

$348 (preset: $348 000)

PFOK1

0

1

0

1

0

1

High when the RFDC value is higher than the FOK slice level, low when lower than the FOK slice level.

High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 4.35ms or more.

High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 10.16ms or more.

High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 21.77ms or more.

PFOK0 Processing

These commands set the FOK signal hold time. See $3B for the FOK slice level. These are the values when MCK = 128Fs, and the hold time is inversely proportional to the MCK setting.

MRS: This command switches the time constant for generating the MIRR comparator level of the MIRR

generation circuit. When 0, the time constant is normal. (default) When 1, the time constant is longer than normal. The time during which MIRR = high due to the effects of RFDC signal pulse noise, etc., can be suppressed by setting MRS = 1.

MRT1, 0: These commands limit the time while MIRR = high.

MRT2

0 0 1 1

MRT1

0 1 0 1

No time limit

1.10

2.20

4.00

MIRR maximum time [ms]

∗

∗: preset

– 84 –

CXD3017Q

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 0

THBON FHBON TLB1ON FLB1ON TLB2ON

0

HBST1 HBST0

LB1S1 LB1S0 LB2S1 LB2S0

$34C (preset: $34C 000)

These bits turn on the boost function. (See §4-20. Filter Composition.) There are five boosters (three for the TRK filter and two for the FCS filter) which can be turned on and off independently.

THBON: When 1, the high frequency is boosted for the TRK filter. Preset is 0. FHBON: When 1, the high frequency is boosted for the FCS filter. Preset is 0. TLB1ON: When 1, the low frequency is boosted for the TRK filter. Preset is 0. FLB1ON: When 1, the low frequency is boosted for the FCS filter. Preset is 0. TLB2ON: When 1, the low frequency is boosted for the TRK filter. Preset is 0.

The difference between TLB1ON and TLB2ON is the position where the low frequency is boosted. For TLB1ON, the low frequency is boosted before the TRK jump, and for TLB2ON, after the TRK jump.

The following commands set the boosters. (See §4-20. Filter Composition.)

HBST1, HBST0: TRK and FCS HighBooster setting.

HighBooster has the configuration shown in Fig. 4-22a, and can select three different combinations of coefficients BK1, BK2 and BK3. (See Table 4-23a.) An example of characteristics is shown in Fig. 4-24a. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs).

LB1S1, LB1S0: TRK and FCS LowBooster-1 setting.

LowBooster-1 has the configuration shown in Fig. 4-22b, and can select three different combinations of coefficients BK4, BK5 and BK6. (See Table 4-23b.) An example of characteristics is shown in Fig. 4-24b. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs).

LB2S1, LB2S0: TRK LowBooster-2 setting.

LowBooster-2 has the configuration shown in Fig. 4-22c, and can select three different combinations of coefficients BK7, BK8 and BK9. (See Table 4-23c.) An example of characteristics is shown in Fig. 4-24c. This booster is used exclusively for the TRK filter. The sampling frequency is 88.2kHz (when MCK = 128Fs).

Note) Fs = 44.1kHz

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 0 1 1

SFBK1 SFBK2

0 0 0 0 0 0 0 0 0 0

$34B (preset: $34B 000)

The low frequency can be boosted for brake operation. See §4-12 for brake operation.

SFBK1: When 1, brake operation is performed by setting the LowBooster-1 input to 0.

This is valid only when TLB1ON = 1. Preset is 0.

SFBK2: When 1, brake operation is performed by setting the LowBooster-2 input to 0.

This is valid only when TLB2ON = 1. Preset is 0.

– 85 –

CXD3017Q

HBST1 HBST0

0 1 1

—

0 1

HighBooster setting

–120/128 –124/128 –126/128

96/128 112/128 120/128

BK1 BK2

2 2 2

BK3

Table 4-23a

Fig. 4-22a

BK5

Z

– 1

Z

– 1

BK4

BK6

Fig. 4-22b

BK8

Z

– 1

Z

– 1

BK7

BK9

Fig. 4-22c

LB1S1 LB1S0

0 1 1

—

0 1

LowBooster-1 setting

–255/256 –511/512

–1023/1024

1023/1024 2047/2048 4095/4096

BK4 BK5

1/4 1/4 1/4

BK6

Table 4-23b

LB2S1 LB2S0

0 1 1

—

0 1

LowBooster-12 setting

–255/256 –511/512

–1023/1024

1023/1024 2047/2048 4095/4096

BK7 BK8

1/4 1/4 1/4

BK9

Table 4-23c

– 1

Z

BK1

BK2

BK3

– 1

Z

– 86 –

CXD3017Q

–15

–9

–3

3

9

15

Gain [dB]

–12

–6

0

6

12

100101

Frequency [Hz]

1k 10k

2

3

1

–90

+90

Phase [degree]

–72

–36

0

+36

+72

100101

Frequency [Hz]

1k 10k

2

3

1

Fig. 4-24a. Servo HighBooster characteristics [FCS, TRK] (MCK = 128Fs)

HBST1 = 0 HBST1 = 1, HBST0 = 0 HBST1 = 1, HBST0 = 1

1

2

3

– 87 –

CXD3017Q

–15

–9

–3

3

9

15

Gain [dB]

–12

–6

0

6

12

100101

Frequency [Hz]

1k 10k

–90

+90

Phase [degree]

–72

–36

0

+36

+72

100101

Frequency [Hz]

1k 10k

2

3

1

3

Fig. 4-24b. Servo LowBooster-1 characteristics [FCS, TRK] (MCK = 128Fs)

LB1S1 = 0 LB1S1 = 1, LB1S0 = 0 LB1S1 = 1, LB1S0 = 1

1

2

3

– 88 –

CXD3017Q

–15

–9

–3

3

9

15

Gain [dB]

–12

–6

0

6

12

100101

Frequency [Hz]

1k 10k

–90

+90

Phase [degree]

–72

–36

0

+36

+72

100101

Frequency [Hz]

1k 10k

2

1

3

2

3

1

Fig. 4-24c. Servo LowBooster-2 characteristics [TRK] (MCK = 128Fs)

LB2S1 = 0 LB2S1 = 1, LB2S0 = 0 LB2S1 = 1, LB2S0 = 1

1

2

3

– 89 –

CXD3017Q

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 1 0

IDFSL3 IDFSL2 IDFSL1 IDFSL0

0 0

IDFT1 IDFT0

0 0 0

INVRFDC

$34E (preset: $34E000)

IDFSL3: New DFCT detection output setting.

When 0, only the DFCT signal described in §4-9 is detected and output from the DFCT pin. (default) When 1, the DFCT signal described in §4-9 and the new DFCT signal are switched and output from the DFCT pin. The switching timing is as follows. When the §4-9 DFCT signal is low, the new DFCT signal is output from the DFCT pin. When the §4-9 DFCT signal is high, this DFCT signal is output from the DFCT pin. In addition, the time at which the new DFCT signal can be output after the §4-9 DFCT signal switches to low can also be set. (See IDFT1, 0 of $34E.)

IDFSL3

0 0 1 1

§4-9 DFCT L H L H

§4-9 DFCT

§4-9 DFCT New DFCT

§4-9 DFCT

DFCT pin

IDFSL2: New DFCT detection time setting.

DFCT = high is held for a certain time after new DFCT detection. This command sets that time. When 0, a long hold time. (default) When 1, a short hold time.

IDFSL1: New DFCT detection sensitivity setting.

When 0, a high detection sensitivity. (default) When 1, a low detection sensitivity.

IDFSL0: New DFCT release sensitivity setting.

When 0, a high release sensitivity. (default) When 1, a low release sensitivity.

IDFT1, 0: These commands set the time at which the new DFCT signal can be output (output prohibited

time) after the §4-9 DFCT signal switches to low.

IDFT1

0 0 1 1

IDFT0

0 1 0 1

204.08µs

294.78µs

408.16µs

612.24µs

New DFCT signal output prohibited time

∗

∗: preset

INVRFDC: RFDC signal polarity inverted input setting.

When 0, the RFDC signal polarity is set to non-inverted. (default) When 1, the RFDC signal polarity is set to inverted.

– 90 –

CXD3017Q

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 1 1 0 1 FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1 —

When D15 = D14 = D13 = D12 = 1 ($34F)

D11 = 0, D10 = 1 FBIAS register write FB9 to FB1: Data; two's complement data, FB9 = MSB.

For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 × VDD/4 and FB9 to FB1 = 100000000 to –256/256 × VDD/4 respectively. (VDD: supply voltage)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 1 1 1 0 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 —

When D15 = D14 = D13 = D12 = D11 = 1 ($34F)

D10 = 0 FBIAS LIMIT register write FBL9 to FBL1: Data; data compared with FB9 to FB1, FBL9 = MSB.

When using the FBIAS register in counter mode, counter operation stops when the value of FB9 to FB1 matches with FBL9 to FBL1.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 1 1 0 0 TV9 TV8 TV7 TV6 TV5 TV4 TV3 TV2 TV1 TV0

When D15 = D14 = D13 = D12 = 1 ($34F)

D11 = 0, D10 = 0 TRVSC register write TV9 to TV0: Data; two's complement data, TV9 = MSB.

For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 × VDD/4 and TV9 to TV0 = 1100000000 to –256/256 × VDD/4 respectively. (VDD: supply voltage)

Notes) • When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to

each bit TV8 to TV0 during external write are read out.

• When reading out internally measured values and then writing these values externally, set TV9 the same as TV8.

$34F

– 91 –

CXD3017Q

$35 (preset: $35 58 2D)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

FT1 FT0 FS5 FS4 FS3 FS2 FS1 FS0 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0

FT1, FT0, FTZ: Focus search-up speed

Default value: 010 (0.673 × VDDV/s) Focus drive output conversion

FT1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 0 1 1 1 1

1.35 × VDD

0.673 × VDD

0.449 × VDD

0.336 × VDD

1.79 × VDD

1.08 × VDD

0.897 × VDD

0.769 × VDD

FT0 FTZ Focus search speed [V/s]

FS5 to FS0: Focus search limit voltage

Default value: 011000 ((1 ± 24/64) × VDD/2, VDD: PWM driver supply voltage) Focus drive output conversion

FG6 to FG0: AGF convergence gain setting value

Default value: 0101101

$36 (preset: $36 0E 2E)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 DTZC TJ5 TJ4 TJ3 TJ2 TJ1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0

DTZC: DTZC delay (8.5/4.25µs, when MCK = 128Fs)

Default value: 0 (4.25µs)

TJ5 to TJ0: Track jump voltage

Default value: 001110 ((1 ± 14/64) × VDD/2, VDD: PWM driver supply voltage) Tracking drive output conversion

SFJP: Surf jump mode on/off

The tracking PWM output is generated by adding the tracking filter output and TJReg (TJ5 to TJ0), by setting D7 to 1 (on)

TG6 to TG0: AGT convergence gain setting value

Default value: 0101110

∗

∗: preset, VDD: PWM driver supply voltage

– 92 –

CXD3017Q

$37 (preset: $37 50 BA)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ

AGGF AGGT

AGV1 AGV2

AGHS AGHT

FZSH, FZSL: FZC (Focus Zero Cross) slice level

Default value: 01 (1/8 × VDD/2, VDD: supply voltage); FE input conversion

FZSH

0 0 1 1

0 1 0 1

1/4 × VDD/2 1/8 × VDD/2 1/16 × VDD/2 1/32 × VDD/2

FZSL Slice level

SM5 to SM0: Sled move voltage

Default value: 010000 ((1 ± 16/64) × VDD/2, VDD: PWM driver supply voltage) Sled drive output conversion

AGS: AGCNTL self-stop on/off

Default value: 1 (on)

AGJ: AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms,

when MCK = 128Fs) Default value: 0 (63ms)

AGGF: Focus AGCNTL internally generated sine wave amplitude (small/large)

Default value: 1 (large)

AGGT: Tracking AGCNTL internally generated sine wave amplitude (small/large)

Default value: 1 (large)

AGGF

0 (small) 1 (large)

∗

1/32 × VDD/2 1/16 × VDD/2

1/16 × VDD/2 1/8 × VDD/2

AGGT

0 (small) 1 (large)

∗

FE/TE input conversion

AGV1: AGCNTL convergence sensitivity during high sensitivity adjustment; high/low

Default value: 1 (high)

AGV2: AGCNTL convergence sensitivity during low sensitivity adjustment; high/low

Default value: 0 (low)

AGHS: AGCNTL high sensitivity adjustment on/off

Default value: 1 (on)

AGHT: AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs)

Default value: 0 (256ms)

∗

∗: preset

– 93 –

CXD3017Q

$38 (preset: $38 00 00)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

VCLM

VCLC

FLM FLC0

RFLM

RFLC AGF AGT

DFSW

LKSW TBLM TCLM

FLC1 TLC2 TLC1 TLC0

DC offset cancel. See §4-3.

∗

VCLM: VC level measurement (on/off) VCLC: VC level compensation for FCS In register (on/off)

∗

FLM: Focus zero level measurement (on/off) FLC0: Focus zero level compensation for FZC register (on/off)

∗

RFLM: RF zero level measurement (on/off) RFLC: RF zero level compensation (on/off)

Automatic gain control. See §4-6.

AGF: Focus auto gain adjustment (on/off) AGT: Tracking auto gain adjustment (on/off)

Misoperation prevention circuit

DFSW: Defect disable switch (on/off)

Setting this switch to 1 (on) disables the defect countermeasure circuit.

LKSW: Lock switch (on/off)

Setting this switch to 1 (on) disables the sled free-running prevention circuit.

DC offset cancel. See §4-3.

TBLM: Traverse center measurement (on/off)

∗

TCLM: Tracking zero level measurement (on/off) FLC1: Focus zero level compensation for FCS In register (on/off) TLC2: Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off)

Note) Commands marked with ∗ are accepted every 2.9ms. (when MCK = 128Fs)

All commands are on when 1.

– 94 –

CXD3017Q

Coefficient RAM address

D15 D14 D13 D12 D11 D10 D9 D8

DAC

SD6

SD5 SD4 SD3 SD2 SD1 SD0

When $3A command SVDA = 0 DAC: Serial data readout DAC mode setting.

When 0, serial data cannot be read out. (default) When 1, serial data can be read out.

SD6 to SD0: These bits select the serial readout data.

$39 (preset: $390000)

D14 D13 D12 D11 D10 D9 D8

Readout data

Readout data length

SD6

SD5 SD4 SD3 SD2 SD1 SD0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0

1 1 1 1 0 0 0 0 1 1 0 0 0 0 0

1 1 1 1 1 0 0 0 1 0 1 0 0 0 0

1 1 0 0 0 1 1 0

∗ ∗ ∗

1 1 0 0

1 0 1 0 0 1 0 1

∗ ∗ ∗

1 0 1 0

Coefficient RAM data Data RAM data RF AVRG register RFDC input signal FCS Bias register TRVSC register DFCT count VC AVRG register FE AVRG register TE AVRG register RFDC (Bottom) RFDC (Peak) RFDC (Peak – Bottom) FE input signal TE input signal SE input signal VC input signal

8 bits

16 bits

8 bits 8 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits

Data RAM address

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

∗: don't care

Note) When $3A SVDA is changed, select the readout data again.

– 95 –

CXD3017Q

Data RAM address

When $3A command SVDA = 1 DAC: This command selects whether to set readout data for the left or right channel.

When 0, right channel readout data is selected. (default) When 1, left channel readout data is selected.

SD6 to SD0: These bits select the data to be output from the left or right channel.

D14 D13 D12 D11 D10 D9 D8

Readout data

Readout data length

SD6

SD5 SD4 SD3 SD2 SD1 SD0

0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0

1 1 1 1 1 1 0 0 0 0 0

1 1 1 1 1 0 1 0 0 0 0

1 1 0 0

∗ ∗ ∗

1 1 0 0

1 0 1 0

∗ ∗ ∗

1 0 1 0

Data RAM data RF AVRG register RFDC input signal FCS Bias register TRVSC register VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal

16 bits

8 bits 8 bits 9 bits 9 bits 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits

1 0 0 0 0 0 0 0 0 0 0 0

∗: don't care

∗1

Right channel preset

∗2

Left channel preset

Note) Coefficient RAM data cannot be output from the audio DAC side.

Do not output RFDC (peak, bottom, peak-bottom) or the DFCT count from the audio DAC side. When $3A SVDA is changed, select the readout data again. The DFCT count counts the number of times the DFCT signal rises while $3994 is set. Readout outputs the DFCT count at that time.

∗1 ∗2

– 96 –

CXD3017Q

$3A (preset: $3A0000)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

FBON

0 0 0 0

FIFZC

0 FPS1 FPS0 TPS1 TPS0

SVDA

0 0 0

FIFZC: This selects the FZC slice level setting command.

When 0, the FZC slice level is determined by the $37 FZSH and FZSL setting values. (default) When 1, the FZC slice level is determined by the $3F8 FIFZB3 to FIFZB0 and FIFZA3 to FIFZA0 setting values. This allows more detailed setting and the addition of hysteresis compared to the $37 FZSH and

FZSL setting. FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block. TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block.

These are effective for increasing the overall gain in order to widen the servo band, etc.

Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However,

6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the

relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00.

FPS1

0 0 1 1

FPS0

0 1 0 1

0dB

+6dB +12dB +18dB

Relative gain

TPS1

0 0 1 1

TPS0

0 1 0 1

0dB

+6dB +12dB +18dB

Relative gain

∗

∗: preset

∗

FBON: FBIAS (focus bias) register operation setting.

FBON

0 1

FBIAS (focus bias) register addition off. FBIAS (focus bias) register addition on.

Processing

SVDA: This allows the data set by the $39 command to be output through the audio DAC.

When 0, audio is output. (default) When 1, the data set by the $39 command is output.

– 97 –

CXD3017Q

$3B (preset: $3B E0 50)

SFOX, SFO2, SFO1:

FOK slice level Default value: 011 (28/256 × VDD/2, VDD = supply voltage) RFDC input conversion

SFOX

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

16/256 × VDD/2 20/256 × VDD/2 24/256 × VDD/2 28/256 × VDD/2 32/256 × VDD/2 40/256 × VDD/2 48/256 × VDD/2 56/256 × VDD/2

SFO2

0 1 0 1 0 1 0 1

SFO1 Slice level

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SFO2 SFO1 SDF2 SDF1

MAX2 MAX1 SFOX BTF

D2V2 D2V1 D1V2 D1V1 0 0 0 0

∗: preset

∗

SDF2, SDF1: DFCT slice level

Default value: 10 (0.0313 × VDD) RFDC input conversion

SDF2

0 0 1 1

0 1 0 1

0.0156 × VDD

0.0234 × VDD

0.0313 × VDD

0.0391 × VDD

SDF1 Slice level

MAX2, MAX1: DFCT maximum time (MCK = 128Fs)

Default value: 00 (no timer limit)

MAX2

0 0 1 1

0 1 0 1

No timer limit

2.00ms

2.36

2.72

MAX1 DFCT maximum time

∗: preset, VDD: supply voltage

∗

∗: preset

∗

– 98 –

CXD3017Q

D1V2, D1V1: Peak hold 1 for DFCT signal generation

Count-down speed setting Default value: 01 (0.688 × VDD/ms, 352.8kHz)

[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter.

D2V2

0 0 1 1

0 1 0 1

22.05

44.1

88.2

176.4

0.0431 × VDD

0.0861 × VDD

0.172 × VDD

0.344 × VDD

D2V1

Count-down speed [V/ms] [kHz]

[V/ms] [kHz]

176.4

352.8

705.6

1411.2

0.344 × VDD

0.688 × VDD

1.38 × VDD

2.75 × VDD

D1V2

0 0 1 1

0 1 0 1

D1V1

Count-down speed

∗: preset, VDD: supply voltage

∗

∗: preset, VDD: supply voltage

∗

BTF: Bottom hold double-speed count-up mode for MIRR signal generation

On/off (default: off) On when 1.

D2V2, D2V1: Peak hold 2 for DFCT signal generation

Count-down speed setting Default value: 01 (0.086 × VDD/ms, 44.1kHz)

[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter.

– 99 –

CXD3017Q

$3C (preset: $3C 00 80)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

COSS COTS

CETZ CETF

COT2 COT1 MOT2 0

BTS1 BTS0 MRC1 MRC0 0 0 0 0

COSS, COTS: These select the TZC signal used when generating the COUT signal.

STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) DTZC is the delayed phase STZC. (The delay time can be selected by D14 of $36.) HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz. See §4-13.

CETZ: Normally, the input from the TE pin enters the TRK filter and is used to generate the TZC

signal. However, the input from the CE pin can also be used. This function is for the center error servo. When 0, the TZC signal is generated by using the signal input to the TE pin. When 1, the TZC signal is generated by using the signal input to the CE pin.

CETF: When 0, the signal input to the TE pin is input to the TRK servo filter.

When 1, the signal input to the CE pin is input to the TRK servo filter.

These commands output the TZC signal. COT2, COT1: The COUT signal is replaced by the TZC signal. Concretely, the TZC signal is output from the

COUT pin and the TZC signal is used for auto sequence instead of the COUT signal.

COSS

1 0 0

—

0 1

STZC HPTZC DTZC

COTS TZC

∗: preset, —: don't care

∗

BTS1

0 0 1 1

0 1 0 1

1 2 4 8

BTS0 Number of count-up steps per cycle MRC1

0 0 1 1

0 1 0 1

5.669

∗

11.338

22.675

45.351

MRC0 Setting time [µs]

∗: preset (when MCK = 128Fs)

∗

MOT2: The MIRR signal is replaced by the STZC signal. Concretely, the STZC signal is output from

the MIRR pin and the STZC signal is used for generating the COUT signal instead of the MIRR signal.

These commands set the MIRR signal generation circuit. BTS1, BTS0: These set the count-up speed for the bottom hold value of the MIRR generation circuit.

The time per step is approximately 708ns (when MCK = 128Fs). The preset value is BTS1 = 1, BTS0 = 0 like the CXD2586R. These bits are valid only when BTF of $3B is 0.

MRC1, MRC0: These set the minimum pulse width for masking the MIRR signal of the MIRR generation circuit.

As noted in §4-9, the MIRR signal is generated by comparing the waveform obtained by subtracting the bottom hold value from the peak hold value with the MIRR comparator level. Strictly speaking, however, for MIRR to become high, these levels must be compared continuously for a certain time. These bits set that time. The preset value is MRC1 = 0, MRC0 = 0 like the CXD2586R.

COT2

1 0 0

—

1 0

STZC HPTZC COUT

COT1

COUT pin output

∗: preset, —: don't care

∗

– 100 –

CXD3017Q

$3D (preset: $3D 00 00)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SFID SFSK THID THSK ABEF TLD2 TLD1 TLD0 0 0 0 0 0 0 0 0

SFID: SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK

filter second-stage output. When the low frequency component of the tracking error signal obtained from the RF amplifier is attenuated, the low frequency can be amplified and input to the SLD servo filter.

SFSK: Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally, the

DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M00 can be kept uniform by adjusting the K30 value even during the above switching.

THID: TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK

filter second-stage output. When signals other than the tracking error signal from the RF amplifier are input to the SE input pin, the signal transmitted from the TE pin can be obtained as TRK hold filter input.

THSK: Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally, the

DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M18 can be kept uniform by adjusting the K46 value even during the above switching.

∗

See "§4-20. Filter Composition" regarding the SFID, SFSK, THID and THSK commands.

ABEF: The focus error (FE) and tracking error (TE) can be generated internally.

When 0, the FE and TE signal input mode results. Input each error signal through the FE and TE pins. (default) When 1, the FE and TE signal generation mode results and the FE and TE signals are generated internally.

TLD0 to 2: These turn on and off SLD filter correction independently of the TRK filter.

See $38 (TLC0 to TLC2) and Fig. 4-3.

TLC0

0

1

—

0 1

OFF

ON

OFF

ON ON

TLD0

VC level correction

TRK filter SLD filter

∗: preset, —: don't care

∗

TLC1

0

1

—

0 1

OFF

ON

OFF

ON ON

TLD1

Tracking zero level correction

TRK filter SLD filter

∗

TLC2

0

1

—

0 1

OFF

ON

OFF

ON ON

TLD2

Traverse center correction

TRK filter SLD filter

∗