Page 1
—1—
E97944-TE
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Absolute Maximum Ratings (Ta = 25 °C)
• Supply voltage VCC1,VCC2 –0.3 to +5.5 V
VCC3 –0.3 to +10.0 V
• Storage temperature
Tstg –55 to +150 °C
• Allowable power dissipation
PD 880 mW
(when mounted on a substrate)
Operating Conditions
• Supply voltage VCC1, VCC2 4.75 to 5.3 V
VCC3 4.75 to 9.45 V
• Operating temperature
Topr –20 to +75 °C
Description
The CXA3185/3186N is a monolithic TV tuner IC
which integrates local oscillator and mixer circuits for
VHF band, local oscillator and mixer circuits for UHF
band, an IF amplifier and a tuning PLL onto a single
chip, enabling further miniaturization of the tuner.
Features
• Low noise figure
• Low power consumption (5 V, 54 mA typ.)
• On-chip tuning PLL (3-wire bus format)
• Selection of frequency steps 31.25 kHz, 50 kHz
and 62.5 kHz
• On-chip 4-output band switch
Applications
• TV tuners
• VCR tuners
• CATV tuners
Structure
Bipolar silicon monolithic IC
All Band TV Tuner IC with On-chip PLL
30 pin SSOP (Plastic)
CXA3185/3186N
Note) Electrostatic discharge strength is weak, and care should be taken in handling this IC.
Page 2
—2—
CXA3185/3186N
Block Diagram and Pin Configuration
Input
Buffer
Bias
USW
IF AMP
CL
DA
CE
FMT
BVL
BVH
BU
VCC1
MIXout1
MIXout2
GND1
MS
VHFin
UHFin1
UHFin2
Shift
Register
Band
SW
Driver
V.REG
VHF
MIX
UHF
MIX
Buffer
VHF
OSC
UHF
OSC
Buffer
Buffer
Phase
Detector
Charge
Pump
LOCK
Det
Divider
14/15bit
Prescaler
1/8
REF
OSC
Divider
1/512,640,1024
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VOSC1
GND
VOSC2
UOSCB1
UOSCE1
UOSCE2
UOSCB2
V
CC2
CPE
V
CC3
CPO
REFOSC
GND
IF OUT
LOCK
16
17
18
23
24
25
26
27
28
29
30
20
21
22
19
Page 3
—3—
CXA3185/3186N
Pin Description
Pin
Symbol Equivalent circuit
Pin voltage
Description
No. (V)
1
2
3
4
5
6
7
8
9
10
11
CL
DA
CE
FMT
BVL
BVH
BU
VCC1
MIXout1
MIXout2
GND1
—
—
1.25
(when open)
ON : Vcc3
OFF : 0
—
Clock input.
Data input.
Enable pin.
4 : Output for FM TRAP.
5 : Power supply output for
VL band.
6 : Power supply output for
VH band.
7 : Power supply output for
UHF band.
The selected band pin goes
High.
Analog circuit power supply.
Mixer outputs.
Analog circuit GND.
5k
100k
1
22
V
CC2
5k
100k
2
22
V
CC2
3
150k
50k
VCC2
22
4
5
6
7
30
VCC3
20k
9
10
—
Page 4
—4—
CXA3185/3186N
Pin
Symbol Equivalent circuit
Pin voltage
Description
No. (V)
12
13
14
15
16
18
17
19
20
21
22
MS
VHFin
UHFin1
UHFin2
VOSC1
VOSC2
GND
UOSCB1
UOSCE1
UOSCE2
UOSCB2
1.5
(when open)
2.3
(VHF)
0
(UHF)
0
(VHF)
2.3
(UHF)
0
(VHF)
2.3
(UHF)
3.0
(VHF)
3.1
(UHF)
3.5
(VHF)
5.0
(UHF)
—
3.2
(VHF)
2.9
(UHF)
—
(VHF)
2.4
(UHF)
—
(VHF)
2.4
(UHF)
3.2
(VHF)
2.9
(UHF)
Frequency step mode
selection. Five modes can be
selected according to the
applied voltage.
VHF input.
The input format is unbalanced
input.
UHF input.
The input method can be
selected from balanced input
or unbalanced input.
External resonance circuit
connection for VHF oscillator.
GND
External resonance circuit
connection for UHF oscillator.
50k
VCC2
120k
1213
14
15
3k 3k
18 16
8
8p
3k
3k
15p
50
V
CC1
600
19 2220 21
3k
3k
V
CC1
Page 5
—5—
CXA3185/3186N
Pin
Symbol Equivalent circuit
Pin voltage
Description
No. (V)
23
24
25
26
27
28
29
30
VCC2
GND2
IFOUT
LOCK
CPE
CPO
REFOSC
VCC3
—
—
2.3
5.0
(Lock)
0.2
(UNLock)
0.6
2.0
4.3
—
PLL circuit power supply.
PLL circuit GND.
IF output.
LOCK detection.
High when locked, Low when
unlocked.
NPN transistor connection for
varicap diode drive.
Charge pump output.
Connect a loop filter.
Crystal connection for
reference oscillator.
Power supply for external
supply.
25
8
40
V
CC1
26
22
VCC2
40k
28
27
22
VCC2
200
500
20k
29
60k
30p 30p
—
—
Page 6
—6—
CXA3185/3186N
Electrical Characteristics See the Electrical Characteristics Measurement Circuit.
Circuit Current (VCC=5 V, Ta=25 °C)
Item
Circuit current A
Circuit current D
Symbol
AICCV
AICCU
DICC
Measurement conditions
VCC1 current, Band switch output
open during VHF operation
VCC1 current, Band switch output
open during UHF operation
VCC2 current
Min. Typ. Max. Unit
30 41 55 mA
31 42 56 mA
7 11 15 mA
Item
Conversion gain
∗1
Noise figure ∗1,
∗2
1 % cross
modulation ∗1,
∗3
Maximum output power
Switch ON drift
∗4
Supply voltage drift
∗4
Symbol
CG1
CG2
CG3
CG4
NF1
NF2
NF3
NF4
CM1
CM2
CM3
CM4
Pomax
∆fsw1
∆fsw2
∆fsw3
∆fsw4
∆fst1
∆fst2
∆fst3
∆fst4
Measurement conditions
VHF operation fRF = 55 MHz
VHF operation fRF = 360 MHz
UHF operation fRF = 360 MHz
UHF operation fRF = 800 MHz
VHF operation fRF = 55 MHz
VHF operation fRF = 360 MHz
UHF operation fRF = 360 MHz
UHF operation fRF = 800 MHz
VHF operation
fD = 55 MHz, fUD = ±12 MHz
VHF operation
fD = 360 MHz, fUD = ±12 MHz
UHF operation
fD = 360 MHz, fUD = ±12 MHz
UHF operation
fD = 800 MHz, fUD = ±12 MHz
50 Ω load saturation output
VHF operation fOSC = 100 MHz
∆f from 3 s to 3 min after switch ON
VHF operation fOSC = 405 MHz
∆f from 3 s to 3 min after switch ON
UHF operation fOSC = 405 MHz
∆f from 3 s to 3 min after switch ON
UHF operation fOSC = 845 MHz
∆f from 3 s to 3 min after switch ON
VHF operation fOSC = 100 MHz
∆f when VCC 5 V changes ±5 %
VHF operation fOSC = 405 MHz
∆f when VCC 5 V changes ±5 %
UHF operation fOSC = 405 MHz
∆f when VCC 5 V changes ±5 %
UHF operation fOSC = 845 MHz
∆f when VCC 5 V changes ±5 %
Min. Typ. Max. Unit
21 24 27 dB
22 25 28 dB
26 29 32 dB
27 30 33 dB
12 15 dB
11 14 dB
8.5 12.5 dB
9.5 13.5 dB
97 101 dBµ
96 100 dBµ
92 96 dBµ
88 92 dBµ
+5 +10 dBm
±300 kHz
±400 kHz
±400 kHz
±500 kHz
±150 kHz
±250 kHz
±200 kHz
±250 kHz
OSC/MIX/IF Amplifier Block
Page 7
—7—
CXA3185/3186N
∗1
Measured value for untuned inputs.
∗2
Noise figure is the direct-reading value of NF meter in DSB.
∗3
Desired signal (fD) input level is –30 dBm. Undesired signal (fUD) is 100 kHz, 30 % AM.
The measurement value is undesired signal level, it measured with a spectrum analyzer at S/I=46 dBm.
∗4
Value when the PLL is not operating.
Item
CL and DA pins
“H” level input voltage
“L” level input voltage
“H” level input current
“L” level input current
CE pins
“H” level input voltage
“L” level input voltage
“H” level input current
“L” level input current
CPO (charge pump)
Output current
Leak current
LOCK
“H” output voltage
“L” output voltage
REFOSC
Oscillator
frequency range
Input capacitance
Drive level
BVL, BVH, BU (Band SW)
Output current
Saturation voltage
Leak current
FMT (Band SW)
Output current
Saturation voltage
Leak current
Bus timing
Data setup time
Data hold time
Enable waiting time
Enable setup time
Enable hold time
Symbol
VIH
VIL
IIH
IIL
VIHE
VILE
IIHE
IILE
ICPO
LeakCP
VLOCKH
VLOCKL
FXTOSC
CXTOSC
VXTOSC
IBS1
VSAT1
LeakBS1
IBS2
VSAT2
LeakBS2
tSD
tHD
tWE
tSE
tHE
Measurement conditions
VIH = VCC
VIL = GND
VIHE=VCC
VILE=GND
When locked
When unlocked
When ON
When ON Sink current = 20 mA
When OFF
When ON
When ON Sink current = 5 mA
When OFF
See Timing Chart on Page 15
See Timing Chart on Page 15
See Timing Chart on Page 15
See Timing Chart on Page 15
See Timing Chart on Page 15
Min. Typ. Max. Unit
3 VCC V
GND 1.5 V
0 –0.1 µA
–1 –2 µA
3 VCC V
GND 1.5 V
100 130 µA
–30 –45 µA
±35 ±50 ±75 µA
30 nA
VCC–0.5 VCC V
0 0.5 V
3 12 MHz
17.5 19 20.5 pF
200 400 mVp-p
–25 mA
100 200 mV
0.5 3 µA
–7 mA
75 150 mV
0.03 0.1 µA
300 ns
600 ns
300 ns
300 ns
600 ns
PLL Block
Page 8
—8—
CXA3185/3186N
Electrical Characteristics Measurement Circuit
CXA3185/3186N
CL
DA
CE
FMT
BVL
BVH
BU
V
CC
1
MIX out1
MIX out2
GND1
MS
VHF in
UHFin1
UHFin2
V
CC
3
REFOSC
CPO
CPE
LOCK
IFOUT
GND2
V
CC
2
UOSCB2
UOSCE2
UOSCE1
UOSCB1
VOSC2
GND
VOSC1
100p
XTAL
1n
LOCK IF OUT
47k 0.047µ
8200p
2SC2785
33p
22k
+30V
3.3µ 1n
+5V
56p
47k
7p
47k
1T363 1T363
0.5p
0.5p
47k
47k
16p
1n
CLOCK DATA ENABLE
FMT BVL BVH BU
2k
56p 56p
100
1n
1n
+5V
3.3µ
1n 1n 1n
VHF IN
1n
UHF IN
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15
4.5t 4.5t
1T363
1T362
47k
150p
47k
3.0ø
2.5t
1n
47k
51
BVH
3.2ø
5.5t
1n
47k
51
0.5p
4MHz
1.2k
1p
8p 4p 8p
56p
2.5ø2.5t
1617182021222324252627282930 19
BVL
Page 9
—9—
CXA3185/3186N
Description of Functions
The CXA3185/3186N is a terrestrial wave broadcast tuner IC which converts frequencies to IF in order to
tune and detect only the desired reception frequency of VHF, CATV and UHF band signals.
In addition to the mixer, local oscillator and IF amplifier circuits required for frequency conversion to IF, this
IC also integrates a PLL circuit for local oscillator frequency control onto a single chip.
The functions of the various circuits are described below.
1. Mixer circuit
This circuit outputs the frequency difference between the signal input to VHFIN or UHFIN and the local
oscillation signal.
2. Local oscillator circuit
A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and
inductance.
3. IF amplifier circuit
This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output
stage.
4. PLL circuit
This PLL circuit fixes the local oscillator frequency to the desired frequency. It consists of a prescaler, main
divider, reference divider, phase comparator, charge pump and reference oscillator. The control format
supports the 3-wire bus format. The following four modes can be selected according to the combination of
the frequency division values of the main and reference dividers.
Mode Main divider Reference divider
A-0 15 bit 1024 fixed
A-1 14 bit 512 fixed
A-2 15 bit 640 fixed
A-3/4 15 bit 512 fixed
Page 10
—10—
CXA3185/3186N
Description of Analog Block Operation
(See the Electrical Characteristics Measurement Circuit.)
VHF oscillator circuit
• This circuit is a differential amplifier type oscillator circuit. Pin 18 is the output and Pin 16 is the input.
Oscillation is performed by connecting an LC resonance circuit including a varicap to Pin 18 via coupled
capacitance, inputting to Pin 16 with feedback capacitance, and applying positive feedback.
• The amplifier between Pins 16 and 18 has an extremely high gain. Therefore, care should be taken to
avoid creating parasitic capacitance, resistance or other feedback loops as this may produce abnormal
oscillation.
VHF mixer circuit
• The mixer circuit employs a double balance mixer with little local oscillation signal leakage.
The input format is base input type, with Pin 12 grounded and the RF signal input to Pin 13.
• The RF signal is inserted from the oscillator, converted to IF frequency and output from Pins 9 and 10.
• Pins 9 and 10 are open collectors, so power must be supplied externally. The electric potential of Pins 9
and 10 at this time must be DC 4.0 V or more.
UHF oscillator circuit
• This oscillator circuit is designed so that two collector ground type Colpitts oscillators perform differential
oscillation operation via an LC resonance circuit including a varicap. Connect resonance capacitance
which consists of colpitts oscillator between Pins 19 and 20, Pins 20 and 21, and Pins 21 and 22. Then
an LC resonance circuit including a varicap diode is connected between Pins 19 and 22.
UHF mixer circuit
• This circuit employs a double balance mixer like the VHF mixer circuit.
The input format is base input type, with Pins 14 and 15 as the RF input pins. The input method can be
selected from balanced input consisting of differential input to Pins 14 and 15 or unbalanced input
consisting of grounding Pin 14 via a capacitor and input to Pin 15.
• Pins 9 and 10 are the mixer outputs.
• Pins 9 and 10 are open collectors, so power must be supplied externally. The electric potential of Pins 9
and 10 at this time must be DC 4.0 V or more.
IF amplifier circuit
• The signals frequency converted by the mixer are output from Pins 9 and 10, and at the same time are
AC coupled inside the IC and input to the IF amplifier.
• Single-tuned filters are connected to Pins 9 and 10 in order to improve the interference characteristics of
the IF amplifier.
• The signal amplified by the IF amplifier is output from Pin 25.
The output impedance is approximately 75 Ω.
Page 11
—11—
CXA3185/3186N
Description of PLL Block
The PLL on this IC supports the 3-wire bus control format.
The serial data is input to the DA, CL and CE pins. The data is loaded to the shift register at the clock rise,
and latched at the enable fall.
1) Mode Setting Method
The modes for each frequency step are set according to the MS pin voltage.
Symbol
CE
CL
DA
LOCK
3-wire bus control
Enable input
Clock input
Data input
Lock signal output
Mode
A-0
A-1
A-2
A-3
A-4
MS pin voltage
0 to 0.15VCC
OPEN
0.45VCC to 0.55VCC
0.65VCC to 0.75VCC
0.85VCC to VCC
Main
divider
15 bit
14 bit
15 bit
15 bit
15 bit
Reference
divider
1024
512
640
512
512
Reference
frequency
∗
3.90625 kHz
7.8125 kHz
6.25 kHz
7.8125 kHz
7.8125 kHz
Frequency
step
∗
31.25 kHz
62.5 kHz
50 kHz
62.5 kHz
62.5 kHz
Control
word length
Total 19 bits
Total 18 bits
Total 19 bits
Total 19 bits
Total 27 bits
∗ Frequency step is for when X’tal OSC = 4 MHz.
2) Programming
• The VCO lock frequency is obtained according to the following formula.
fosc = fref × 8 × (32 M + S)
fosc: local oscillator frequency
fref : reference frequency
8 : prescaler fixed frequency division ratio
M : main divider frequency division ratio
S : swallow counter frequency division ratio
The variable frequency division ranges of M and S are as follows, and are set as binary.
32 ≤ M ≤ 1023 (32 ≤ M ≤ 511 for A-1 mode)
0 ≤ S ≤ 31
• The PLL control data is comprised of the above frequency data and the band switch control data.
Page 12
—12—
CXA3185/3186N
2-1) The CXA3185N control format is as follows.
2-1-1 : A-0/A-2/A-3 Modes (19-bit data format)
Front bit ←MSB LSB→
2-1-2 : A-1 Mode (18-bit data format)
Front bit ←MSB LSB→
2-1-3 : A-4 Mode (27-bit data format)
Front bit ←MSB LSB→
BU FMT BVH BVL M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0
BU FMT BVH BVL M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0
∗) X: Don’t care
S0 to : swallow counter frequency division ratio setting
M0 to : main divider frequency division ratio setting
BVL : VL band switch control (output PNP Tr ON when “1”)
BVH : VH band switch control (output PNP Tr ON when “1”)
FMT : FM trap switch control (output PNP Tr ON when “1”)
BU : UHF band switch control (output PNP Tr ON when “1”)
CP : charge pump current switching (200 µA when “1”, 50 µA when “0”)
T1 : test mode selection (when “1”)
CD : charge pump OFF (when “1”)
R0, R1: reference divider frequency division ratio setting (See the table below.)
Reference Divider Frequency Division Ratio Table
BU FMT BVH BVL M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0
X CP T1 CD X R1 R0 X
R1
0
1
X
R0
1
1
0
Reference divider
1024
512
640
∗) X: Don’t care
Page 13
—13—
CXA3185/3186N
2-2) The CXA3186N control format is as follows.
The BU and FMT data order is switched for the CXA3185N.
In this case the control format is as follows.
2-2-1 : A-0/A-2/A-3 Modes (19-bit data format)
Front bit ←MSB LSB→
2-2-2 : A-1 Mode (18-bit data format)
Front bit ←MSB LSB→
2-2-3 : A-4 Mode (27-bit data format)
Front bit ←MSB LSB→
S0 to : swallow counter frequency division ratio setting
M0 to : main divider frequency division ratio setting
BVL : VL band switch control (output PNP Tr ON when “1”)
BVH : VH band switch control (output PNP Tr ON when “1”)
FMT : FM trap switch control (output PNP Tr ON when “1”)
BU : UHF band switch control (output PNP Tr ON when “1”)
CP : charge pump current switching (200 µA when “1”, 50 µA when “0”)
T1 : test mode selection (when “1”)
CD : charge pump OFF (when “1”)
R0, R1: reference divider frequency division ratio setting (See the table below.)
Reference Divider Frequency Division Ratio Table
FMT BU BVH BVL M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0
FMT BU BVH BVL M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0
FMT BU BVH BVL M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0
X CP T1 CD X R1 R0 X
∗) X: Don’t care
∗) X: Don't care
R1
0
1
X
R0
1
1
0
Reference divider
1024
512
640
Page 14
—14—
CXA3185/3186N
3) 3-wire Bus Data Format
Band switch data Frequency data
DATA
CLOCK
ENABLE
BU
/FMT
FMT
/BU
BVH BVL M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0
1 4 5 18
Band switch data Frequency data
DATA
CLOCK
ENABLE
BU
/FMT
FMT
/BU
BVH BVL M8 M7 M6 M5 M4 M3 M2 M1 M0 S4 S3 S2 S1 S0
1 4 5
M9
19
Band switch data Frequency data
DATA
CLOCK
ENABLE
BU
/FMT
FMT
/BU
BVH BVL M8 S3 S2 S1 S0 X CP T1 CD X R1 R0 X
1 4 5
M9
27
Test data
2019
A-1 Mode (18-bit data format)
A-0/A-2/A-3 Modes (19-bit data format)
A-4 Mode (27-bit data format)
Page 15
—15—
CXA3185/3186N
4) Bus Timing Chart
tSD tHD
3V
1.5V
3V
1.5V
3V
1.5V
tHE
DATA
CLOCK
ENABLE
tSE
tSD = Data setup time
tHD = Data hold time
tSE = Enable setup time
tHE = Enable hold time
tWE = Enable waiting time
t
WE
Page 16
—16—
CXA3185/3186N
Circuit current vs. Supply voltage 1
AI
CC
- Circuit current [mA]
VCC1 - Supply voltage [V]
Circuit current vs. Supply voltage 2
DI
CC
- Circuit current [mA]
VCC2 - Supply voltage [V]
Band SW output voltage vs. Output current (BU, BVH, BVL)
Output voltage [V]
Output current [mA]
Band SW output voltage vs. Output current (FMT)
Output voltage [V]
Output current [mA]
0 1 2 3 4 65
I/O characteristics (Untuned input)
IF output level [dBm]
RF input level [dBm]
45
40
35
UHF
4.7 4.8 4.9 5.0 5.2 5.3 5.4
15
10
5
4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4
VCC3=9V
VCC3=5V
9.2
9.0
8.8
8.6
5.0
4.8
4.6
4.4
0 5 10 15 20 25
9.2
9.0
8.8
8.6
5.0
4.8
4.6
4.4
VCC3=9V
VCC3=5V
20
0
–20
–40
–60
–60 –50 –40 –30 –20 –10 0 10
5.1
VHF
f
RF=100MHz (VHF)
fRF=450MHz (UHF)
fIF is both f=45MHz
Page 17
—17—
CXA3185/3186N
Conversion gain vs. Reception frequency (Untuned input)
CG - Conversion gain [dB]
PCS beat characteristics
IF output level [dBm]
SG output level [dBm]
(fP level)
Noise figure vs. Reception frequency (Untuned input, in DSB)
NF - Noise figure [dB]
Reception frequency [MHz]
Next adjacent cross modulation vs. Reception frequency
(Untuned input)
CM - Cross modulation [dBµ]
Reception frequency [MHz]
Oscillation frequency power supply fluctuation (PLL off)
+B drift [kHz]
Oscillation frequency [MHz]
Reception frequency [MHz]
fIF=45MHz
40
35
30
25
20
15
10
5
0
VHF (Low) VHF (High)
UHF
0 100 200 300 400 500 600 700 800 900 0 100 200 300 400 500 600 700 800 900
20
15
10
5
0
VHF (Low)
VHF (High)
UHF
fIF=45MHz
120
100
80
60
40
20
0
fUD=fD+12MHz
f
UD=fD–12MHz
(100kHz, 30% AM)
0 100 200 300 400 500 600 700 800 900
fIF=45MHz
400
300
200
100
0
–100
–200
–300
–400
0 100 200 300 400 500 600 700 800 900
VHF (Low)
VHF (High)
(V
CC=5V)
V
CC+5%
V
CC–5%
UHF
fIF
fBeat
+20
+10
0
–10
–20
–30
–40
–50
–60
–70
–80
–30 –20 –10 0 +10 +20
fLocal=129MHz
fP=83.25MHz
fC=86.83MHz, (fP–12dB)
fS=87.75MHz, (fP–1.7dB)
fIF=45.75MHz
fBeat=fIF±920kHz
Page 18
—18—
CXA3185/3186N
VHF (Low) 95MHz → VHF (High) 395MHz
UHF 413MHz → UHF 847MHz
Varicap voltage [V]
30
20
0
10
Varicap voltage [V]
30
20
0
10
T=70ms
–90,0000ms
10,0000ms
20.0ms/div
110,000ms
T=70ms
–90,0000ms
10,0000ms
20.0ms/div
110,000ms
5.0V/div
offset 10.0V
5.0V/div
offset 10.0V
Tuning Response Time
Page 19
—19—
CXA3185/3186N
IF output spectrum
IF output spectrum
RF input level : –40dBm
CENTER 45.0MHz
RES BW 1.0kHz
VBW 10Hz
SPAN 100.0kHz
SWP 30.0s
RF input level : –40dBm
RL=0dBm
10dB/div
VHF (High)
fRF=350MHz
fLO=395MHz
CENTER 45.0MHz
RES BW 1.0kHz
VBW 10Hz
SPAN 100.0kHz
SWP 30.0s
VHF (Low)
fRF=55MHz
fLO=100MHz
RL=0dBm
10dB/div
IF output [dBm]
IF output [dBm]
Page 20
—20—
CXA3185/3186N
IF output spectrum
RF input level : –40dBm
UHF (Low)
fRF=800MHz
fLO=845MHz
RL=0dBm
10dB/div
CENTER 45.0MHz
RES BW 1.0kHz
VBW 10Hz
SPAN 100.0kHz
SWP 30.0s
IF output [dBm]
Page 21
—21—
CXA3185/3186N
12 13
j100
j50
j25
0
50
–j25
–j50
–j100
350MHz
50MHz
1000p
S11
BYP
VHFin
14 15
j100
j50
j25
0
50
350MHz
–j100
800MHz
–j50
–j25
1000p
S11
UHFin1
UHFin2
VHF Input Impedance
UHF Input Impedance
Page 22
—22—
CXA3185/3186N
j50
j25
0
–j25
–j50
–j100
50
45MHz
j100
IF Output Impedance
Page 23
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER/PALLADIUM
42/COPPER ALLOY
30PIN SSOP (PLASTIC)
∗9.7 ± 0.1
∗5.6 ± 0.1
0.65
0.22 – 0.05
30
1 15
16
1.25
+ 0.2
– 0.1
7.6 ± 0.2
0.15
+ 0.05
– 0.02
0.1 ± 0.1
0.5 ± 0.2
0° to 10°
A
DETAIL A
SSOP-30P-L01
SSOP030-P-0056
0.1g
NOTE: Dimension “∗” does not include mold protrusion.
PLATING
0.10
0.13
M
+ 0.1
Package Outline Unit : mm
CXA3185/3186N
—23—
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
Loading...