Page 1
PLL IC for LCD Monitor/Projector
Description
The CXA3106Q is a PLL IC for LCD monitors/
projectors with built-in phase detector, charge pump,
VCO and counter.
The various internal settings are performed by
serial data via a 3-line bus.
Applicable LCD monitor/projector resolution are
VGA, SVGA and XGA, etc.
Features
• Supply voltage: 5V ± 10% single power supply
• Package: 48-pin QFP
• Power consumption: 335mW
• Sync input frequency: 10 to 100kHz
• Clock output signal frequency: 10 to 120MHz
• Clock delay: 1/16 to 20/16 CLK
• Sync delay: 1/16 to 20/16 CLK
• I/O level: TTL, PECL (complementary)
• Low clock jitter
• 1/2 clock output
CXA3106Q
48 pin QFP (Plastic)
Functions
• Phase detector enable
• UNLOCK output
• Output TTL disable function
• Power save function (2 steps)
Applications
• CRT displays
• LCD projectors
• LCD monitors
• Multi-media
Pin Configuration (Top View)
IOGND
PLLV
PLLGND
VCOV
VCOGND
VCOHGND
IRGND
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
IOVCC
CC
CC
IREF
RC2
RC1
IRVCC
37
38
39
40
41
42
43
44
45
46
47
48
CC
PECLV
36
1
CC
IOV
VBB
35
2
IOGND
DSYNCH
33
34
4
3
VCOH
CLKH
DSYNCL
32
31
6
5
VCO
VCOL
CLKL
30
7
HOLD
CLK/2L
CLK/2H
29
8
SYNCL
SYNCH
CC
PECLV
28
9
SYNC
IOGND
26
27
10
11
SENABLE
CC
TTLV
25
12
SCLK
TTLGND
23
20
19
18
17
16
15
14
13
SDATA
24
22
21
DSYNC
CLK
CLKN
CLK/2
CLK/2N
DGND
DV
CC
UNLOCK
DIVOUT
SEROUT
CS
TLOAD
– 1 –
E97447A7X-PS
Page 2
CXA3106Q
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage IOVCC, DVCC, TTLVCC, PECLVCC, PLLVCC,
VCOVCC, IRVCC, –0.5 to +7.0 V
IOGND, DGND, TTLGND, VCOHGND, PLLGND,
VCOGND, IRGND –0.5 to +0.5 V
• Input voltage VCOH, VCOL, SYNCH, SYNCL, VCO, HOLD,
SYNC, SENABLE, SCLK, SDATA, TLOAD, CS IOGND – 0.5 to IOVCC + 0.5 V
RC2 IRGND – 0.5 to IRVCC + 0.5 V
• Output current SEROUT, DIVOUT, UNLOCK, CLK/2N, CLK/2,
CLKN, CLK, DSYNC, CLK/2L, CLK/2H, CLKL,
CLKH, DSYNCH, DSYNCL, VBB –30 to +30 mA
IREF, RC1 –2 to +2 mA
• Storage temperature Tstg –65 to +150 °C
• Operating ambient temperature
Ta –25 to +75 °C
• Allowable power dissipation
PD 750 mW
Recommended Operating Conditions
Min. Typ. Max.
• Supply voltage IOVCC, DVCC, TTLVCC, PECLVCC,
PLLVCC, VCOVCC, IRVCC 4.75 5.00 5.25 V
IOGND, DGND, TTLGND, VCOHGND,
PLLGND, VCOGND, IRGND –0.05 0 0.05 V
• Digital input DIN (PECL) ∗1H level IOVCC – 1.1
DIN (PECL) ∗1L level IOVCC – 1.5 V
DIN (TTL) ∗2H level 2.0 V
DIN (TTL) ∗2L level 0.8 V
• SYNC, SYNCH, SYNCL input jitter 1.0 ns
• Operating temperature
Ta –20 +75 °C
∗1
VCOH, VCOL, SYNCH, SYNCL
∗2
VCO, HOLD, SYNC, SENABLE, SCLK, SDATA, TLOAD, CS
– 2 –
Page 3
DSYNC
(TTL)
DSYNC
(PECL)
CLK
(TTL)
NCLK
(TTL)
CLK
(PECL)
CLK/2
(TTL)
NCLK/2
(TTL)
CLK/2
(PECL)
UNLOCK
CXA3106Q
VBB
RC2RC1
1bit
on/off
1 to 4 CLK
TTLOUT
Polarity
Coarse
Delay
Latch
1bit
PECLOUT
on/off
1bit2bit
logic
1bit
TTLOUT
on/off
TTLOUT
PECLOUT
2bit
DIVMUXVCO
1bit5bit2bit
Fine
Delay
1/16 to 20/16 CLK
1/256 to 1/4096 CLK
1bit
TTLOUT
on/off
Programmable
Counter
1bit
on/off
12bit
TTLOUT
RSET
1/2
1bit
PECLOUT
on/off
unlock
detect
PECL
whole chip
power save
synthesizer
power save
TTLINTTLOUTCONTROL REGISTERDAC
1bit
on/off
CSTLOAD
1bit
DIVOUTSEROUT
Block Diagram
TTLIN
VCO
(TTL)
PECLIN
VCO
(PECL)
TTLIN
SYNC
(TTL)
Charge
Phase
Polarity
PECLIN
SYNC
(PECL)
Pump
Detector
1bit
– 3 –
1bit
TTLIN
HOLD
(TTL)
1bit
on/off
read out
TTLOUT
SDATASCLKSENABLE
IREF
Page 4
Pin No. Symbol Description Reference voltage level
1 IOVCC Digital power supply 5V
2 IOGND Digital GND 0V
3 VCOH External VCO input PECL
4 VCOL External inverted VCO input PECL
5 VCO External VCO input TTL
6 HOLD Phase detector disable signal input TTL
7 SYNCH Sync input PECL
8 SYNCL Inverted sync input PECL
9 SYNC Sync input TTL
10 SENABLE Control signal (enable) TTL
11 SCLK Control signal (clock) TTL
12 SDATA Control signal (data) TTL
13 TLOAD Programmable counter test input TTL
14 CS Chip select TTL
15 SEROUT Register read output TTL
16 DIVOUT Programmable counter test output TTL
17 UNLOCK Unlock signal output TTL
18 DVCC Digital power supply 5V
19 DGND Digital GND 0V
20 CLK/2N Inverted 1/2 clock output TTL
21 CLK/2 1/2 clock output TTL
22 CLKN Inverted clock output TTL
23 CLK Clock output TTL
24 DSYNC Delay sync signal output TTL
25 TTLGND TTL output GND 0V
26 TTLVCC TTL output power supply 5V
27 IOGND Digital GND 0V
28 PECLVCC PECL output power supply 5V
29 CLK/2L Inverted 1/2 clock output PECL
30 CLK/2H 1/2 clock output PECL
31 CLKL Inverted clock output PECL
32 CLKH Clock output PECL
33 DSYNCL Delay sync signal output PECL
34 DSYNCH Inverted delay sync signal output PECL
35 VBB PECL reference voltage PECLVCC – 1.3V
36 PECLVCC PECL output power supply 5V
37 IOGND Digital GND 0V
38 IOVCC Digital power supply 5V
39 PLLVCC PLL circuit analog power supply 5V
40 PLLGND PLL circuit analog GND 0V
41 VCOVCC VCO circuit analog power supply 5V
42 VCOGND VCO circuit analog GND 0V
43 VCOHGND VCO SUB analog GND 0V
44 IREF Charge pump current preparation 1.3V
45 RC2 External pin for LPF 2.0V to 4.4V
46 RC1 External pin for LPF 2.1V
47 IRGND IREF analog GND 0V
48 IRVCC IREF analog power supply 5V
CXA3106Q
– 4 –
Page 5
Pin Description and I/O Pin Equivalent Circuit
CXA3106Q
Pin
No.
18
19
25
26
27
28
36
1
2
Symbol I/O
IOVCC
IOGND
DVCC
DGND
TTLGND
TTLVCC
IOGND
PECLVCC
PECLVCC
Reference
voltage level
—
—
—
—
—
—
—
—
—
5V
0V
5V
0V
0V
5V
0V
5V
5V
Equivalent circuit Description
Digital power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
Digital GND.
Digital power supply.
Digital GND.
TTL output GND.
TTL output power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
Digital GND.
PECL output power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
PECL output power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
37
38
39
40
41
42
43
47
48
IOGND
IOVCC
PLLVCC
PLLGND
VCOVCC
VCOGND
VCOHGND
IRGND
IRVCC
—
—
—
—
—
—
—
—
—
0V
5V
5V
0V
5V
0V
0V
0V
5V
Digital GND.
Digital power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
PLL circuit analog power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
PLL circuit analog GND.
VCO circuit analog power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
VCO circuit analog GND.
VCO SUB analog GND.
IREF analog GND.
IREF analog power supply.
Ground this pin to the ground pattern
with a 0.1µF ceramic chip capacitor as
close to the pin as possible.
– 5 –
Page 6
CXA3106Q
Pin
No.
3
4
7
8
Symbol I/O
VCOH
VCOL
SYNCH
SYNCL
Reference
voltage level
PECL
I
PECL
I
PECL
I
PECL
I
IOV
CC
3
4
IOGND
Equivalent circuit Description
External VCO input.
Programmable counter test input
(switchable by a control register).
When using the VCO PECL input,
open the Pin 5 VCO TTL input.
External inverted VCO input.
When open, this pin goes to the PECL
threshold voltage (IOVcc – 1.3V).
Only the pin 3 VCOH input with VCOL
input open can be also operated but
rr
7
8
complementary input is recommended
in order to realize stable high-speed
operation.
Sync input.
When using the SYNCH PECL input,
open the Pin 9 SYNC TTL input.
The sync signal can be switched
between positive/negative polarity by
an internal register.
Inverted sync input.
When open, this pin goes to the PECL
threshold voltage (IOVcc – 1.3V).
Only the Pin 7 SYNCH input with
SYNCL input open can be also
operated but complementary
input is recommended in order to
realize stable high-speed operation.
– 6 –
Page 7
CXA3106Q
Pin
No.
10
5
6
9
Symbol I/O
VCO
HOLD
SYNC
SENABLE
Reference
voltage level
TTL
I
TTL
I
TTL
I
TTL
I
Equivalent circuit Description
External VCO input.
Programmable counter test input
(controlled by a control register).
When using the VCO TTL input, open
the Pin 3 VCOH and Pin 4 VCOL
PECL inputs.
Phase detector disable signal.
Active high. When this pin is high, the
phase detector output is held. This pin
goes to high level when open.
(See the HOLD Timing Chart.)
Sync input.
When using the SYNC TTL input,
open the Pin 7 SYNCH and Pin 8
SYNCL PECL inputs.
The sync signal can be switched
IOVCC
5
6
9
10
11
12
13
r/2
r
1.5V
2r
between positive/negative polarity by
a control register.
Control signal (enable) for setting the
internal registers.
When SENABLE is low, registers can
be written; when high, registers can be
read.
(See the Control Register Table and
Control Timing Chart.)
11
12
13
SCLK
SDATA
TLOAD
IOGND
Control signal (clock) for setting the
internal registers.
When SENABLE is low, SDATA is
loaded to the registers at the rising
TTL
I
edge of SCLK.
When SENABLE is high, the register
contents are output from SEROUT at
the falling edge of SCLK.
(See the Control Register Table and
Control Timing Chart.)
Control signal (data) for setting the
TTL
I
internal registers.
(See the Control Register Table and
Control Timing Chart.)
Programmable counter test input.
This pin is normally open status and
TTL
I
high. Register contents can be loaded
immediately to Programmable counter
by setting TLOAD low during the
programmable counter test mode.
– 7 –
Page 8
CXA3106Q
Pin
No.
14
15
16
20
21
22
Symbol I/O
CS
SEROUT
DIVOUT
CLK/2N
CLK/2
CLKN
Reference
voltage level
TTL
I
TTL
O
TTL
O
TTL
O
TTL
O
TTL
O
Equivalent circuit Description
IOVCC
Chip select.
When low, all circuits including the
register circuit are set to the power
14
save mode.
When high, all circuits are set to
operating mode.
IOGND
Register read output.
When SENABLE is high, the register
contents are output from SEROUT at
the falling edge of SCLK.
(See the Control Register Timing
Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
Programmable counter test output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
IOVCC
TTLV
CC
Inverted 1/2 clock output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
15
22
(high impedance) by a control register.
23
1/2 clock output.
24
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
IOGND
100k
16
20
21
TTLGND
Inverted clock output.
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
23
24
CLK
DSYNC
Clock output.
TTL
O
(See the I/O Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
Delay sync signal output.
(See the I/O Timing Chart.)
TTL
O
TTL output can be turned ON/OFF
(high impedance) and switched
between positive/negative polarity by
a control register.
– 8 –
Page 9
CXA3106Q
Pin
No.
17
29
30
Symbol I/O
UNLOCK
CLK/2L
CLK/2H
Reference
voltage level
TTL
O
PECL
O
PECL
O
IOGND
Equivalent circuit Description
Unlock signal output.
TTLVCC
This pin is an open collector output,
and pulls in the current when a phase
difference occurs. The UNLOCK
17
sensitivity can be adjusted by
connecting a capacitor and resistors
to this output as appropriate.
TTLGND
(See the UNLOCK Timing Chart.)
TTL output can be turned ON/OFF
(high impedance) by a control register.
Inverted 1/2 clock output.
(See the I/O Timing Chart.)
This pin requires an external pulldown resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
1/2 clock output.
(See the I/O Timing Chart.)
This pin requires an external pulldown resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
31
32
33
34
CLKL
CLKH
DSYNCL
DSYNCH
Inverted clock output.
(See the I/O Timing Chart.)
IOVCC
PECL
O
PECLV
CC
This pin requires an external pulldown resistor.
When not used, connect to PECLVCC
32
30
31
29
without connecting a pull-down
34
resistor.
33
Clock output.
(See the I/O Timing Chart.)
This pin requires an external pull-
PECL
O
IOGND
down resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
Delay sync signal output.
(See the I/O Timing Chart.)
This pin requires an external pull-
PECL
O
down resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
Inverted delay sync signal output.
(See the I/O Timing Chart.)
This pin requires an external pull-
PECL
O
down resistor.
When not used, connect to PECLVCC
without connecting a pull-down
resistor.
– 9 –
Page 10
CXA3106Q
Pin
No.
35
44
Symbol I/O
VBB
IREF
Reference
voltage level
PECLVCC
O
–1.3V
O
1.3V
IOGND
IRVCC
IRGND
IOGND
Equivalent circuit Description
PECLVCC
PECL reference voltage.
When used, ground this pin to the
35
ground pattern with a 0.1µF ceramic
chip capacitor as close to the pin as
possible.
Charge pump current preparation.
Connect to GND via an external
resistor (1.6kΩ).
Ground this pin to the ground pattern
44
with a 0.1µF ceramic chip capacitor
as close to the pin as possible.
45
46
RC2
RC1
External pin for LPF.
See the Recommended Operating
IRV
2.0V
O
to
CC
4.4V
IRGND
O
2.1V
100
VCOVCC
46
45
VCOGND
IOGND
Circuit for the external circuits. Note
that external resistors and capacitors
should be metal film resistors and
temperature compensation capacitors
which are relatively unaffected by
temperature change.
External pin for LPF.
See the Recommended Operating
Circuit for the external circuits.
– 10 –
Page 11
CXA3106Q
LSB
ADDR0
ADDR1
MSB
ADDR2
DATA0
DATA1
DATA2
1
0
0
8
7
6
DIV
VCO
DIV
VCO
DIV
VCO
Bit 0
Bit 1
Bit 2
12
11
10
0
1
0
DIV
VCO
DIV
VCO
DIV
VCO
Bit 8
Bit 9
Bit 10
19
18
17
1
1
0
26
25
24
0
0
1
FINE
DELAY
FINE
DELAY
FINE
DELAY
Bit 0
Bit 1
Bit 2
29
28
27
1
0
1
Bit 0
C.Pump
Bit 1
C.Pump
PD
POL
37
36
35
0
1
1
POL
SYNC
POL
DSYNC
CLK
Enable
41
40
39
1
1
1
VCO
By-pass
Synth
power
power
Read out
DATA3
DATA ADDRESS
DATA4
DATA5
DAT6
MSB1VCO
DATA7
Register Name
5
VCO
4
VCO
3
VCO
2
VCO
DIV
DIV
DIV
DIV
DIV
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
9
DIVREG1
register read no
register read no
DIV
VCO
Bit 11
DIVREG2
16
15
14
Bit 0
23
22
21
DIV 1, 2, 4
13
Bit 1
20
DIV 1, 2, 4
CENFREREG
register read no
register read no
Bit 3
FINE
DELAY
Bit 4
FINE
DELAY
Bit 0
DELAY
COARSE
Bit 1
DELAY
COARSE
DELAYREG
34
33
32
31
30
CPREG
register read no
register read no
38
NCLK
Enable
CLK/2
Enable
Enable
NCLK/2
Enable
DSYNC
Enable
UNLOCK
TTLPOLREG
register read no
Enable
DIVOUT
TESTPOWREG
Register No.
Register 1
Control Register Table
Register 2
Register 3
– 11 –
Register 4
Register 5
Register 6
Register 7
Page 12
CXA3106Q
Electrical Characteristics (Ta = 25°C, VCC = 5V, GND = 0V)
Item Symbol Conditions Min. Typ. Max. Unit
Current consumption (excluding output current)
Current consumption 1
Current consumption 2
Current consumption 3
Digital input
Digital high level input
voltage (PECL)
Digital low level input
voltage (PECL)
VCOL, SYNCL input open
voltage (PECL)
Digital high level input
current (PECL)
Digital low level input
current (PECL)
Digital high level input
voltage (TTL)
Digital low level input
voltage (TTL)
Digital high level input
current (TTL)
ICC1
ICC2
ICC3
VIH1
VIL1
VIO
IIH1
IIL1
VIH2
VIL2
IIH2
CS = H, Synth Power = 1
CS = H, Synth Power = 0
CS = L
VIH = IOVCC – 0.8V
VIL = IOVCC – 1.6V
VIH = 2.7V
40
5
3
IOVCC
–1.15
–100
–200
2.0
–200
67
15
10
IOVCC
–1.3
100
30
20
IOVCC
–1.5
100
0
0.8
–20
mA
mA
mA
V
V
V
µA
µA
V
V
µA
Digital low level input
current (TTL)
HOLD characteristics
RC1 input pin leak current
HOLD signal set-up time
HOLD signal hold time
Digital output
Digital high level output
voltage (PECL)
Digital low level output
voltage (PECL)
PECL output reference
voltage
Digital high level output
voltage (TTL)
Digital low level output
voltage (TTL)
IIL2
Ileak
Ths
Thh
VOH1
VOL1
VBB
VOH2
VOL2
VIL = 0.5V
RL = 330Ω
RL = 330Ω
RL = 330Ω
CL = 10pF
CL = 10pF
–500
20
20
PECLVCC
–1.1
2.7
PECLVCC
–1.3
–100
1.00
PECLVCC
–1.6
0.5
µA
nA
ns
ns
V
V
V
V
– 12 –
Page 13
Item Symbol Conditions Min. Typ. Max. Unit
UNLOCK output
CXA3106Q
UNLOCK output current
SYNC input
SYNC input frequency range
DSYNC output
DSYNC output variable
coarse delay time setting
resolution
DSYNC output variable
coarse delay time
DSYNC output variable
fine delay time setting
resolution
DSYNC output variable
fine delay time
VCO characteristics
DIV output frequency
operation range 1
DIV output frequency
operation range 2
Iunlock
Fin
Rdsync1
Td1
Rdsync2
Td2
FVCO1
FVCO2
DIV = 1/1
DIV = 1/2
–30
10
1
1/16
40
20
mA
100
2
4
5
20/16
120
60
kHz
bit
CLK
bit
CLK
MHz
MHz
DIV output frequency
operation range 3
VCO lock range
VCO gain 1
VCO gain 2
VCO gain 3
Charge pump current 1
Charge pump current 2
Charge pump current 3
VCO counter bits
FVCO3
Vlock
KVCO1
KVCO2
KVCO3
Kpd1
Kpd2
Kpd3
Rdiv2
DIV = 1/4
DIV = 1/1
DIV = 1/2
DIV = 1/4
C.Pump Bit = 00,
IREF = 1.6kΩ
C.Pump Bit = 10,
IREF = 1.6kΩ
C.Pump Bit = 11,
IREF = 1.6kΩ
10
2.0
200
100
50
80
350
1350
320
160
80
100
400
1600
12
30
4.4
550
270
135
130
500
1800
MHz
V
Mrad/sv
Mrad/sv
Mrad/sv
µA
µA
µA
bit
– 13 –
Page 14
Item Symbol Conditions Min. Typ. Max. Unit
CLK (CLK, CLK/2) output
CXA3106Q
CLK output (PECL)
frequency range 1
CLK output (PECL)
frequency range 2
CLK output (PECL)
frequency range 3
CLK, CLK/2 output (PECL)
rise time
CLK, CLK/2 output (PECL)
fall time
CLK output (TTL)
frequency range 1
CLK output (TTL)
frequency range 2
CLK output (TTL)
frequency range 3
CLK, CLK/2 output (TTL)
rise time
CLK, CLK/2 output (TTL)
fall time
Fclk1PECL
Fclk2PECL
Fclk3PECL
TrPECL
TfPECL
Fclk1TTL
Fclk2TTL
Fclk3TTL
TrTTL
TfTTL
DIV = 1/1
DIV = 1/2
DIV = 1/4
10% to 90%,
RL = 330Ω
10% to 90%,
RL = 330Ω
DIV = 1/1
DIV = 1/2
DIV = 1/4
10% to 90%,
CL = 10pF
10% to 90%,
CL = 10pF
40
20
10
1.0
1.0
40
20
10
2.0
2.0
1.5
1.5
3.0
3.0
120
60
30
2.0
2.0
80
60
30
4.0
4.0
MHz
MHz
MHz
ns
ns
MHz
MHz
MHz
ns
ns
CLK output (PECL, TTL)
duty
SYNC input (PECL) and
CLK output (PECL) delay
offset
CLK output (PECL) and
DSYNC output (PECL)
phase difference
CLK output (PECL) and
CLK/2 output (PECL)
phase difference
CLK output (PECL) and
DIVOUT output (TTL) rise
phase difference
CLK output (PECL) and
DIVOUT output (TTL) fall
phase difference
DSYNC, CLK, CLK/2 PECL
output and TTL output
phase difference
Dclk2
Td3
Td4
Td5
Td6
Td7
Td8
CL = 10pF
CL = 10pF
CL = 10pF
CL = 10pF
CL = 10pF
CL = 10pF
CL = 10pF
40
1.5
0.0
1.5
50
1
2.4
0.8
14
11
3.0
60
3.0
1.0
4.5
%
ns
ns
ns
ns
ns
ns
– 14 –
Page 15
Item Symbol Conditions Min. Typ. Max. Unit
CLK (CLK, CLK/2) output
CLK vs. SYNC output jitter
(NTSC)
CLK vs. SYNC output jitter
(VGA)
CLK vs. SYNC output jitter
(SVGA)
Tj1p-p
Tj2p-p
Tj3p-p
triggered at SYNC
Fsync = 15.73kHz
(Crystal)
Fclk = 12.27MHz
N = 780
Fine Delay =
2/16 to 20/16
triggered at SYNC
Fsync = 31.47kHz
(Crystal)
Fclk = 25.18MHz
N = 800
triggered at SYNC
Fsync = 48.08kHz
(Crystal)
Fclk = 50.00MHz
N = 1040
4.0
3.0
2.0
7.0
5.0
3.0
CXA3106Q
ns
ns
ns
CLK vs. SYNC output jitter
(XGA)
CLK vs. DSYNC output jitter
Control registers
SCLK frequency
SENABLE setup time
SENABLE hold time
SDATA setup time
SDATA hold time
SENABLE setup time
SENABLE hold time
Tj4p-p
Tj5p-p
SCLK
TENS
TENH
TDS
TDH
TNENS
TNENH
triggered at SYNC
Fsync = 56.48kHz
(Crystal)
Fclk = 75.00MHz
N = 1328
triggered at DSYNC
in write/read mode
in write mode
in write mode
in write mode
in read mode
in read mode
in read mode
1.6
3
0
3
0
3
0
2.5
0.1
12
ns
ns
MHz
ns
ns
ns
ns
ns
ns
– 15 –
Page 16
CXA3106Q
Description of Block Diagram
Sync Input
Sync signals in the range of 10 to 100kHz can be input. Input supports both positive and negative polarity.
PECL input can also be a single input.
When SYNC is positive polarity, the clock is regenerated in synchronization with the rising edge of the sync signal.
When SYNC is negative polarity, the clock is regenerated in synchronization with the falling edge of the sync signal.
VCO oscillation stops when there is no sync input.
Register: SYNC POL
SYNC input polarity
1
Positive
0
Negative
Phase Detector
The phase detector operates at the sync input frequency of 10 to 100kHz. The PD input polarity should be
set to the default PD POL = 1. Phase comparison is performed at the edges.
The input circuit of the phase detector does not contain a hysteresis circuit, so the waveform must be shaped
at the front end of the CXA3106Q when inputting a noisy signal.
The phase detector HOLD signal is supplied by TTL. (See the HOLD Timing Chart.)
The PLL UNLOCK signal is output by an open collector.
(See the UNLOCK Timing Chart.)
Charge Pump
The gain (I, I/4, I/16) can be varied by changing the charge pump current using 2 bits of control register.
Register: C.Pump bit 1
Register: C.Pump bit 0
Charge pump current
0
0
100µA
1
0
1
1
400µA 1600µA
LPF
This is a loop filter comprised of the external capacitors and resistor.
Be sure to use metal film resistors with little temperature variation and a temperature-compensated capacitor.
In particular, the 0.33µF capacitor should be equivalent to Murata's high dielectric constant series capacitor
type B or better. (electrostatic capacitance change ratio ±10%: T = –25 to +85°C)
VCO
The VCO oscillator frequency covers from 40 to 120MHz.
VCO Rear-end Counter
The VCO output is frequency divided to 1/1, 1/2 or 1/4 by switching 2 bits of control register.
The operating range can be expanded to 10 to 120MHz by combining the counter with a VCO frequency divider.
Register: DIV 1, 2, 4 bit 1
Register: DIV 1, 2, 4 bit 0
Counter frequency divisions
0
0
1/1
1
0
1
1
1/2 1/4
– 16 –
Page 17
CXA3106Q
Feedback Programmable Counter
This counter can be set as desired from 256 to 4096 using 12 bits.
Frequency divisions = (m + 1) × 8 + n, n: 3 bits (VCO DIV bits 0 to 2), m: 9 bits (VCO DIV bits 3 to 11)
When the register value is changed, the new setting is actually loaded to the counter when the counter value
becomes "all 0".
Clock Output
When SYNC input is positive polarity, the clock is regenerated in synchronization with the rising edge of the
sync signal.
The clock output delay time can be changed in the range of 1/16 to 20/16 CLK using 5 bits of control register.
(See the I/O Timing Chart.)
Output is TTL and PECL (complementary), and supports both positive and negative polarity. Clock TTL
output can also be turned off independently.
Register: Clock Enable
Clock output status
1
ON
0
OFF
1/2 Clock Output
Reset is performed at the delay sync timing and the clock output is frequency divided by 1/2. (See the I/O
Timing Chart.)
Both odd and even output are TTL and PECL output. TTL output can also be turned off independently.
Register: Clock Enable
Clock output status
1
ON
0
OFF
Delay Sync Output
The front edge of the delay sync pulse is latched by the pulse obtained by frequency dividing the CLK
regenerated by the PLL, so there is almost no jitter with respect to CLK. This front edge can be used as the
reset signal for the system timing circuit.
The rear edge of the delay sync pulse is latched by the CLK regenerated by the PLL. This relationship is
undefined for one clock as shown in the Timing Chart.
The delay sync output delay time can be varied in two stages. First, the delay time can be varied in the range
of 1/16 to 20/16 CLK using 5 bits of control register, and then in the range of 1 to 4 CLK using 2 bits of
control register. In other words, the total delay time is ((1/16 to 20/16) + (1 to 4)) CLK. (See the I/O Timing
Chart.)
DSYNC output is TTL and PECL (complementary), and supports both positive and negative polarity. Clock
TTL output can also be turned off.
Register: Clock Enable
Clock output status
Lower delay line
FINE DELAY bits 0 to 4
Delay time
Upper delay line
COARSE DELAY bits 0 to 1
Delay time
Register: DSYNC POL
DSYNC output polarity
1
ON
00000
1/16CLK
00
1CLK
1
Positive
0
OFF
00001
2/16CLK
01
2CLK
0
Negative
· · · · · · · · · · · ·
· · · · · · · · · · · ·
10
3CLK
– 17 –
10011
20/16CLK
11
4CLK
Page 18
Control Circuit (3-bit address, 8-bit data)
The timing and input methods are described hereafter.
Feedback programmable counter control REGISTER1, 2 12bit
VCO rear-end counter control REGISTER3 2bit
Fine delay line control REGISTER4 5bit
Coarse delay line control REGISTER4 2bit
Charge pump current DAC control REGISTER5 2bit
Phase detector input positive/negative polarity control REGISTER5 1bit
Sync input positive/negative polarity control REGISTER6 1bit
Delay sync output positive/negative polarity control REGISTER6 1bit
Clock TTL output OFF function REGISTER6 1bit
Inverted clock TTL output OFF function REGISTER6 1bit
1/2 clock TTL output OFF function REGISTER6 1bit
Inverted 1/2 clock TTL output OFF function REGISTER6 1bit
Delay sync TTL output OFF function REGISTER6 1bit
UNLOCK output OFF function REGISTER6 1bit
Programmable counter input switching REGISTER7 1bit
Power save with register contents held REGISTER7 1bit
Register read function power ON/OFF REGISTER7 1bit
Programmable counter TTL output OFF function REGISTER7 1bit
CXA3106Q
Power Save
The CXA3106Q realizes 2-step power saving (all OFF, control registers only ON). This is controlled by a
control register and the chip selector.
Step 1: Chip selector control
CS
Power save status
H
Power ON
L
All OFF
Step 2: Control register control
Register: Synth power
Power save status
1
Power ON
Control registers only ON
0
Readout Circuit (during test mode)
The control register contents can be read by serial data from SEROUT.
(See the Control Register Timing Chart.)
Register: Read out power
Readout status
0
Function OFF
1
Function ON
– 18 –
Page 19
Programmable Counter Output (during test mode)
The programmable counter output is TTL output from the DIVOUT pin.
(See the I/O Timing Chart.)
This output is normally not used.
CXA3106Q
Register: DIVOUT Enable
DIVOUT output status
0
OFF
1
ON
TLOAD input (during test mode)
This control signal forcibly loads the control register contents to the programmable counter.
This signal is normally not used.
TLOAD
Forced load control status
H
Function OFF
L
Function ON
VCO input (during test mode)
This is the programmable counter test signal input pin.
This pin can be switched internally by the MUX circuit.
TTL and PECL input are possible.
This pin is normally not used.
Register: VCO By-pass
Input status
1
Internal VCO
0
External input
– 19 –
Page 20
CXA3106Q
Control Register Timing
1) Write mode
Many CXA3106Q functions can be controlled via a program. Characteristics are changed by setting the
internal control register values via a serial interface comprised of three pins: SENABLE (Pin 10), SCLK (Pin
11) and SDATA (Pin 12). The write timing diagram is shown below.
Input the 8-bit data and 3-bit register address MSB first to the SDATA pin. Some registers are not 8 bits, but
the data is input aligned with the LSB side in these cases. (See the Register Table.)
SENABLE is the enable signal and is active low. SCLK is the transfer clock signal, and data is loaded to the
IC at the rising edge. When SENABLE rises, SCLK must be high. (Registers are set at the rising edge of
SENABLE.) When SENABLE falls, SCLK may be either high or low.
SENABLE
SDATA
8bit
DATA
3bit
ADDRESS
SCLK
Enlarged
TENS TENH
SENABLE
SDATA
SCLK
TDHTDS
Enlarged
For example, when inputting a 16-bit signal, the initial 5 bits are invalid and the latter 11 bits are valid. This is
to say that the latter 11 bits are loaded to the register.
SENABLE
SDATA
5bit
Invalid DATA
8bit
DATA
3bit
address
SCLK
– 20 –
Page 21
CXA3106Q
The settings of the frequency divider (2 bits, DIV1, 2, 4) and programmable counter (12 bits, VCODIV) at the
rear end of the VCO are transferred in the order shown below. (The data will be set when the three registers
are transferred.)
First DIVREG2, CENFREREG and DIVREG1 are set, and then the data is transferred independently at the
timings shown below.
DIVREG2 (upper 4 bits of VCODIV)
↓
CENFREREG (2 bits of DIV1, 2, 4)
↓
DIVREG1 (lower 8 bits of VCODIV)
All three of the above registers must be changed even when changing only (2 bits of DIV1, 2, 4). This is the
same when changing only (12 bits of VCODIV).
SENABLE
SDATA
SCLK
DIVREG2
CENFREREG DIVREG1
– 21 –
Page 22
CXA3106Q
2) Read mode
Data can be transferred from the shift register to the data register only when SENABLE is high.
Binary data can be read from the data register by inputting SCLK when SENABLE is high. Data is loaded
from the data register to the SCAN PATH circuit each time one clock is input to SCLK, and is output
sequentially from the register read no. 1 data (VCODIV bit 7) through the SEROUT pin. When the 41st SCLK
clock pulse is input, the register read no. 41 data (VCO By-pass) is output. Then, when the 42nd clock pulse
is input to SCLK, the output returns to the register read no. 1 data (VCODIV bit 7) and the data output is
repeated. Also, the data output from the SCAN PATH circuit is automatically reloaded even when the shift
register data is changed during data output.
Note) Since all registers do not have 8 bits, only the valid bits of each register are loaded to the SCAN PATH
circuit. (See the Control Register Table for the actual register read no.)
SCLK
SENABLE
CLK
I/P SHIFT REGISTER, 11 BITS
NEN
TR
EN
CLK
8 BIT DATA 3 BIT ADDRESS
7 DATA REGISTERS (41 LATCHES).
REGISTERS ARE DIFFERENT LENGTHS
UP TO 8 BIT
SCAN PATH, 1 ELEMENT PER REGISTER BIT
Block Diagram during Read Mode
TNENS TNENH
SEROUT
SENA
SEROUT
SCLK
READ NO. 1 READ NO. 2 READ NO. N
1 2
N
Timing Chart during Read Mode
– 22 –
Page 23
CXA3106Q
0 1 2 3 4CLK
1CLK
Td7
(typ. 11ns)
Td6
(typ. 14ns)
Td4
Td1
(1 to 4) CLK
(typ. 2.4ns)
Td5
(typ. 0.8ns)
1CLK
Timing Charts
1. I/O timing
Td3
(typ. 1ns)
SYNC input
(positive polarity)
(PECL)
CLK output
(PECL)
Td2 8CLK
1/16CLK to 20/16CLK
DIVOUT output
(TTL)
– 23 –
DSYNC output
(positive polarity)
(PECL)
RESET
(internal signal)
CLK/2 output
(PECL)
Page 24
2. HOLD timing
SYNC input
(SYNC POL = 1)
SYNC input
(SYNC POL = 0)
DIVOUT output
(TTL)
CXA3106Q
Thh Ths Thh Ths
HOLD input
(TTL)
The phase comparison output is held and fixed VCO output frequency is output.
CLK output
T
hold
HOLD signal set-up time (Ths) is a time from the rising edge of HOLD signal to the falling edge of DIVOUT.
Or, when SYNC POL = 1, it is a time from the falling edge of HOLD signal to the rising edge of SYNC; when
SYNC POL = 0, it is the time from the falling edge of HOLD signal to the falling edge of SYNC.
HOLD signal hold time (Thh) is the time from the falling edge of DIVOUT to falling edge of HOLD signal. Or,
when SYNC POL = 1, it is the time from the rising edge of SYNC to the rising edge of HOLD signal; when
SYNC POL = 0, it is the time from the falling edge of SYNC to the rising edge of HOLD signal.
When the HOLD input is held, the CLK frequency fluctuation can be calculated as follows.
∆V
Ileak
–Q+Q
C
VCO
∆f
I
SW
SW
I
C · ∆V = Q = Ileak · Thold
C: Loop filter capacitance
∆V: Voltage variation due to leak current
Ileak: Internal amplifier leak current
Thold: Hold time
∆V = Ileak · Thold/C
∆f = ∆V · KVCO = Ileak · Thold/C · KVCO
For example, assuming f = 100MHz, Ileak = 1nA, Thold = 1ms, C = 0.33µF, and KVCO = 2π · 50MHz/V, then:
∆V = 1 × 10–9· 1 × 10–3/(0.33 × 10–6) = 3 × 10–6[V]
∆f = 1 × 10–9· 1 × 10–3/(0.33 × 10–6) · 50 × 106= 151 [Hz]
– 24 –
Page 25
CXA3106Q
3. UNLOCK timing
Outside the ICInside the IC
CC
V
I2
Signal from phase
comparator
unlock
detect
S1
R1
I1
S2
R2
UNLOCK
C
The unlock detect output is an open collector. When unlock detect output S1 goes high, the current I1 is pulled in.
The UNLOCK sensitivity can be adjusted by connecting external resistors (R1, R2) and a capacitor (C) to this output
pin as appropriate and changing these values. Operation during three modes is described below.
CASE 1: When there is no phase difference, that is to say, when the PLL is locked.
The S1 signal is low and the S2 signal is high.
The UNLOCK output remains low.
S1
S2
threshold
UNLOCK
level
CASE 2: When there is a phase difference, that is to say, when the S1 signal goes high and low as shown in
the figure below, the fall slew rate of the S2 signal is determined by the current I1 flowing into that
open collector. Therefore, increasing the resistance R1 causes the S2 signal fall slew rate to
become slower. Also, since the S2 signal rise slew rate is determined by the current I2, reducing
the resistance R2 causes the S2 signal rise slew rate to become faster. If this integrated S2 signal
does not fall below the threshold level of the next inverter, the UNLOCK signal stays low, and the
PLL is said to be locked.
S1
S2
threshold
level
UNLOCK
CASE 3: However, even if a phase difference exists as shown above, if the resistance R1 is reduced, the
current I1 flowing into the open collector increases, and the S2 signal fall slew rate becomes faster.
Also, if the resistance R2 is increased, the S2 signal rise slew rate becomes slower. If this
integrated S2 signal falls below the threshold level of the next inverter, the UNLOCK signal goes
from low to high, and the PLL is said to be unlocked.
S1
S2
UNLOCK
threshold
level
– 25 –
Page 26
Charge Pump and Loop Filter Settings
The CXA3106Q's charge pump is a constant-current output type as shown below.
CXA3106Q
CC
V
When a constant-current output charge pump circuit is used inside the
PLL, the phase detector output acts as a current source, and the
dimension of its transmittance KPD is A/rad. Also, when considering the
S1
To LPF
S2
VCO input as a voltage, the LPF transmittance dimension must be
expressed in ohms (Ω = V/A).
Therefore, the PLL transmittance when a constant-current output charge
pump circuit is used is as follows.
LPF VCO
F (S)
(Ω)
ωr
1/S
θr
+
–
θo
N
1/S 1/N
(A/rad)
ω0/N
PD
KPD
counter
The PLL closed loop transmittance is obtained by the following formula.
KVCO
(rad/S/V)
ω0/N
θo/N
θr
KPD · F (S) · KVCO · 1/N · 1/S
=
1 + KPD · F (S) · KVCO · 1/N · 1/S
... (1)
Here, KPD, F (S), and KVCO are:
KPD: Phase comparator gain (A/rad)
F (S): Loop filter transmittance (Ω)
KVCO: VCO gain (rad/s/V)
∗1
The reason for the 1/S inside the phase detector is as follows.
θo (t)/N =
t
∫
o ω0 (t)/Ndt + θo (t = 0)/N ... (a)
θo (t = 0) = 0
θo (t)/N =
t
∫
o ω0 (t)/Ndt ... (b)
Performing Laplace conversion:
θo (S)/N = W0 (S)/N ... (c)
1
S
– 26 –
Page 27
CXA3106Q
The loop filter F (S) is described below.
The loop filter smoothes the output pulse from the phase comparator and inputs it as the DC component to the
VCO. In addition to this, however, the loop filter also plays an important element in determining the PLL
response characteristics.
Typical examples of loop filters include lag filters, lag-lead filters, active filters, etc. However, the CXA3106Q's
LPF is a current input type active filter as shown below, so the following calculations show an actual example
of deriving the PLL closed loop transmittance when using this type of filter and then using this transmittance to
create a formula for setting the filter constants.
Current input type active filter
CR
i
i
–A
–1
–Vo
Vo
The filter transmittance is as follows.
VO
+ VO = (R + )
A
F (S) = ·
1 + SRC
SC
1 + Sτ
= ·
SC
1
SC
A
1 + A
A
1 + A
The Bode diagram for formula (2) is as follows.
log scale
1
gain [dB]
τ
∴τ = RC
0
Here, assuming A > 1, then:
F (S) =
1 + Sτ
SC
...........................
(2)
phase [deg]
–90
Next, substituting (2) into (1) and obtaining the overall closed loop transmittance for the PLL:
θo/N
θr
KPD · KVCO · τ
NC
=
KPD · KVCO · τ
NC
· S +
· S +S2+
KPD · KVCO
NC
KPD · KVCO
NC
...
(3)
log w
log w
–45deg
2ζωnS + ωn
=
S2+ 2ζωnS + ωn
ωn =
KPD · KVCO
√
ζ = ωnτ
NC
1
2
.................................................................
2
............................................
2
......................................................
– 27 –
(4)
(5)
(6)
Page 28
CXA3106Q
Here, ωn and ζ are as follows.
ωn characteristic angular frequency:
The oscillatory angular frequency when PLL oscillation is assumed to have been maintained by the loop filter
and individual loop gains is called the characteristic angular frequency: ωn.
ζ damping factor:
This is the PLL transient response characteristic, and serves as a measure of the PLL stability. It is
determined by the loop gain and the loop filter.
A capacitor C2 is added to the actual loop filter.
This added capacitor C2 is used to reduce the R noise, and a value of about 1/10 to 1/1000 of C1 should be
selected as necessary.
Current input type active filter with added capacitor C2
C2
C1 R
i
i
–A
–1
–Vo
The filter transmittance is as follows.
F (S) =
S ((C1 + C2) + C1 · C2 · R · S)
=
S (C1 + C2) (1 + τ2 · S)
1 + C1 · R · S
1 + τ1 · S
τ1 = C1 · R
C1 · C2 · R
τ2 =
C1 + C2
Here, assuming C2 = C1/100, then:
C1 · C1/100 · R
τ2 =
C1 + C1/100
Vo
..................
(7)
The Bode diagram for formula (7) is as follows.
log scale
1
1
τ1
gain [dB]
log w
log w
0
–45deg
phase [deg]
–90
τ2
1
= C1 · R
101
1
= τ1
101
– 28 –
Page 29
Next, the various parameters inside an actual CXA3106Q are obtained.
The CXA3106Q's charge pump output block and the LPF circuit are as follows.
C2
C1R1
100µA
or 400µA
or 1600µA
46
CC
V
S1
45
CXA3106Q
100k
To VCO
CXA3106Q
100µA
or 400µA
or 1600µA
S2
10020k
First, KPD is as follows.
KPD = 100µ/2π or 400µ/2π or 1600µ/2 π (A/rad)
Typical KVCO characteristics curves for the CXA3106Q's internal VCO are as follows.
120
80
40
VCO frequency [MHz]
VCO DIV = 1/1
VCO DIV = 1/2
VCO DIV = 1/4
234
VCO input voltage [V]
Therefore, KVCO is as follows.
KVCO = 2π · 50M or 2π · 25M or 2π · 12.5M (rad/s/V)
– 29 –
Page 30
ωn and ζ calculated for various types of computer signals are shown below.
Here, the various parameters are as follows.
FSYNC: Input H sync frequency
FCLK: Output clock frequency
KPD∗2π: Phase comparator gain ∗2π (KPD*2π = +100 or 400 or 1600)
KVCO/2π: VCO gain (when VCO DIV = 1/1, KVCO/2π = 50)
(when VCO DIV = 1/2, KVCO/2π = 50/2)
(when VCO DIV = 1/4, KVCO/2π = 50/4)
N: Counter value
C1: Loop filter capacitance value
R1: Loop filter resistance value
CXA3106Q
NTSC
NTSC
NTSC
PAL
PAL
PAL
PC-98
VGA
MAC
VESA
SVGA
SVGA
SVGA
SVGA
Resolution
640 × 480
640 × 480
640 × 480
640 × 480
800 × 600
800 × 600
800 × 600
800 × 600
FSYNC
kHz
15.734
15.734
15.734
15.625
15.625
15.625
24.82
31.47
35.00
37.86
35.16
37.88
46.88
48.08
FCLK
MHz
12.27
18.41
24.55
14.69
22.03
29.38
21.05
25.18
30.24
31.50
36.00
40.00
49.50
50.00
KPD
∗
2π
µA
400
400
400
400
400
400
100
100
400
400
400
400
400
400
C.Pump
setting
Bit1
Bit0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KVCO/2π
M/(S∗V)
50/4
50/4
50/2
50/4
50/4
50/2
50/2
50/2
50/2
50/2
50/2
50/2
50/2
50/2
DIV1.2.4
setting
Bit1
Bit0
1
1
1
1
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
N
setting
780
1170
1560
940
1410
1880
848
800
864
832
1024
1056
1056
1040
C1
µF
0.33
0.33
0.33
0.33
0.33
0.33
0.33
0.33
0.33
0.33
0.33
0.33
0.33
0.33
R1
Ω
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
3300
ωn
kHzrad
4.41
3.60
4.41
4.01
3.28
4.01
2.99
3.08
5.92
6.04
5.44
5.36
5.36
5.40
fn
kHz
0.70
0.57
0.70
0.64
0.52
0.64
0.48
0.49
0.94
0.96
0.87
0.85
0.85
0.86
ζ
2.40
1.96
2.40
2.19
1.78
2.19
1.63
1.68
3.22
3.29
2.96
2.92
2.92
2.94
SVGA
MAC
XGA
XGA
XGA
MAC
XGA
800 × 600
832 × 624
1024 × 768
1024 × 768
1024 × 768
1024 × 768
1024 × 768
53.67
49.72
48.36
56.48
60.02
60.24
68.68
56.25
57.28
65.00
75.00
78.75
80.00
94.50
400
400
400
400
400
400
400
1
0
1
0
1
0
1
0
1
0
1
0
1
0
50/2
50/2
50/1
50/1
50/1
50/1
50/1
1
1
0
0
0
0
0
1048
0
1152
0
1344
0
1328
0
1312
0
1328
0
1376
0
0.33
0.33
0.33
0.33
0.33
0.33
0.33
3300
3300
3300
3300
3300
3300
3300
5.38
5.13
6.72
6.76
6.80
6.76
6.64
0.86
0.82
1.07
1.08
1.08
1.08
1.06
2.93
2.79
3.66
3.68
3.70
3.68
3.61
– 30 –
Page 31
CXA3106Q
CLK Jitter Evaluation Method
The regenerated CLK is obtained by applying Hsync to the CXA3106Q. Apply this CLK to a digital
oscilloscope and observe the CLK waveform using Hsync as the trigger.
Pulse
Generator
Computer signal
Hsync
CLK
H
Sync
Trigger
Back
Porch
triger
CXA3106Q
CLKHsync
15 to 25% of Tsync
EnlargedEnlarged Enlarged Enlarged
ch1
Active
Video
Tsync = 1/fsync
Digital
Oscilloscope
Front
Porch
CLK
Tjp-p
The CLK jitter is measured at peak to peak in the long-term write mode of the digital oscilloscope as shown in
the figure. The CLK jitter size varies according to the difference in the relative position with respect to Hsync.
Therefore, when the observation point is changed, the CLK jitter at that point is observed.
The figure below shows an typical example of the CLK jitter for the CXA3106Q.
The CLK jitter increases slightly at the rising edge of Hsync (in the case of positive polarity), and then settles
down thereafter. However, this is not a problem as the active pixels start after about 20% of the H cycle has
passed from the rising edge of Hsync.
Jitter amount [Tjp-p]
0 1/4 · Tsync 2/4 · Tsync 3/4 · Tsync Tsync
Observation points
– 31 –
Page 32
Example of Representative Characteristics
CXA3106Q
KVCO characteristics
200
150
DIV = 1/1
100
DIV = 1/2
50
CLKIH Output Frequency [MHz]
0
2.0 4.52.5 3.0 3.5 4.0
DIV = 1/4
Vrc2 Control Voltage [V]
Coarse Delay Td1 vs. Coarse Delay Bit
5
Ta = –25°C
Ta = +25°C
4
Ta = +75°C
KVCO characteristics
200
Ta = –25°C
Ta = +25°C
Ta = +75°C
150
100
Output Frequency [MHz]
50
0
2.0 4.52.5 3.0 3.5 4.0
Vrc2 Control Voltage [V]
Fine Delay Td2 vs. Fine Delay Bit
25
Ta = –25°C
Ta = +25°C
20
Ta = +75°C
3
Coarse Delay Td1 [CLK]
2
1
0312
Coarse Delay Bit
Jitter peak-peak [ns]
15
10
Fine Delay Td2 [1/16 CLK]
Jitter peak-peak vs. Output Frequency
3.5
VGA, N = 800, DIV = 1/2, CP = 10
SVGA, N = 1056, DIV = 1/2, CP = 10
3.0
2.5
2.0
1.5
XGA, N = 1344, DIV = 1/1, CP = 10
VGA
SVGA
5
0
02051015
Fine Delay Bit
XGA
1.0
30 50 70 80
20 9040 60
Output Frequency [MHz]
– 32 –
Page 33
CXA3106Q
Notes on Operation
• Be sure not to separate the analog and digital power supplies, and the analog and digital GND.
• The ground pattern should be as wide as possible. Using a multi-layer substrate with a mat ground is
recommended.
• Ground the power supply pins of the IC with a 0.1µF or larger ceramic chip capacitor as close to each pin as
possible.
• Be sure to accurately match the I/O characteristic impedance in order to ensure sufficient performance during
high-speed operation.
• Design the set so that the loop filter (external) is located at the minimum distance. (See the CXA3106Q
PWB.)
– 33 –
Page 34
CXA3106Q
(1) Recommended PECL I/O circuit
The peripheral circuits mainly use PECL for digital input and output. Of course, PECL and TTL can also be
mixed. In this case, disable the TTL outputs with the control registers.
PECL level output pins
330Ω
GND
1200pF
Loop Filter
100pF
0.33µF
3.3kΩ
35
36
IOGND
37
CC
IOV
38
PLLVCC
39
PLLGND
40
CC
VCOV
41
VCOGND
42
VCOHGND
43
1.6kΩ 100Ω
∗3
∗
4
IREF
44
RC2
45
RC1
46
IRGND
47
CC
IRV
48
CC
IOV
1
CC
VBB
PECLV
2
34
IOGND
DSYNCH
VCOH
3
33
DSYNCL
VCOL
4
32
5
CLKH
VCO
31
6
CLKL
HOLD
30
CLK/2H
SYNCH
7
29
CLK/2L
SYNCL
8
CC
PECLV
SYNC
9
2728
IOGND
SENABLE
10
26
11
CC
TTLV
SCLK
25
TTLGND
DSYNC
CLK
CLKN
CLK/2
CLK/2N
DGND
DV
UNLOCK
DIVOUT
SEROUT
TLOAD
SDATA
12
CC
CS
24
23
22
21
20
19
18
V
CC
100kΩ
UNLOCK output
∗
2
17
16
15
10nF
GND
14
13
GND VCC (+5.0V)
Notes)
∗
1
Unless otherwise specified, all capacitors are 0.1µF.
∗
2
Vary the external resistor and capacitor values of the
UNLOCK output as necessary.
∗
3
This external resistor (1.6kΩ) should be a metal film
resistor in consideration of temperature characteristics.
∗
4
The loop filter's capacitors and resistor should also be
temperature compensated.
SYNCH, SYNCL: PECL level
HOLD
complementary input
– 34 –
Control
Register
Page 35
CXA3106Q
(2) Recommended TTL I/O circuit
The peripheral circuits mainly use TTL for digital input and output. Of course, PECL and TTL can also be
mixed.
1200pF
Loop Filter
100pF
0.33µF
3.3kΩ
35
36
IOGND
37
CC
IOV
38
PLLVCC
39
PLLGND
40
CC
VCOV
41
VCOGND
42
VCOHGND
43
1.6kΩ 100Ω
∗
3
∗
4
IREF
44
RC2
45
RC1
46
IRGND
47
CC
IRV
48
CC
IOV
1
CC
PECLV
2
VBB
IOGND
34
DSYNCH
VCOH
3
33
DSYNCL
VCOL
4
32
5
CLKH
VCO
31
6
CLKL
HOLD
30
CLK/2H
SYNCH
7
29
CLK/2L
SYNCL
8
CC
PECLV
SYNC
9
2728
IOGND
SENABLE
10
26
11
CC
TTLV
SCLK
25
TTLGND
DSYNC
CLK
CLKN
CLK/2
CLK/2N
DGND
DV
UNLOCK
DIVOUT
SEROUT
CS
TLOAD
SDATA
12
CC
TTL level output pins
24
23
22
21
20
19
18
17
16
15
V
GND
CC
100kΩ
10nF
UNLOCK output
∗
2
14
13
GND VCC (+5.0V)
Notes)
∗
1
Unless otherwise specified, all capacitors are 0.1µF.
∗
2
Vary the external resistor and capacitor values of the
UNLOCK output as necessary.
∗
3
This external resistor (1.6kΩ) should be a metal film
resistor in consideration of temperature characteristics.
∗
4
The loop filter's capacitors and resistor should also be
temperature compensated.
HOLD
Control
Register
SYNC: TTL level input
– 35 –
Page 36
CXA3106Q
Connecting the CXA3106Q with Sony ADC (Demultiplex Mode)
When connecting the PLL output to A/D converters with built-in demultiplex function such as the
CXA3026AQ/CXA3026Q/CXA3086Q (Sony), a simple system can be configured by connecting the CLK
(PECL) and CLKN (PECL) outputs of the CXA3106Q to the CLK (PECL) and CLKN (PECL) inputs of each
A/D converter, respectively, and the 1/2 CLK (PECL) and 1/2 CLKN (PECL) outputs of the CXA3106Q to the
RESETN (PECL) and RESET (PECL) inputs of each A/D converter, respectively. (when the PLL counter
value N is an even number)
Wiring Diagram
R
G
VIN
CLK (PECL)
CLKN (PECL)
RESETN (PECL)
RESET (PECL)
VIN
CLK (PECL)
CLKN (PECL)
RESETN (PECL)
RESET (PECL)
ADC
CXA3026AQ
CXA3026Q
CXA3086Q
ADC
CXA3026AQ
CXA3026Q
CXA3086Q
8 or 6
TTL
8 or 6
TTL
8 or 6
TTL
8 or 6
CMOS LOGIC
TTL
B
CLK (PECL)
CLKN (PECL)
1/2 CLK (PECL)
PLL
CXA3106Q
VIN
CLK (PECL)
CLKN (PECL)
RESETN (PECL)
RESET (PECL)
DSYNC (TTL)
1/2 CLKN (PECL)
ADC
CXA3026AQ
CXA3026Q
CXA3086Q
(TTL)
1/2 CLK
– 36 –
8 or 6
TTL
8 or 6
TTL
• CXA3026AQ 8bit 140MSPS ADC
• CXA3026Q 8bit 120MSPS ADC
• CXA3086Q 6bit 140MSPS ADC
CLK (TTL)
RESET (TTL)
Page 37
CXA3106Q and Sony ADC (Demultiplex Mode) Timing
The CXA3106Q and CXA3026Q/CXA3026AQ/CXA3086Q timings are shown below.
Here, the important timings are as follows.
(The clock cycle is labeled as T.)
• Within the A/D converters
Clock input vs. reset input
The setup time is T–1ns and the hold time is 0ns, satisfying the A/D converter specifications.
• Within the CMOS LOGIC at the rear end of the A/D converters
A/D converter data output vs. 1/2 clock output timing
The setup time is T–4.5ns and the hold time is T–0.5ns. (These timings also include combinations of
three A/D converters from different lots, and are defined for all operating temperatures and all operating
supply voltages. See the CXA3026Q/CXA3026AQ/CXA3086Q specifications for a detailed description.)
• Within the CMOS LOGIC at the rear end of the A/D converters
DSYNC signal from CXA3106Q vs. A/D converter 1/2 clock output
The setup time is T–3ns and the hold time is T–5ns.
CXA3106Q
CXA3106Q
CLK (PECL)
out
DSYNC (TTL)
out
1/2CLK (PECL)
out
CXA3026Q
CXA3026AQ
CXA3086Q
1/2CLK (TTL)
out
T
0 to 1ns
4.5 to 8ns
3 to 7.5ns
Thold min.
T–5ns
Tsetup min.
T–3ns
Tsetup min.
T–4.5ns
∗
See the CXA3026AQ/Q and
CXA3086Q specifications.
Thold min.
T–0.5ns
DATA (TTL)
out
– 37 –
Page 38
CXA3106Q
Connecting the CXA3106Q with Sony ADC (Straight Mode)
When connecting the PLL output to A/D converters such as the CXA3026AQ/CXA3026Q/CXA3086Q (Sony),
a simple system can be configured as shown below.
Wiring Diagram
R
G
VIN
CLK (PECL)
CLKN (PECL)
ADC
CXA3026AQ
CXA3026Q
CXA3086Q
VIN
CLK (PECL)
CLKN (PECL)
ADC
CXA3026AQ
CXA3026Q
CXA3086Q
8 or 6
TTL
8 or 6
TTL
CMOS LOGIC
B
CLK (PECL)
CLK (TTL)
CLKN (PECL)
PLL
CXA3106Q
VIN
CLK (PECL)
CLKN (PECL)
DSYNC (TTL)
ADC
CXA3026AQ
CXA3026Q
CXA3086Q
8 or 6
TTL
CLK (TTL)
RESET (TTL)
• CXA3026AQ 8bit 140MSPS ADC
• CXA3026Q 8bit 120MSPS ADC
• CXA3086Q 6bit 140MSPS ADC
– 38 –
Page 39
CXA3106Q and Sony ADC (Straight Mode) Timing
The CXA3106Q and CXA3026Q/CXA3026AQ/CXA3086Q timings are shown below.
Here, the important timings are as follows.
(The clock cycle is labeled as T.)
• Within the CMOS LOGIC at the rear end of the A/D converters
A/D converter data output vs. clock output from CXA3106Q
The setup time is T–8.5ns and the hold time is 2ns. (These timings also include combinations of three A/D
converters from different lots, and are defined for all operating temperatures and all operating supply
voltages. See the CXA3026Q/CXA3026AQ/CXA3086Q specifications for a detailed description.)
• Within the CMOS LOGIC at the rear end of the A/D converters
DSYNC signal from CXA3106Q vs. clock output from CXA3106Q
The setup time is T–4.5ns and the hold time is 1.5ns.
CXA3106Q
CXA3106Q
CLK (PECL)
out
CLK (TTL)
out
DSYNC (TTL)
out
CXA3026Q
CXA3026AQ
CXA3086Q
T
1.5 to 4.5ns
1.5 to 3ns
Thold min.
1.5ns
Tsetup min.
T–4.5ns
Tsetup min.
T–8.5ns
DATA (TTL)
out
6.5ns min
10ns max
Thold min.
2ns
– 39 –
Page 40
CXA3106Q
CXA3106Q-PWB (CXA3106Q Evaluation Board)
The CXA3106Q-PWB is an evaluation board for the CXA3106Q PLL-IC. This board makes it possible to easily
evaluate the CXA3106Q's performance using the supplied control program (Note: IBM PC/AT, MS-DOS 5.0
and newer US mode specifications).
Features
• Two input level (TTL and PECL) SYNC input
• Two output level (TTL and PECL) CLK, CLK2 and DSYNC output
• Supply voltage: +5.0V
Absolute Maximum Ratings (Ta = 25°C)
Supply voltage VCC –0.5 to +7.0 V
Recommended Operating Conditions
• Supply voltage VCC 4.75 to 5.25 V
GND 0 V
• Digital input (PECL) DIN (High) VCC – 1.1 V (Min.)
DIN (Low) VCC – 1.5 V (Max.)
(TTL) DIN (High) GND + 2.0 V (Min.)
DIN (Low) GND + 0.8 V (Max.)
• Operating ambient temperature
Ta –20 to +75 °C
Block Diagram
VCO input
(PECL/TTL)
SYNC input
(PECL/TTL)
CONTROL BUS (TTL)
SENABLE, SCLK, SDATA
Loop Filter
DSYNC output
(PECL/TTL)
CLK output
CXA3106Q
48pin QFP
3
(PECL/TTL)
CLK/2 output
(PECL/TTL)
VBB (PECL)
SEROUT (TTL)
DIVOUT (TTL)
UNLOCK (TTL)
– 40 –
Page 41
Setting Methods and Notes on Operation
Input pins
This PWB supports TTL single and PECL complementary input.
Input pins: SYNC: TTL level input, 10 to 100kHz
SYNCL: PECL low level input, 10 to 100kHz
SYNCH: PECL high level input, 10 to 100kHz
VCO: TTL level input. This is a test pin and is therefore normally not used.
VCOL: PECL low level input. This is a test pin and is therefore normally not used.
VCOH: PECL high level input. This is a test pin and is therefore normally not used.
Output pins
This PWB supports TTL single and PECL complementary output.
CXA3106Q
DSYNCH,
DSYNCL: PECL level complementary delay SYNC outputs. The output range is 10 to 100kHz.
DSYNC: TTL level delay SYNC output. The output range is 10 to 100kHz.
CLKH,
CLKL: PECL level complementary CLK outputs. The output range is 10 to 120MHz.
CLK,
CLKN: TTL level complementary CLK outputs. The output range is 10 to 80MHz.
CLK/2H,
CLK/2L: PECL level complementary 1/2 CLK outputs. The output range is 5 to 60MHz.
CLK/2,
CLK/2N: TTL level complementary CLK outputs. The output range is 5 to 60MHz.
VBB: Outputs the PECL amplitude threshold voltage.
SEROUT: TTL level control register serial data output.
DIVOUT: TTL level internal programmable counter test output.
UNLOCK: TTL level UNLOCK output. This pin requires external circuits such as appropriate capacitors and
resistors.
See the IC specifications for a detailed description.
PECL outputs (VBB, DSYNCH, DSYNCL, CLKH, CLKL, CLK/2H, CLK/2L) are output constantly, but TTL
outputs (DSYNC, CLK, CLKN, CLK/2, CLK/2N, SEROUT, DIVOUT, UNLOCK) are controlled by the respective
control registers. Therefore, the enable/disable settings should be made in accordance with the application.
See the following pages for the setting method.
– 41 –
Page 42
CXA3106Q
Jumper Wire Settings
S1, S2: These enable/disable HOLD (Pin 6). HOLD is active high, so the jumper wire should be connected to
S2 (HOLD = low) for normal use. When using HOLD, connect the jumper wire to S1 (HOLD = high).
(For the initial setting, the jumper wire is connected to S2.)
S3, S4: These enable/disable TLOAD (Pin 13). Connect the jumper wire to S4 (TLOAD = high) for normal use.
When using TLOAD, connect the jumper wire to S3 (TLOAD = low). (For the initial setting, the jumper
wire is connected to S4.)
S5, S6: These enable/disable CS (Pin 14). Connect the jumper wire to S6 (CS = high) for normal use. When
using Power Save, connect the jumper wire to S5 (CS = low). (For the initial setting, the jumper wire is
connected to S6.)
Supplied Program
This PWB is equipped with a control program that facilitates evaluation of the CXA3106Q. Operation methods
and precautions are as follows.
1) Compatible personal computers
Use an IBM PC/AT or compatible machine equipped with a 25-pin D-SUB parallel port (printer port). Also,
operating systems which support the program are MS-DOS 5.0 or newer and MS-Windows 3.1 or newer.
(When using Windows, start the program from the DOS window.)
2) Connect the supplied cable
Connect the supplied cable to the parallel port of the personal computer and the DBUS1 connector of the
CXA3106Q-PWB.
D-SUB 25-pin parallel connector pin arrangement
113
14 25
2pin : SCLK
3pin : SDATA
4pin : SENABLE
11pin : SERIN
19pin : GND
3) Connect the power cable and supply power to the CXA3106Q-PWB
4) Start the program
A) Boot the personal computer and then shift to the directory containing the program.
B) Set MS-DOS to US mode. → US Return or Enter
C) Input the program name. →∗1CXA3106A or CXA3106B Return or Enter → Move to the program screen.
∗1
Only one of either CXA3106A or CXA3106B can be used as the program name depending on the printer
port setting of the personal computer.
– 42 –
Page 43
5) Description of the program screen
A) When the program is started, the following initial screen is displayed.
Please type the name of the initialization file OR press ENTER.
The file extention.INI should not be included. The default file
when ENTER is pressed is CXA3106.INI
Filename > _
When this screen appears, press the Return or Enter key. The screen shifts to the function setting screen.
B) Function settings
When the program is loaded, the following function setting screen appears.
CXA3106Q
CXA3106 PLL REGISTERS
Divisor 1344
Divider 2
Coarse Delay 00 Fine Delay 10
Charge Pump 10
Polarity Power
SYNC DSYNC PD SCAN SYNTH VCO Bypass
1 1 1 OFF ON ON
O/P Enable
DIVOUT UNLOCK DSYNC CLK2 NCLK2 CLK1 NCLK1
OFF OFF OFF OFF OFF OFF OFF
Use arrow keys to select data bit. Press ENTER to toggle and load data.
Use Pg Up and Pg Dn to increment/decrement divisor and fine delay registers.
Press a to abort, s to scan registers MIXED SIGNAL SYSTEMS JAN 1997
– 43 –
Page 44
CXA3106Q
Divisor
This is used to input the frequency division ratio of the program counter. The value can be changed as
desired from 9 to 4111 by moving the cursor to the position of the number and pressing the Return or Enter
key. (Note: The operating range of the CXA3106Q is from 256 to 4096.) The value can also be incremented
or decremented by one step by pressing the Page Up or Page Down key, respectively.
The internal VCO has an oscillator frequency of 40 to 120MHz, so the output frequency and Divider (VCO
frequency divider) setting range are as follows.
1/1
1/2
Divider
1/4
20 60
Divider = 2
10 30
Divider = 4
40 120
40 80 120
O/P Frequency [MHz]
Divider = 1
Divider
This sets the VCO output frequency division ratio to 1/1, 1/2 or 1/4. The frequency division ratio changes
repeatedly in the order of 1/1 → 1/2 → 1/4 → 1/1 each time the cursor is moved to the position of the number
and the Return or Enter key is pressed.
Coarse Delay
This is the DSYNC upper delay time setting. The value can be changed by moving the cursor to the position
of the number and pressing the Return or Enter key. The delay time variable range settings are "00" (1 CLK),
"01" (2 CLK), "10" (3 CLK) or "11" (4 CLK).
Fine Delay
This is the DSYNC lower delay time setting. The value can be changed by moving the cursor to the position
of the number and pressing the Return or Enter key. The value can also be incremented or decremented by
one step by pressing the Page Up or Page Down key, respectively. The delay time can be varied from 1/16
CLK to 32/16 CLK by setting "0" to "31", respectively.
Charge Pump
This is the charge pump circuit KI setting. The value can be changed by moving the cursor to the position of
the number and pressing the Return or Enter key. KI can be set to "00" (about 100µA), "10" (about 400µA) or
"11" (about 1.6mA).
The setting "01" is not used. (Setting "01" is the same as setting "00".)
Polarity
These are the SYNC, DSYNC and PD (Phase Detector) polarity inversion settings, and should be set as
necessary such as when inverting the SYNC input and DSYNC output waveforms. The setting value "1" is
positive polarity, and "0" is negative polarity. These should normally all be set to "1". (Fix PD to "1" other than
during test mode.)
– 44 –
Page 45
CXA3106Q
Power
SCAN: This is the control register read setting. When this is ON, the control register serial data is
output from SEROUT (Pin 15). This should normally be set to OFF.
SYNTH: This is the enable/disable setting for this IC. This should normally be set to ON.
VCO Bypass: This is set to OFF when testing the program counter. This should normally be set to ON.
O/P Enable
These are the enable/disable settings for each TTL output (DIVOUT, UNLOCK, DSYNC, CLK2, NCLK2,
CLK1 and NCLK1). Set to ON when performing evaluation using TTL output.
– 45 –
Page 46
CXA3106Q
C) Description of readout mode
This program has a function (readout mode) that reads the contents written to the control registers from the
CXA3106Q SEROUT (Pin 15) and displays these contents on the screen. This function is described below.
1) Set SCAN to ON at the function setting screen.
2) Press the S key.
The following screen appears.
SCAN RESULT, CXA3106 PLL REGISTERS
Register 1 DIVREG1 00111000
Register 2 DIVREG2 0101
Register 3 CENFREREG 1011111
Register 4 DELAYREG 0010000
Register 5 CPREG 100
Register 6 TTLPOLREG 00000011
Register 7 TESTPOWREG 0111
Press r to return to PLL REGISTERS MENU.
Press a to abort MIXED SIGNAL SYSTEMS AUG 1996
This screen conforms to the Control Register Table listed in the CXA3106Q specifications.
3) Press the R key to return to the original function setting screen.
D) Quit the program
Press the A key to quit the program.
– 46 –
Page 47
CXA3106Q
Substrate Pattern (parts surface)
Substrate Pattern (solder surface)
– 47 –
Page 48
CXA3106Q
Control Register
DBUS1
PR2
SEROUT
BNC3
VCO
SYNCH
SYNCL
SYNC
BNC4
BNC5
BNC6
PR3
DIVOUT
BNC2
VCOL
S1
S2
PR4
UNLOCK
BNC1
S3
VCOH
CXA3106Q PCB v1.1
R19
IC1
S6
S4
S5
PR11
CLK/2N
VCC
PR12
CLK/2
PR13
CLKN
C21
33µ
GND
+
PR8
DSYNCL
R3
R10
PR6
CLKL
R7
R14
PR1
CLK/2L
R6
R13
PR14
CLK
R1
R8
R2
R9
R4
R11
R5
R12
PR10
VBB
PR9
DSYNCH
PR7
CLKH
PR5
CLK/2H
PR15
DSYNC
Silk Screen (parts surface)
C12
C19
C18
C2
C6
C4
C20
C3
C11
C7
C10
C5
C8
C9
C1
C14
C13
C18
C15
C17
C16
Silk Screen (solder surface)
– 48 –
Page 49
CXA3106Q
C20
1200p
C19
R18
GND
0.33µ
3.3k
PR10A
VBB
PR9A
DSYNCH
PR8A
PR7A
DSYNCL
CLKH
PR6A
CLKL
PR5A
PR1A
CLK/2H
CLK/2L
PR15A
PR14A
DSYNC
CLK
PR13A
CLKN
PR12A
PR11A
CLK/2
CLK/2N
GND
R8 330R1
R9 330R2
R10 330R3R11 330R4R14 330R7R12 330R5R13 330
R6
VCC
C1
C13
C14
C15
C18
C16
26
CC
TTLV
SCLK
11
0.1µ
C9
25
TTLGND
CC
SDATA
12
C17
0.1µ
0.1µ
DSYNC
CLK
CLKN
CLK/2
CLK/2N
DGND
DV
UNLOCK
DIVOUT
SEROUT
CS
TLOAD
GND
24
23
22
21
20
19
C7
18
0.1µ
PR4A
UNLOCK
17
16
S6
15
14
S5
13
PR3A
DIVOUT
PR2A
SEROUT
S3 S4
CC
PWR1
PWR2
GND
V
VCC
C21
GND
33µ
0.1µ
0.1µ
0.1µ
0.1µ
0.1µ
C8
29
CLK/2L
SYNCL
8
0.1µ
28
CC
PECLV
SYNC
9
27
IOGND
SENABLE
10
CC
V
C10
0.1µ
31
35
34
VBB
IOGND
VCOH
2
33
DSYNCL
DSYNCH
VCOL
3
4
32
CLKH
VCO
5
S1
30
CLKL
CLK/2H
CXA3106Q
HOLD
SYNCH
6
7
S2
R19
1.6k
C6
C5
C4
C11
0.1µ
0.1µ
0.1µ
100p
C12
C3
0.1µ
0.1µ
36
CC
IOGND
37
38
39
40
41
42
43
44
45
46
47
48
PECLV
IOV
CC
PLLV
CC
PLLGND
VCOV
CC
VCOGND
VCOHGND
IREF
RC2
RC1
IRGND
CC
IRV
CC
IOV
1
C2
0.1µ
VCOL
VCOH
BNC2
BNC1
PWB Circuit Diagram
BNC3
VCO
BNC4
SYNCH
BNC5
BNC6
SYNCL
SYNC
– 49 –
1
DBUS1
GND
5
Control Register
Note) R1 to R7 are not mounted.
Page 50
Package Outline Unit: mm
15.3 ± 0.4
CXA3106Q
48PIN QFP (PLASTIC)
+ 0.4
12.0 – 0.1
2536
37
48
112
0.8 0.3 – 0.1
+ 0.15
24
13
± 0.12
M
+ 0.35
2.2 – 0.15
+ 0.1
0.15 – 0.05
0.15
+ 0.2
0.1 – 0.1
13.5
0.9 ± 0.2
PACKAGE STRUCTURE
EPOXY RESIN
SOLDER / PALLADIUM
PLATING
COPPER / 42 ALLOY
0.7g
SONY CODE
EIAJ CODE
JEDEC CODE
QFP-48P-L04
∗QFP048-P-1212-B
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 50 –
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