Page 1
– 1 –
CXA3026Q
E94711D92
8-bit 120MSPS Flash A/D Converter
Description
The CXA3026Q is an 8-bit high-speed flash A/D
converter capable of digitizing analog signals at the
maximum rate of 120MSPS. ECL, PECL or TTL can
be selected as the digital input level in accordance
with the application. The TTL digital output level
allows 1:2 demultiplexed output.
Features
• Differential linearity error: ±0.5LSB or less
• Integral linearity error: ±0.5LSB or less
• High-speed operation with a maximum conversion
rate of 120MSPS
• Low input capacitance: 21pF
• Wide analog input bandwidth: 150MHz
• Low power consumption: 760mW
• Low error rate
• Excellent temperature characteristics
• 1:2 demultiplexed output
• 1/2 frequency divided clock output
(with reset function)
• Compatible with ECL, PECL and TTL digital input levels
• Single +5V power supply operation available
• Surface mounting package
Pin Configuration (Top View)
Structure
Bipolar silicon monolithic IC
Applications
• Magnetic recording (PRML)
• Communications (QPSK, QAM)
• LCDs
• Digital oscilloscopes
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
48 pin QFP (Plastic)
LEAD TREATMENT: PALLADIUM PLATING
CLK/E
N.C.
CLK/T
N.C.
N.C.
DV
CC2
DGND2
P2D0
P2D1
P2D2
P2D3
CLKN/E
P2D4
P2D7
P2D6
DGND1
DV
CC
1
DV
CC
2
DGND2
P1D0
P1D1
P1D2
P1D3
P2D5
RESETN/E
SELECT
RESETN/T
INV
CLKOUT
DV
CC2
DGND2
P1D7
P1D6
P1D5
P1D4
RESET/E
DV
EE
3
V
RM
1
AGND
AV
CC
V
IN
V
RM
2
AV
CC
V
RM
3
AGND
V
RT
DGND3
V
RB
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
2
3
4
5
6
7
8
9
10
11
12 1
Page 2
– 2 –
CXA3026Q
Absolute Maximum Ratings (Ta = 25°C)
Unit
• Supply voltage AVCC, DVCC1, DVCC2 –0.5 to +7.0 V
DGND3 –0.5 to +7.0 V
DVEE3 –7.0 to +0.5 V
DGND3 – DVEE3 –0.5 to +7.0 V
• Analog input voltage VIN VRT – 2.7 to AVCC V
• Reference input voltage VRT 2.7 to AVCC V
VRB VIN – 2.7 to AVCC V
|VRT – VRB| 2.5 V
• Digital input voltage ECL (
∗∗∗/E∗
1
) DVEE3 to +0.5 V
PECL (
∗∗∗
/E) –0.5 to DGND3 V
TTL (
∗∗∗
/T, INV) –0.5 to DVCC1 V
other (SELECT) –0.5 to DVCC1 V
VID
∗
2
(|
∗∗∗
/E –
∗∗∗
N/E|) 2.7 V
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation PD 2 W
(when mounted on a glass fabric base epoxy board with 50mm x 50mm, 1.6mm thick)
Recommended Operating Conditions
With a single power supply With dual power supplies Unit
Min. Typ. Max. Min. Typ. Max.
• Supply voltage DVCC1, DVCC2, AVCC +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 V
DGND1, DGND2, AGND –0.05 0 +0.05 –0.05 0 +0.05 V
DGND3 +4.75 +5.0 +5.25 –0.05 0 +0.05 V
DVEE3 –0.05 0 +0.05 –5.5 –5.0 –4.75 V
• Analog input voltage VIN VRB VRT VRB VRT V
• Reference input voltage VRT +2.9 +4.1 +2.9 +4.1 V
VRB +1.4 +2.6 +1.4 +2.6 V
|VRT – VRB| 1.5 2.1 1.5 2.1 V
• Digital input voltage ECL (
∗∗∗
/E) : VIH DGND3 – 1.05 DGND3 – 0.5 V
: VIL DGND3 – 3.2 DGND3 – 1.4 V
PECL (
∗∗∗
/E) : VIH DGND3 – 1.05 DGND3 – 0.5 V
: VIL DGND3 – 3.2 DGND3 – 1.4 V
TTL (
∗∗∗
/T, INV) : VIH 2.0 2.0 V
: VIL 0.8 0.8 V
other (SELECT) : VIH DVCC1 DVCC1 V
: VIL DGND1 DGND1 V
VID
∗
2
(|
∗∗∗
/E –
∗∗∗
N/E|) 0.4 0.8 0.4 0.8 V
•
Maximum conversion rate
Fc (Straight mode) 100 100 MSPS
(DMUX mode) 120 120 MSPS
• Ambient temperature Ta –20 +75 –20 +75 °C
∗1∗∗∗
/E and
∗∗∗
/T indicate CLK/E and CLK/T, etc. for the pin name.
∗
2
VID: Input Voltage Differential
ECL and PECL switching level
VID
V
IL (min.)
V
IH
VTH (DGND3 – 1.2V)
V
IL
VIH (max.)
DGND3
Page 3
– 3 –
CXA3026Q
Block Diagram
6bits
2
3
5
8
10
12
13
14
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
44
1
r/2
•
•
•
•
•
•
•
•
•
1
2
63
64
65
126
127
128
129
191
192
193
254
255
•
•
•
r
6bits
9
7
4
r1
r2
r
r
r
r
r
r
r
r
r
r
r
r
r
r
/2
6bits
6bits
8bits
8bits
Delay
15
46
47
48
Select
D Q
Q
45
SELECT
11
43
DGND1 DVEE3
DGND2
AGND
AVCC DVCC2
DV
CC1INV DGND3
6
V
RT
VRM3
V
IN
VRM2
V
RB
VRM1
CLK/T
CLK/E
CLKN/E
RESETN/T
RESETN/E
RESET/E
TTLOUT
LATCHB
TTLOUT
LATCHA
6-bit LATCH + ENCODER
ENCODER
CLKOUT
N. C.
P2D0
P2D1
P2D2
P2D3
P2D4
P2D5
P2D6
P2D7
P1D0
P1D1
P1D2
P1D3
P1D4
P1D5
P1D6
P1D7
(LSB)
(MSB)
(LSB)
(MSB)
Page 4
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CXA3026Q
Pin Description and I/O Pin Equivalent Circuit
Analog ground.
Separated from the digital ground.
Analog power supply.
Separated from the digital power
supply.
Digital ground.
Digital power supply.
Digital power supply.
Ground for ECL input.
+5V for PECL and TTL input.
Digital power supply.
–5V for ECL input.
Ground for PECL and TTL input.
No connected pin.
Not connected with the internal
circuits.
Clock input.
CLK/E complementary input.
When left open, this pin goes to the
threshold potential.
Only CLK/E can be used for
operation, but complementary input
is recommended to attain fast and
stable operation.
Reset input.
When the input is set to low level,
the built-in CLK frequency divider
circuit can be reset.
RESETN/E complementary input.
When left open, this pin goes to the
threshold voltage. Only RESETN/E
can be used for operation.
3, 10
5, 8
20, 29
32, 41
19, 30
31, 42
12
1
16, 17
18
13
14
48
47
AGND
AVCC
DGND1
DGND2
DVCC1
DVCC2
DGND3
DVEE3
N.C.
CLK/E
CLKN/E
RESETN/E
RESET/E
GND
+5V
(typ.)
GND
+5V
(typ.)
+5V (Typ.)
(With a
single
power
supply)
GND
(With dual
power
supplies)
GND
(With a
single
power
supply)
–5V (Typ.)
(With dual
power
supplies)
ECL/
PECL
Pin
No.
Symbol
I
I
I
I
I/O
Standard
voltage level
Equivalent circuit Description
DGND3
DV
EE3
r r
1.2V
r
r
13
14
48
47
Page 5
– 5 –
CXA3026Q
15 CLK/T
Clock input.
46
RESETN/T
TTL
TTL
Vcc
or
GND
Reset input.
When left open, this input goes to
high level. When the input is set to
low level, the built-in CLK frequency
divider circuit can be reset.
44
INV
Data output polarity inversion input.
When left open, this input goes to
high level.
(See Table 1. I/O Correspondence
Table.)
45
SELECT
Data output mode selection.
(See Table 2. Operating Mode
Table.)
4.0V
(typ.)
11
VRT
Top reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip capacitor.
VRB +
(VRT – VRB)
9
VRM3
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
7
VRM2
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
4
VRM1
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
2.0V
(typ.)
2
VRB
Bottom reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip capacitor.
DVCC1
DGND1
1.5V
r/2
r
DVEE3
15
46
DVCC1
DGND1
DVEE3
44
DVCC1
DGND1
DVEE3
45
r1
r/2
Comparator 1
Comparator 63
Comparator 64
Comparator 128
Comparator 191
Comparator 127
Comparator 192
Comparator 255
r
r
2
r/2
r
r
r
r
4
7
9
2
11
r
I
I
I
I
I
4
3
4
2
VRB +
(VRT – VRB)
4
1
VRB +
(VRT – VRB)
Pin
No.
Symbol I/O
Standard
voltage level
Equivalent circuit Description
Page 6
– 6 –
CXA3026Q
Clock output.
(See Table 2. Operating Mode Table.)
33
to
40
P1D0
to
P1D7
Port 1 side data output.
21
to
28
P2D0
to
P2D7
43 CLKOUT
Port 2 side data output.
6 VIN
VRT
to
VRB
I
TTL
O
O
O
Analog input.
AVCC
Comparator
Vref
AGND
DVEE3
AVCC
6
DVCC2
DGND2
DVCC1
DGND1
100K
DVEE3
21
28
33
40
43
to
to
Pin
No.
Symbol I/O
Standard
voltage level
Equivalent circuit Description
Page 7
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CXA3026Q
Resolution
DC characteristics
Integral linearity error
Differential linearity error
Analog input
Analog input capacitance
Analog input resistance
Analog input current
Reference input
Reference resistance
Reference current
Offset voltage VRT side
VRB side
Digital input (ECL, PECL)
Digital input voltage: High
: Low
Threshold voltage
Digital input current: High
: Low
Digital input capacitance
Digital input (TTL)
Digital input voltage: High
: Low
Threshold voltage
Digital input current: High
: Low
Digital input capacitance
Digital output (TTL)
Digital output voltage
: High
: Low
Switching characteristics
Maximum conversion rate
Aperture jitter
Sampling delay
Clock high pulse width
Clock low pulse width
RESETN_CLK setup
RESETN_CLK hold time
CLKOUT output delay
Data output delay
Output rise time
Output fall time
Electrical Characteristics
(DVCC1, 2, AVCC, DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, Ta = 25°C)
Item Symbol Min. Typ. Max. UnitConditions
EIL
EDL
CIN
RIN
IIN
Rref
∗
3
Iref
∗
4
EOT
EOB
VIH
VIL
VTH
IIH
IIL
VIH
VIL
VTH
IIH
IIL
VOH
VOL
Fc
Taj
Tds
Tpw1
Tpw0
T_rs
T_rh
Td_clk
Tdo1
Tdo2
Tr
Tf
4
0
75
9.7
2
2
DGND3 – 1.05
DGND3 – 3.2
–50
–75
2.0
–50
–500
2.4
120
3
3.2
3.2
3.5
0
4.5
T
∗
5
6.5
8
21
115
17.4
DGND3 – 1.2
1.5
10
4.5
7
T + 1
8
2
2
±0.5
±0.5
50
500
155
28
15
10
DGND3 – 0.5
DGND3 – 1.4
+50
0
5
0.8
0
0
5
0.5
6
8
T + 2
10
bits
LSB
LSB
pF
kΩ
µA
Ω
mA
mV
mV
V
V
V
µA
µA
pF
V
V
V
µA
µA
pF
V
V
MSPS
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VIN = 2Vp-p, Fc = 5MSPS
VIN = +3.0V + 0.07Vrms
VIH = DGND3 – 0.8V
VIL = DGND3 – 1.6V
VIH = 3.5V
VIL = 0.2V
IOH = –2mA
IOL = 1mA
DMUX mode
CLK
CLK
RESETN – CLK
RESETN – CLK
(CL = 5pF)
DMUX mode (CL = 5pF)
(CL = 5pF)
0.8 to 2.0V (CL = 5pF)
0.8 to 2.0V (CL = 5pF)
∗
These characteristics are for PECL input,unless otherwise specified.
Page 8
– 8 –
CXA3026Q
∗
5
T =
∗
6
TPS: Times Per Sample
∗
7
Pd = (ICC + IEE) · VCC +
(VRT – VRB)
2
Rref
Table 1. I/O Correspondence Table
Dynamic characteristics
Input bandwidth
S/N ratio
Error rate
Power supply
Supply current
Supply current
Power consumption
ICC
IEE
Pd
∗
7
150
125
0.4
660
46
40
145
0.6
760
10
–12
10
–9
10
–9
185
0.8
960
MHz
dB
dB
TPS
∗
6
TPS
TPS
mA
mA
mW
VIN = 2Vp-p, –3dB
Fc = 120MSPS,
fin = 1kHz Fs
DMUX mode
Fc = 120MSPS,
fin = 29.999MHz Fs
DMUX mode
Fc = 120MSPS,
fin = 1kHz Fs
DMUX mode
Error > 16LSB
Fc = 120MSPS,
fin = 29.999MHz Fs
DMUX mode
Error > 16LSB
Fc = 100MSPS,
fin = 24.999MHz Fs
Straight mode
Error > 16LSB
{
{
{
{
{
1
Fc
INV
1
D7 D0 D7 D0
0
VIN
VRT
VRM2
VRB
255
254
.
.
.
128
127
.
.
.
1
0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0
.
.
.
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
.
.
.
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
.
.
.
0 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0
.
.
.
1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1
Step
Item Symbol Min. Typ. Max. UnitConditions
∗
3
Rref: Resistance value between VRT and VRB
∗
4
Iref =
VRT – VRB
Rref
Page 9
– 9 –
CXA3026Q
Electrical Characteristics Measurement Circuit
Current Consumption Measurement Circuit
VRT
VIN
VRB
AVCC
DVCC1
DVCC2
DGND3
DGND2
DGND1
AGND
CLK/E
DV
EE3
5MHz PECL
4V
1.95V
2V
5V 5V
Icc
I
EE
Integral Linearity Error Measurement Circuit
Differential Linearity Error Measurement Circuit
CXA3026Q
A < B A > B
Comparator
A8
to
A1
A0
B8
to
B1
B0
Buffer
Controller
DVM
8 8
“1”“0”
000···00
to
111···10
V
IN
+V
–V
S2
S1
S1: ON when A < B
S2: ON when A > B
Sampling Delay Measurement Circuit
Aperture Jitter Measurement Circuit
CXA3026Q
OSC1
φ: Variable
OSC2
Logic
Analizer
100MHz
100MHz
Amp
ECL
Buffer
CLK
V
IN
8
fr
1024
samples
Aperture Jitter Measurement Method
VIN
CLK
V
IN
CLK
VRT
VRM2
V
RB
129
128
127
126
125
Sampling timing fluctuation
(= aperture jitter)
σ (LSB)
∆υ
∆ t
Error Rate Measurement Circuit
Comparator
A > B
Pulse
Counter
CXA3026Q
Signal
Source
Latch
Latch
1/8
+
Signal
Source
Fc
4
–1kHz
2Vp-p Sin Wave
Fc
V
IN
CLK CLK
8
16LSB
A
B
Where σ (LSB) is the deviation of the output codes when
the largest slew rate point is sampled at the clock which
has exactly the same frequency as the analog input
signal, the aperture jitter Taj is:
Taj = σ/ = σ/ ( )
∆t
∆υ
2
256
× 2πf
Page 10
– 10 –
CXA3026Q
Description of Operating Modes
The CXA3026Q has two types of operating modes which are selected with Pin 45 (SELECT).
1. DMUX mode (See Application Circuit 1-(1), (2) and (3).)
Set the SELECT pin to Vcc for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the
data is output after being demultiplexed by this 1/2 frequency divided clock. The 1/2 frequency divided clock,
which has adequate setup time and hold time for the output data, is output from the CLKOUT pin.
When resetting this 1/2 frequency divided clock, the low level of the RESET signal should be input to the
RESETN pin (Pin 46or 48). The RESET signal requires the setup time (T_rs ≥ 3.5ns) and hold time (T_rh ≥
0ns) to the clock rising edge because it is synchronized with and taken in the clock. Therefore, set the RESET
signal to low for T_rs (min.) + T_rh (min.) = 3.5ns or longer to the clock rising edge.
The reset period can be extended by making the low level period of the RESET signal longer because the
clock output pin is fixed to low (reset) during the low level period at the clock rising edge. If the reset start
timing is regarded as not important, the timing where the RESET signal is set from high to low is not so
consequence. However, when the reset is released this timing must become significant because the timing is
used to commence the 1/2 frequency divided clock. In this case, the setup time (T_rs) is also necessary.
See the timing chart for detail. (This chart shows the example of reset for 2T.)
The A/D converter can operate at FC (min.) = 120MSPS in this mode.
Table 2. Operating Mode Table
SELECT
VCC
GND
DMUX mode
Straight mode
120MSPS
100MSPS
Demultiplexed output
60Mbps
Straight output
100Mbps
The input clock is 1/2 frequency divided
and output. 60MHz
The input clock is inverted and output.
100MHz
Operating
mode
Maximum
conversion rate
Data output Clock output
Page 11
– 11 –
CXA3026Q
8bits
CLKOUT
DATA
8bits
CLKOUT
DATA
CLK
A
B
CLK
A
CXA3026Q
CXA3026Q
CLK
RESETN
CLK
RESETN
A
B
A
8bits
CLKOUT
DATA
8bits
CLKOUT
DATA
CLK
CXA3026Q
CXA3026Q
A
B
CLK
RESETN
CLK
RESETN
CLK
RESET signal
RESET signal
(Reset period)
(Reset period)
When the RESET signal is not used.
When the RESET signal is used.
2. Straight mode (See Application Circuits 1-(4), (5) and (6).)
Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the
clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter
as the system clock.
The A/D converter can operate at Fc (min.) = 100MSPS in this mode.
Digital input level and supply voltage settings
The logic input level for the CXA3026Q supports ECL, PECL and TTL levels.
The power supplies (DVEE3, DGND3) for the logic input block must be set to match the logic input (CLK and
RESET signals) level.
Digital input level
ECL
PECL
TTL
–5V
0V
0V
0V
+5V
+5V
±5V
+5V
+5V
(1) (4)
(2) (5)
(3) (6)
DVEE3 DGND3 Supply voltage Application circuits
Table 3. Logic Input Level and Power Supply Settings
A
A
Page 12
– 12 –
CXA3026Q
Application Circuit 1
(1) DMUX ECL input
+5V(D)
DG
–5V(D)
AG
DG
+5V(A)
4V
+5V(D)
DG
8-bit Digital Data
Latch
8-bit Digital Data
Latch
P1D0 to P1D7
8-bit Digital Data
P2D0 to P2D7
8-bit Digital Data
ECL RESET signal
ECL-CLK
DG
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
1
DG
+5V(D)
2V
+5V(A)
2
AGAGAGAG
(2) DMUX PECL input
+5V(D)
DG
+5V(D)
DG
8-bit Digital Data
Latch
8-bit Digital Data
Latch
P1D0 to P1D7
8-bit Digital Data
P2D0 to P2D7
8-bit Digital Data
PECL-CLK
DG
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
1
DG
+5V(D)
2
+5V(D)
AG
DG
+5V(A)
4V
2V
+5V(A)
AGAGAGAG
PECL RESET signal
12
(3) DMUX TTL input
+5V(D)
DG
AG
AG
+5V(A)
4V
+5V(D)
DG
8-bit Digital Data
Latch
8-bit Digital Data
Latch
P1D0 to P1D7
8-bit Digital Data
P2D0 to P2D7
8-bit Digital Data
TTL RESET signal
TTL-CLK
DG
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
1
DG
+5V(D)
2V
AG
+5V(A)
2
+5V(D)
DG
AGAG
12
Page 13
– 13 –
CXA3026Q
(4) Straight ECL input
+5V(D)
DG
+5V(D)
DG
8-bit Digital Data
Latch
P1D0 to P1D7
8-bit Digital Data
ECL-CLK
DG
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
46
47
48
1
DG
+5V(D)
2
ECL → TTL
DG
45
AGAG
+5V(A)
4V
2V
AG
+5V(A) –5V(D)
DG
AGAG
(5) Straight PECL input
+5V(D)
DG
+5V(D)
DG
8-bit Digital Data
Latch
P1D0 to P1D7
8-bit Digital Data
PECL-CLK
DG
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
46
47
48
1
DG
+5V(D)
2
PECL → TTL
DG
45
AGAG
+5V(A)
4V
2V
AG
+5V(A)
+5V(D)
DG
AGAG
(6) Straight TTL input
+5V(D)
DG
+5V(D)
DG
8-bit Digital Data
Latch
P1D0 to P1D7
8-bit Digital Data
TTL-CLK
DG
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
46
47
48
1
DG
+5V(D)
2
DG
45
AGAG
+5V(A)
4V
2V
AG
+5V(A)
+5V(D)
DG
AGAG
Page 14
– 14 –
CXA3026Q
Application Circuit 2 Straight Mode TTL I/O (When a single power supply is used)
CLK/E
N.C.
CLK/T
N.C.
N.C.
DV
CC2
DGND2
P2D0
P2D1
P2D2
P2D3
CLKN/E
RESETN/E
SELECT
RESETN/T
INV
CLKOUT
DV
CC2
DGND2
P1D7
P1D6
P1D5
P1D4
RESET/E
DV
EE
3
V
RM
1
AGND
AV
CC
V
IN
V
RM
2
AV
CC
V
RM
3
AGND
V
RT
DGND3
V
RB
P2D4
P2D7
P2D6
DV
CC
1
DV
CC
2
DGND2
P1D0
P1D1
P1D2
P1D3
P2D5
DGND1
Analog
input
AG
+5V (A)
2V
4V
TTL CLK
(LSB) P2D0
P2D1
P2D2
P2D3
P2D4
P2D5
P2D6
(MSB) P2D7
(LSB) P1D0
(MSB) P1D7
P1D1
P1D2
P1D3
P1D4
P1D5
P1D6
short
10µF
10µF
1µF
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
1
AG
AG
DG
+5V
(D)
AG
AG
24
short
Short the analog system and digital system at one point immediately
under the A/D converter. See the Notes on Operation.
is the chip capacitor of 0.1µF.
1µF
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Page 15
– 15 –
CXA3026Q
DMUX Mode Timing Chart (Select = VCC)
CLK
V
IN
T
Tpw0Tpw1
N + 3
N + 4
N + 2
N + 5
N + 6
Tds
N + 1
N + 7
N
N – 1
4.5ns (typ.)
2.0V
0.8V
N
2.0V
0.8V
Tdo1
≈T ≈T
P2D0 to D7
P1D0 to D7
T + 1ns (typ.)
N + 1 N + 3
N + 2
CLK OUT
RESET signal
T_rs
T_rhT_rsT_rh
2.0V
0.8V
2.0V
0.8V
2.0V
0.8V
8ns (max.)
Td_clk
4.5ns (min.)
(Reset period)
Tdo2; 8ns (typ.)
6.5ns (min.)
10ns (max.)
Td_clk; 7ns (typ.)
8ns (max.)
4.5ns (min.)
Page 16
– 16 –
CXA3026Q
Straight Mode Timing Chart (Select = GND)
Tds
T
Tpw1
N + 1
N – 1
N
N + 2
N + 3
CLK
V
IN
Tpw0
4.5ns (typ.)
N – 3 N – 1
P2D0 to D7
P1D0 to D7 NN – 2N – 4
N – 4 N – 2 N – 1N – 3N – 5
2.0V
0.8V
2.0V
0.8V
CLK OUT
(CLK is inverted and output.)
RESET signal
2.0V
0.8V
Td_clk; 7ns (typ.)
Tdo2; 8ns (typ.)
6.5ns (min.)
10ns (max.)
4.5ns (min.)
8ns (max.)
Page 17
– 17 –
CXA3026Q
Timing of A/D Converter and Peripheral Circuit
In the maximum clock rate of the DEMUX Mode, the timing of 3 channels of ADC CLK OUT in same phase is
described in detail as below.
For example, the CLK OUT from one of the ADC is used as the data latch clock. The clock delay and data
delay are showed in the following specification, i.e.
Td_clk 4.5ns (min.) to 8.0ns (max.)
Tdo2 6.5ns (min.) to 10ns (max.)
These values are considered in all the temperature change and power supply variation. When the maximum
clock rate 120MSPS is used, the set-up time (ts) is seemed to be very small from above specifications. But the
3 channels of ADC are in the same circuit board, so that the DATA OUT delay and CLK OUT delay will be
changed in same trend at the same condition of the temperature change and power supply variation. As a
result, 0.5ns of the delay will be faster, when the highest temperature and highest power supply is used. Also,
0.5ns of the delay will be later, when the lowest temperature and lowest power supply is used. These delay
can be omitted in this case.
When Ta = 25°C, VCC = +5V, the clock delay and data delay are
Td_clk 5.0ns (min.) to 7.5ns (max.)
Tdo2 7.0ns (min.) to 9.5ns (max.)
The timing of the DATA OUT and CLK OUT with above delay variation is showed in below. Consequently, the
set-up time for the data latching can be obtained as ts (min.) = 3.5ns. The output delay change of the DATA OUT
and CLK OUT due to the temperature change and the power supply variation should have the same trend of
the delay change, the minimum ts = 3.5ns can be guaranteed at any temperature change and power supply
variation.
Analog input R
Analog input G
Analog input B
CLK
RESET
8bit
8bit
8bit
8bit
8bit
8bit
P1D/out
P2D/out
CLK OUT
Vin
CLK
RESET
CXA3026Q
P1D/out
P2D/out
CLK OUT
Vin
CLK
RESET
CXA3026Q
P1D/out
P2D/out
CLK OUT
Vin
CLK
RESET
CXA3026Q
Gate Array
Latch
CLK
8ns
( = 1/120MSPS)
th-reset
RESET signal
Td_clk (min.)
5.0ns
<4.5ns>
Td_clk (max.)
7.5ns
<8.0ns>
CLK OUT
Tdo2 (min.)
9.5ns
<10ns>
7.0ns
<6.5ns>
th (min.)
7.5ns
P1D/out
P2D/out
16ns
Tdo2 (min.)
ts (min.)
3.5ns
Note: In the timing chart, the values in the brackets < > are included all the temperature change and the
power supply variation.
Page 18
– 18 –
CXA3026Q
Notes on Operation
• The CXA3026Q is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input.
Characteristic impedance should be properly matched to ensure optimum performance during high-speed
operation.
• The power supply and grounding have a profound influence on converter performance. The power supply
and grounding method are particularly important during high-speed operation. General points for caution are
as follows.
— The ground pattern should be as large as possible. It is recommended to make the power supply and
ground patterns wider at an inner layer using a multi-layer board.
— To prevent interference between AGND and DGND and between AVcc and DVcc, make sure the
respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVcc
and DVcc lines at one point each via a ferrite-bead filter Shorting the AGND and DGND patterns in one
place immediately under the A/D converter improves A/D converter performance.
— Ground the power supply pins (AVcc, DVcc1, DVcc2, DVEE3) as close to each pin as possible with a
0.1µF or larger ceramic chip capacitor.
(Connect the AVcc pin to the AGND pattern and the DVcc1, DVcc2 and DVEE3 pins to the DGND pattern.)
— The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring
capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output
waveform since the original output slew rate is quite fast.
• The analog input pin VIN has an input capacitance of approximately 21pF. To drive the A/D converter with
proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance
or parasitic inductance by using a large capacity drive circuit. keeping wiring as short as possible, and using
chip parts for resistors and capacitors, etc.
• The VRT and VRB pins must have adequate by-pass to protect them from high-frequency noise. By-pass them
to AGND with approximately 1µF tantal capacitor and, 0.1µF chip capacitor as short as possible.
• If the CLK/E pin is not used, by-pass this pin to DGND with an approximately 0.1µF capacitor. At this time,
approximately DGND3 – 1.2V voltage is generated. However, this is not recommended for use as threshold
voltage VBB as it is too weak.
• When the digital input level is ECL or PECL level,
∗∗∗
/E pins should be used and
∗∗∗
/T pins left open. When
the digital input level is TTL,
∗∗∗
/T pins should be used and
∗∗∗
/E pins left open.
Page 19
– 19 –
CXA3026Q
Current consumption vs.
Ambient temperature characteristics
Ta – Ambient temperature [°C]
–25
130
25 75
Current consumption [mA]
140
150
160
170
Current consumption vs.
Conversion rate characteristics response
Fc – Conversion rate [MSPS]
0
130
60
Current consumption [mA]
140
150
160
170
120
DMUX mode
CL = 5pF
fin = – 1kHz
fCLK
4
Analog input current vs.
Analog input voltage characteristics
Analog input voltage [V]
2 3 4
Analog input current [µA]
100
200
0
Reference current vs.
Ambient temperature characteristics
Ta – Ambient temperature [°C]
–25
10
25 75
Reference current [mA]
15
20
V
RT = 4V
VRB = 2V
Example of Representative Characteristics
Page 20
– 20 –
CXA3026Q
SNR vs. Input frequency response
Input frequency [MHz]
1
20
5 50
SNR [dB]
30
40
50
303 10
Error rate vs. Conversion rate characteristics
120 140 160
10
–6
10
–7
10
–8
10
–9
10
–10
Error > 16LSB
fin = – 1kHz
fCLK
4
Maximum conversion rate vs.
Ambient temperature characteristics
Ta – Ambient temperature [°C]
–25
130
25 75
Fc – Maximum conversion rate [MSPS]
150
170
fin = – 1kHz
fCLK
4
140
160
Fc = 120MSPS
Error > 16LSB
Error rate: 10–9 TPS
Error Rate [TPS]
Fc – Conversion rate [MSPS]
Page 21
– 21 –
CXA3026Q
CXA3026Q Evaluation Board
Description
The CXA3026Q Evaluation Board is a special board designed to maximize and facilitate the evaluation
performance of the CXA3026Q. After latching the CXA3026Q output data with a frequency divided clock, the
analog signal can be regenerated by a 10-bit high-speed D/A converter. The latched data can also be
extracted externally via a 24-pin cable connector.
Features
• Resolution: 8 bits
• Maximum conversion rate: 120MSPS (min.)
• Supply voltage: ±5.0V
• Dual analog input pins: DIR.IN: AC coupling input pin
AMP.IN: Operational amplifier input pin
• Clock frequency division: 1/1 to 1/16
Absolute Maximum Ratings
• Supply voltage VCC –0.5 to +7.0 V
VEE –7.0 to +0.5 V
+AMP –0.5 to +7.0 V
–AMP –7.0 to +0.5 V
Recommended Operating Conditions Min. Typ. Max.
• Supply voltage VCC +4.75 +5.0 +5.25 V
GND 0 V
VEE –5.50 –5.0 –4.75 V
+AMP +3 +5 +7 V
–AMP –7 –5 –3 V
| (+AMP) – (–AMP) | 9 10 11 V
• Analog input AMP. IN –0.75 0 +1.05 V
DIR. IN 1.5 2.0 2.2 Vp-p
• Clock input CLK. IN 0.8 1.0 1.2 Vp-p
Page 22
– 22 –
CXA3026Q
DIR IN
CON2
AGND
AGND
51Ω
AMP IN
CON1
AGND
AGND
82Ω
× (–2)
V
RB. R1
Vrb
VRT. R2
Vrt
OFFSET. R3
OFFSET
B
A
Vrt
Vrb S1
V
RT
VRB
VIN
AGND
130Ω
270Ω
1kΩ 390Ω
0.1µF
CLK IN
CON3
DGND
DGND
51Ω
VBB
CLK CLKOUT
S2
PECL/TTL
Counter
(PECL)
(PECL)
4
(TTL)
4
P1D0 to D7
P2D0 to D7
CXA3026Q
(TTL)
8
(TTL)
8
(TTL)
8
(ECL)
8
TTL/ECL
LATCH
DAC
(TTL)
8
(ECL)
8
TTL/ECL
LATCH
DAC
(TTL)
CON7 CON8
P1 side DATA P2 side DATA
(ECL)
TTL/ECL
FULL SCALE. R4
D/A OUT
(–1.0V)
FULL SCALE. R5
D/A OUT
(–1.0V)
SW1
SELECT
DMUX
Straight
SW2
A/D
INV
NORM
INV
SW3
D/A
INV
P1 side OUT
P2 side OUT
CON5
AGND
CON4
AGND
– AMP + AMP V
EE GND VCC
CON6
1kΩ
Block Diagram
Page 23
– 23 –
CXA3026Q
Pin Description and I/O Level
Pin No.
CON1
CON2
CON3
CON4
CON5
CON6
CON7
CON8
AMP. IN
DIR. IN
CLK. IN
P1 side OUT
P2 side OUT
VCC
GND
VEE
+AMP
–AMP
P1 side DATA
P2 side DATA
I
I
I
O
O
I
I
I
I
I
O
O
0.95Vp-p
2.0Vp-p
1.0Vp-p
0 to –1V
0 to –1V
+5.0V
0V
–5.0V
+5.0V
–5.0V
TTL
TTL
0.8A
–0.6A
40mA
–40mA
Doubles the analog input signal amplitude using the
operational amplifier. The input impedance is 50Ω.
AC coupling input. Suitable for sine waves and other
repeating waveforms. The input impedance is 50Ω.
The CXA3026Q operates at the PECL level clock
using the sine wave-to-PECL conversion circuit.
The input impedance is 50Ω.
Allows the D/A converted waveform of the
CXA3026Q port 1 side data to be observed.
The output impedance is 50Ω.
Allows the D/A converted waveform of the
CXA3026Q port 2 side data to be observed.
The output impedance is 50Ω.
The inside of the board is divided into analog and
digital systems.
+ side power supply for the operation amplifier.
– side power supply for the operation amplifier.
The CXA3026Q port 1 side data output is latched at
the frequency divided clock and then output.
The CXA3026Q port 2 side data output is latched at
the frequency divided clock and then output.
Symbol I/O
Standard
I/O level
Current Description
Board Adjustments and Settings
1. VRB.R1: CXA3026Q VRB voltage adjusting volume.
2. VRT.R2: CXA3026Q VRT voltage adjusting volume.
3. OFFSET.R3: Adjusting volume for matching the AMP.IN input and DIR.IN input signal ranges to the
CXA3026Q input range.
4. FULL SCALE.R4: Full-scale adjusting volume for the port 1 D/A output. (–1V: Typ.)
5. FULL SCALE.R5: Full-scale adjusting volume for the port 2 D/A output. (–1V: Typ.)
6. S1: Switching junction for the dual analog input pins.
Set as follows according to the input pins used.
7. S2: Setting junction for the clock frequency division ratio. The operating speed after
latching is determined by the frequency division ratio set here.
When set to CLK OUT, it operates according to the CXA3026Q clock output.
8. SW1 SELECT: CXA3026Q output mode selector switch.
9. SW2 A/D INV: CXA3026Q output polarity inversion switch.
10. SW3 D/A INV: D/A converter output polarity inversion switch.
Junction
Symbol
A B
AMP.IN
DIR.IN
OPEN
0.1µF
SHORT
10kΩ
Page 24
– 24 –
CXA3026Q
Notes on Board Operation
1. The factory settings for the CXA3026Q Evaluation Board are as follows.
When using the board in this condition, the input signals should be input at the amplitudes shown below.
(The frequency is set as desired.)
Analog input signal: CON1 (AMP.IN)
Clock input signal: CON3 (CLK.IN)
0V center, 800mVp-p or less
0V center, 1.0Vp-p
VRB.R1 = 1.5V
VRT.R2 = 3.0V
OFFSET.R3 = 2.25V
FULL SCALE.R4 = –1V
FULL SCALE.R5 = –1V
S1 A
...
OPEN, B
...
SHORT
S2 8
...
SHORT (1/8 frequency division)
2. When the analog signal is input from the CON1 (AMP.IN) pin, IC2:CLC404 limits the input dynamic range
of the A/D converter's analog input signal according to the +AMP and –AMP supply voltages. The power
supply for the operational amplifier can also be shifted to +AMP = +7.0V and –AMP = –3.0V to allow use
with a wider input dynamic range.
3. When the analog input signal is a sine wave or other repeating waveform, the signal can be input from the
CON2 (DIR.IN) pin with AC coupling. In these cases, the input dynamic range is not limited by the +AMP
and –AMP supply voltages, but the VRT level may be limited by IC3:NJM3403A. Therefore, the power
supply for the operational amplifier should be shifted in the same manner as in 2. above.
4. In the evaluation board of the CXA3026Q, CLC404 (Comlinear) is employed for IC2 to drive the analog
input signal. Though, CLC505 (Comlinear) can also be used instead of CLC404, there should be a little
change in the peripheral circuit in this case.
Page 25
– 25 –
CXA3026Q
CXA3026Q Evaluation Board Timing Chart
N
N + 1
N + 2
N + 3
0V
0V
2Vp-p
1Vp-p
Approximately 6.0ns
Approximately 9.0ns
0 to –1V
N – 6
N – 6
N – 4
N – 2
N – 2N – 4
N – 4 N – 3 N – 2 N – 1
(PECL)
(TTL)
(TTL)
(TTL)
(Analog regeneration waveform)
CON4
P1 side OUT
CXA3026Q
P1 side DATA
CXA3026Q
CLK
CON7
P1 side DATA
CLK
CON3
CLK IN
CON2
DIR IN
Operating Conditions CXA3026Q operating mode
Analog input
S2 setting
: Straight mode
: DIR IN pin input
: 1/2 frequency divided clock
CON7
P1 side DATA
DATA
Page 26
– 26 –
CXA3026Q
Circuit Diagram
DGND
C20
0.1µF
C11
1µF
C23
0.1µF
C25
0.1µF
AGND
AV
CC
C22
0.1µF
AGND
C26
0.1µF
C24
0.1µF
C21
0.1µF
C12
1µF
DV
CC
DGND
IC3B
NJM3403A
7
6
5
AGND
R18
51
R17
43
S1
A
B
DIR IN
CON2
IC2
CLC404
6
2
3
AGND
IC3C
NJM3403A
8
10
9
C19
0.1µF
C10
1µF
AGND +AMP
R16
270
AGND
AGND
IC3A
NJM3403A
1
2
3
C18
0.1µF
C9
1µF
AGND +AMP
C16
0.1µF
C7
1µF
AGND –AMP
C17
0.1µF
C8
1µF
AGND –AMP
R12
390k
R11
200k
R15
270
R14
130
AMP IN
CON1
R13
82
R10
22k
R9
7.5k
R3
10k
R1
2k
R2
1k
R7
510
R8
510
AVCC
R6
51
AGND
D1
TL431CP
11
4
4
7
C27
0.1µF
DVCC
R30
82
C30
0.1µF
DGND
DGND
R2882R29
82
R25
130
R26
130
R27
130
R22
1k
IC4B
10H116 (PECL)
6
10
9
7
IC4A
10H116 (PECL)
2
5
4
3
IC4C
10H116 (PECL)
14
13
12
15
DGND
CLK IN
CON3
C15
0.1µ
R201kR21
390
R19
51
11
IC4D
10H116 (PECL)
DGND
R24
130
R23
82
DVCC
DVCC
DGND
DVCC
C28
0.1µF
DGND
SW2
SW1
D/A INV
A/D INV
SELECT
DVCC
C29
0.1µF
–AMP +AMP AVEE DVEE AGND DGND AVCC DVCC
VCCGNDVEE–AMP +AMP
C6
33µF
C1
33µF
C2
33µF
L1 L2 L3 L4 L5 L6
C3
33µFC433µF
C5
33µF
C33 0.1µF
DGND
DGND
DVCC
C34 0.1µF
2
3
4
5
6
7
9
11
12
13
14
15
CLK
S1
D0
S2
D1
D2
D3
Q0
Q1
Q2
Q3
Cout
IC5
10H136 (PECL)
SW3
CON6
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
36
35
34
31
32
33
40
39
38
37
4142
43
44
45
46
47
48
2
3
4
5
6
7
8
9
10
11
12
1
CLK/E
N.C.
N.C.
N.C.
DV
CC2
DGND2
P2D0
P2D1
P2D2
P2D3
CLKN/E
CLK/T
RESETN/E
SELECT
INV
CLKOUT
DV
CC
2
DGND2
P1D7
P1D6
P1D5
P1D4
RESET/E
RESETN/T
P1D3
DV
CC2
DGND2
DGND1
DV
CC1
P1D2
P1D1
P1D0
P2D7
P2D6
P2D5
P2D4
IC1
CXA3026Q
DV
EE3
V
RB
AGND
V
RM1
AV
CC
AVCC
VRM3
AGND
V
RT
DGND3
V
IN
VRM2
P1D0
P1D1
P1D2
P1D3
P1D4
P1D5
P1D6
P1D7
CLKOUT
D/A INV
P2D0
P2D1
P2D2
P2D3
P2D4
P2D5
P2D6
P2D7
1/16
1/8
1/4
1/2
CLKN
CLK
DGND
AGND
AGND
Page 27
– 27 –
CXA3026Q
R46
620
C32
0.1µF
DGND
DGND
DGND
DVCC
R31 82 R34 130
R32 82 R35 130
R33 82 R36 130
DGND
13
14
16
17
18
19
12
2
3
4
7
8
9
11
1
IN8 OUT8
20
10
IN7 OUT7
IN6 OUT6
IN5 OUT5
IN4 OUT4
IN3 OUT3
IN2 OUT2
IN1 OUT1
S
DGND
S2
1/1
1/2
1/4
1/8
1/16
CLKOUT
13
14
15
16
17
19
20
21
22
23
24
2
3
4
8
9
10
11
12
1
D0
D1
D2
D3
Q0
Q1
Q2
Q3
D4
D5
D0N
D1N
D2N
D3N
D4N
D5N
Q4
Q5
13
14
15
16
17
18
19
2
3
4
5
6
7
8
9
11
12
1
1D 1Q
2D 2Q
3D 3Q
4D 4Q
5D 5Q
6D 6Q
7D 7Q
8D 8Q
OC
CLK
2
4
7
Y1
10
B
5
6
15
13
14
12
3
1
A1 Y1
Y2
Y2
Y3
Y3
Y4
Y4
A2
A3
A4
R50
620
DVEE
DVEE
DGND
C46
0.1µF
R49
620
C45
0.1µF
DV
EE
DGND
R38
82
R37
82
R40
130
R39
130
C54
0.1µFR52k
R44
1k
R45
270
AGND
D3
TL431CP
AGND
AVEE
C55
0.1µF
C14
1µF
C56
0.1µF
DGND
P2 side OUT
CON5
DVEE
C51
0.1µFR42k
R42
1k
R43
270
AGND
D2
TL431CP
AGND
AVEE
C52
0.1µF
C13
1µF
C53
0.1µF
DGND
P1 side OUT
CON4
DVEE
13
14
16
17
18
19
12
2
3
4
7
8
9
11
1
AGND
20
10
VREF
AV
EE
NC
OUT
DGND
INV
21
22
23
24
25
26
27
28
5
6
15
AGND
NC
NC
NC
NC
NC
DV
EE
C50
0.1µF
DGND
R41
620
DVEE
IC10
MB767
IC11
10H124
13
14
16
17
18
19
12
2
3
4
7
8
9
11
1
AGND
20
10
MSB
VREFD2
AV
EED3
NCD4
OUT
D5
DGND
D6
INV
D7
21
22
23
24
25
26
27
28
5
6
15
AGND
NC
NC
NC
NC
NC
DV
EE
D8
D9
CLKN
LSB
NC
NC
CLK
IC12
CX20201-1
IC13
CX20201-1
IC7
74AS574
IC8
100390
OE
V
BB
CLKOUT
D/A INV
P2D0
P2D1
P2D2
P2D3
P2D4
P2D5
P2D6
P2D7
1/16
1/8
1/4
1/2
CLKN
CLK
1 2
IC14
74ALS34
DGND
13
14
15
16
17
18
19
2
3
4
5
6
7
8
9
11
12
1
1D 1Q
2D 2Q
3D 3Q
4D 4Q
5D 5Q
6D 6Q
7D 7Q
8D 8Q
OC
CLK
IC6
74AS574
P1D0
P1D1
P1D2
P1D3
P1D4
P1D5
P1D6
P1D7
P1D0
P1D1
P1D2
P1D3
P1D4
P1D5
P1D6
P1D7
CON8
P2 side DATA
C39
0.1µF
DGND
DVCC
1
2
25
26
IC15
74ALS34
IC16
74ALS34
10
8
6
4
2
12
10
8
11
9
5
3
1
13
11
9
P2D0
P2D1
P2D2
P2D3
P2D4
P2D5
P2D6
P2D7
P2D0
P2D1
P2D2
P2D3
P2D4
P2D5
P2D6
P2D7
13
14
16
17
18
19
12
2
3
4
7
8
9
11
1
IN8 OUT8
20
10
IN7 OUT7
IN6 OUT6
IN5 OUT5
IN4 OUT4
IN3 OUT3
IN2 OUT2
IN1 OUT1
S
R48
620
DVEE
DVEE
C44
0.1µF
R47
620
C43
0.1µF
DGND
IC9
MB767
CON7
P1 side DATA
C35
0.1µF
DGND
DVccDGND
1
2
25
26
IC14
74ALS34
IC15
74ALS34
6
4
2
12
10
8
6
4
5
3
1
13
11
9
5
3
P1D0
P1D1
P1D2
P1D3
P1D4
P1D5
P1D6
P1D7
AGND
AGND
11
MSB
D2
D3
D4
D5
D6
D7
D8
D9
CLKN
LSB
NC
NC
CLK
Page 28
– 28 –
CXA3026Q
Component List
No. Product name Function
IC1 CXA3026Q 8-bit A/D converter
IC2 CLC404AJE OP-AMP
IC3 NJM3403AM OP-AMP
IC4 MC10H116L ECL Buffer
IC5 MC10H136L ECL Countor
IC6, 7 74AS574N TTL Latch
IC8 100390 PECL → TTL conversion
IC9, 10 MB767P TTL → ECL conversion
IC11 MC10H124L TTL → ECL conversion
IC12, 13 CXA20201A-1 10-bit D/A converter
IC14 to 16 74ALS34 TTL Buffer
D1 to 3 TL431CP Shunt regulator
SW1 to 3 ATE1D-2F3-10 Toggle switch
S1, 2 JX-1 Short pin
CON1 to 5 01K0315 BNC connector
CON6 TJ-563 Power supply connector
CON7, 8 (FAP-2601-1202) Flat cable connector
L1 to 6 ZBF503D-00 Ferrite-bead filter
C1 to 6 Tantal capacitor 33µF
C7 to 12 Tantal capacitor 1µF
C15 Ceramic capacitor 0.1µF
All parts other than those listed above
Chip capacitor 0.1µF
No. Product name Function
R2 RJ-5W-1K 1kΩ volume resistor
R1, 4, 5 RJ-5W-2K 2kΩ volume resistor
R3 RJ-5W-10K 10kΩ volume resistor
R46 to 50 RGLD4X621J 620Ω network resistor
R6, 18, 19 FRD-25SR (0.25W) 51Ω
R7.8 FRD-25SR (0.25W) 510Ω
R9 FRD-25SR (0.25W) 7.5kΩ
R10 FRD-25SR (0.25W) 22kΩ
R11 FRD-25SR (0.25W) 200kΩ
R12 FRD-25SR (0.25W) 390kΩ
R13, 23, 28 to 33, 37, 38 FRD-25SR (0.25W) 82Ω
R14, 24 to 27, 34 to 36, 39, 40 FRD-25SR (0.25W) 130Ω
R15, 16, 43, 45 FRD-25SR (0.25W) 270Ω
R17 FRD-25SR (0.25W) 43Ω
R20, 22, 42, 44 FRD-25SR (0.25W) 1kΩ
R21 FRD-25SR (0.25W) 390Ω
R41 FRD-25SR (0.25W) 620Ω
∗
CON7 and 8 are not mounted when boards are shipped. (Manufacturer: YAMAICHI Electronics Co., Ltd.)
Component side silk diagram
74ALS34
74ALS34
74ALS34
CXA3026Q/AQ
CXA3026Q/AQ EVALUATION BOARD
Page 29
– 29 –
CXA3026Q
Component side pattern diagram
Solder side pattern diagram
Page 30
– 30 –
CXA3026Q
Package Outline Unit: mm
SONY CODE
EIAJ CODE
JEDEC CODE
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER / PALLADIUM
PLATING
COPPER / 42 ALLOY
48PIN QFP (PLASTIC)
15.3 ± 0.4
12.0 – 0.1
+ 0.4
0.8 0.3 – 0.1
+ 0.15
± 0.12
13
24
2536
37
48
1 12
2.2 – 0.15
+ 0.35
0.9 ± 0.2
0.1 – 0.1
+ 0.2
13.5
0.15
0.15 – 0.05
+ 0.1
QFP-48P-L04
∗QFP048-P-1212-B
0.7g
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
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