Datasheet CXA2542AR Datasheet (Sony)

Description

The CXA2542AR is a bipolar IC developed for CD

player RF signal processing and servo control.

Features

• Automatic focus bias adjustment circuit

• Automatic tracking balance and gain adjustment

circuits

• RF level control circuit

• Interruption countermeasure circuit

• Anti-shock circuit

• Defect detection and prevention circuits

• RF I-V amplifier, RF amplifier

• APC circuit

• Focus and tracking error amplifier

• Focus, tracking and sled servo control circuits

• Focus OK circuit

• Mirror detection circuit

• Single power supply and dual power supplies

Applications

CD players

Structure

Bipolar silicon monolithic IC

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VCC 12 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation

PD 1400 mW

Recommended Operating Conditions

Operating supply voltage VCC – VEE 3.0 to 3.6 V

4.5 to 5.5 V

– 1 –

CXA2542AR

E98743-PS

RF Signal Processing Servo Amplifier for CD Player

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

48 pin LQFP (Plastic)

– 2 –

CXA2542AR

Block Diagram

PS1-4TM1-7TG1-2FS1-4IFB1-6 BAL1-4 TOG1-4

DFCTO

FE AMP

FO. BIAS WINDOW COMP.

TGFL

TRK. GAIN WINDOW COMP.

F IV AMP

E IV AMP

VEE

VCC

TG1

TM1

DFCT

TRACKING PHASE COMPENSATION

IIL DATA REGISTER INPUT SHIFT REGISTER ADDRESS DECODER SENS SELECTOR OUTPUT DECODER

VEE

E-F BALANCE WINDOW COMP.

E

F

FEI

FDFCT

FLB

FE_O

FE_M

TA_M

TG2

TGU

SRCH

FGD

FSET

LD

RFTC

RF_M

RF_O

RF_I

CB

CC1

FOK

CC2

CP

PD1

PD

SL_P

SL_O

ISET

V

CC

CLK

DATA

XRST

SL_M

C. OUT

XLT

SENS1

PD2 IV AMP

PD1 IV AMP

VCC

VEE

APC

VEE

LASER POWER CONTROL

RF SUMMING AMP

VCC

VEE

LEVEL S

FZC

TZC

ATSC

BALL

BALH

TGL

TGH

FOL

FOH

LDON

LPCL

LPC

TGFL

VEE

VCC

MIRR

DFCT2

VEE

VCC

ISET

VCC

VEE

VCC

TM5

TM6

VEE

VCC

TM3

TM4

FSET

TG2

FOCUS PHASE COMPENSATION

TM7

VEE

VCC

FS1

FS2

DFCT

FS4

IIL

↓

TTL

42

44

45

46

48

2

3

4

6

7

8

9

10

11

12

1

13

27

28

29

30

39

38

36

35

34

31

32

33

14

15

16

17

18

19

20

21

22

23

24

25

26

TM2

VCC

FZC COMP.

TZC COMP.

ATSC WINDOW COMP.

MIRR

FOK

BAL1

BAL2

BAL3

BAL4

IFB1

VEE

VCC

IFB6

IFB5

IFB4

IFB3

IFB2

TOG1

TOG2

TOG3

TOG4

37

5

TA_O

SENS2

ATSC

LPFI

TEO

VC

TDFCT

TZC

FEO

FZC

PD2

47

40

41

43

IIL

↓

TTL

↓

IIL

VCC

VEE

VCC

VEE

VCC

VEE

CC1

XDFCT1

INT

– 3 –

CXA2542AR

Pin Description

Pin No.

Symbol

I/O

Equivalent circuit

Description

1

FEI

I

2

FDFCT

I

Focus error input.

Connects the capacitor for defect time constant.

3

FGD

I

Ground this pin through a capacitor for cutting the focus servo highfrequency gain.

4

FLB

I

External time constant setting pin for boosting the focus servo lowfrequency.

5

FE_O

O

12

TA_O

O

15

SL_O

O

Focus drive output.

Tracking drive output.

Sled drive output.

6

FE_M

I

Focus amplifier inverted input.

147

50k

90k

2µ

6

250µ

5 12 15

147

100k

147

2

3µ

1

147

130k

68k

4µ

40k

470k

330k

3

4

7

SRCH

I

External time constant setting pin for generating the focus search waveform.

147

50k

11µ

20k

7

– 4 –

CXA2542AR

8

TGU

I

External time constant setting pin for switching the tracking high-frequency gain.

9

TG2

I

External time constant setting pin for switching the tracking high-frequency gain.

10

FSET

I

Peak frequency setting pin for focus and tracking phase compensation amplifier.

11

TA_M

I

Tracking amplifier inverted input.

13

SL_P

I

14

SL_M

I

Sled amplifier non-inverted input.

Sled amplifier inverted input.

147

2µ

13

147

100k

11µ

11

147k

15k 15k

10

20k

110k

82k

147

8

423k

470k

9

16

ISET

I

Connect the external resistor to set the current which determines the Focus search, Track jump, and Sled kick levels.

147

50µ

16

147

22µ

14

Pin No.

Symbol

I/O

Equivalent circuit

Description

– 5 –

CXA2542AR

18

CLK

I

20

DATA

I

17 VCC

I

Positive power supply.

Serial data input from CPU. (no pull-up resistance)

Serial data transfer clock input from CPU. (no pull-up resistance)

19

XLT

I

21

XRST

I

Latch input from CPU. (no pull-up resistance)

Reset input; resets at Low. (no pull-up resistance)

147

20µ

1k

18 20

147

20µ

4k

2.5p

19 21

22

C. OUT

O

23

SENS1

O

24 SENS2

O

Track number count signal output.

Outputs FZC, DFCT1, TZC, BALH, TGH, FOH, ATSC, and others according to the command from CPU.

Outputs DFCT2, MIRR, BALL, TGL, FOL, and others according to the command from the CPU.

100k

147

20k

22 23 24

VCC

17

25

FOK

O

Focus OK comparator output.

147

20k

100k

40k

25

Pin No.

Symbol

I/O

Equivalent circuit

Description

– 6 –

CXA2542AR

26

CC2

I

28

CB

I

Input for the RF summing amplifier output with capacitance coupled.

Connects the defect bottom hold capacitor.

147

43k

39k

26

75k

147

28

7.6k

240k

29

CP

I

Connects the MIRR hold capacitor. MIRR comparator non-inverted input.

30

RF_I

I

31

RF_O O

32

RF_M

I

27

CC1

O

1.5k

100k

29

147

10k10k

30

31

32

147

27

Input for the RF summing amplifier output with capacitance coupled.

RF summing amplifier output. Eyepattern check point.

RF summing amplifier inverted input. The RF amplifier gain is determined by the resistance connected between this pin and RFO pin.

RF summing amplifier output. Used for the defect capacitance coupling.

33

RFTC

I

External time constant setting pin during RF level control.

147

50µ

10µ

50µ

33

Pin No.

Symbol

I/O

Equivalent circuit

Description

– 7 –

CXA2542AR

34

LD

O

APC amplifier output.

35

PD

I

APC amplifier input.

36 37

PD1 PD2

I I

RF I-V amplifier inverted input. Connect these pins to the photo diode A + C and B + D pins.

147

10k

8.65k

100µ

2k

8k

36 37

0.2p

147

8µ

20µ

55k

10k

35

1k

10k

34

38 39

F E

I I

F I-V and E I-V amplifier inverted input. Connect these pins to photo diodes F and E pins.

147

260k

12p

500

10µ

38 39

VEE

40

VEE

—

Negative power supply.

Pin No.

Symbol

I/O

Equivalent circuit

Description

– 8 –

CXA2542AR

43

ATSC

I

44

TZC

I

Window comparator input for ATSC detection.

Tracking zero-cross comparator input.

41

TEO

O

Tracking error amplifier output. E-F signal is output.

45

TDFCT

I

Connects the capacitor for defect time constant.

147

75k

10µ

44

147

1k

100k

1k

10µ 10µ

43

42

LPFI

I

Comparator input for balance adjustment. (Input from TEO through LPF)

147

7µ

42

147

32k 15k 3k15k

20k

150k

6.6k

147

100k

3µ

41

45

Pin No.

Symbol

I/O

Equivalent circuit

Description

– 9 –

CXA2542AR

46

VC

O

(VCC + VEE)/2 DC voltage output.

VC

50

120

46

15k

47

FZC

I

Focus zero-cross comparator input.

147

7µ

300k

6k

54k

47

48 FEO

O

Focus error amplifier output. Connected internally to the window comparator input for bias adjustment.

147

25p

174k

10µ

300µ

48

Pin No.

Symbol

I/O

Equivalent circuit

Description

– 10 –

CXA2542AR

TEST

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

Current consumption 1

Current consumption 2

Center amplifier output offset

Offset

Voltage gain

Max. output amplitude - High

Max. output amplitude - Low

Offset

Voltage gain 1

Voltage gain 2

Voltage gain difference

Max. output voltage – High

Max. output voltage – Low

BIAS0

BIAS1

BIAS2

BIAS3

BIAS4

BIAS5

BIAS6

19 (OFF)

10, 13

10

13

10

RST

39F

3BF

3BE

3BD

3BB

3B7

3AF

39F

17

40

—

36 37

36

37

36

17

40

46

31

48

1kHz I/O ratio

V2 = 0.2VDC

1FB6: ON

1kHz I/O ratio

V2 = 100mVDC

IFB1, 2, 3, 4, 5, 6: OFF

IFB1: ON, BIAS0: reference

IFB2: ON, BIAS0: reference Output gain difference with T15

IFB3: ON, BIAS0: reference Output gain difference with V17

IFB4: ON, BIAS0: reference Output gain difference with V18

IFB5: ON, BIAS0: reference Output gain difference with V19

IFB6: ON, BIAS0: reference Output gain difference with V20

12.0

–25.0

–100

–70

16.5

1.2

—

–120

15.6

–3

1

—

560

–29.0

5

18.5

–18.5

0

–13

19.5

1.4

–1.3

0

18.6

0

1.4

–1.3

718

–22.7

6

25.0

–12.0

100

70

22.5

—

–1.0

120

21.6

3

—

–1

1042

–16.5

7

mA

mV

dB

V

mV

dB

V

mV

dB

Item

SW conditions (ON switches)

SD

Input pin

Measurement conditions

Min. Typ. Max. Unit

Electrical Characteristics (VCC = 1.5V, VEE = 1.5V, Topr = 25°C)

RF amplifierFE amplifier

Measurement pin

– 11 –

CXA2542AR

FOH threshold value

FOL threshold value

Offset

GAIN UP (F)

GAIN UP (E)

Voltage gain F0

Voltage gain F1

Voltage gain F2

Voltage gain F3

Voltage gain F4

Voltage gain E0

Voltage gain E1

Voltage gain E2

Voltage gain E3

Voltage gain E4

Max. output voltage – High

Max. output voltage – Low

Output voltage 1

Output voltage 2

Output voltage 3

Output voltage 4

LD OFF

T21

T22

T23

T24

T25

T26

T27

T28

T29

T30

T31

T32

T33

T34

T35

T36

T37

T38

T39

T40

T41

T42

14

15

14

15

1

9

38 39

38

39

38

39

38

39

35

39F

34F 308

36F 308

34F

34E 30F

34D

34B

347 34F

30F

00

30E

30D

30B

307

34F 308

3C4

3C0

48

41

34

I

FB6: ON Pin 1 voltage when SENS1 (Pin 23) goes from High to Low

IFB6: ON Pin 1 voltage when SENS2 (Pin 24) goes from High to Low

TOG: OFF, BAL1, 2, 3: ON

V1 = 2 kHz, I/O ratio TOG: OFF, BAL1, 2, 3: ON

V1 = 2kHz, TOG: OFF I/O ratio

V1 = 2kHz, TOG1: ON Reference to F0

V1 = 2kHz, TOG2: ON Reference to F0

V1 = 2kHz, TOG3: ON Reference to F0

V1 = 2kHz, TOG4: ON Reference to F0

V1 = 2kHz, BAL: OFF I/O ratio

V1 = 2kHz, BAL1: ON Reference to E0

V1 = 2kHz, BAL2: ON Reference to E0

V1 = 2kHz, BAL3: ON Reference to E0

V1 = 2kHz, BAL4: ON Reference to E0

V1 = 1VDC, TOG: OFF, BAL1, 2, 3: ON

I1 = 364µA

I1 = 439µA

I1 = 515µA

0.8mA sink

I1 = 515µA, LD: OFF

5

–35

–25

7.2

1.2

–2.3

–3.9

–6.9

–11.1

–1.6

0.16

0.58

1.43

2.96

0.5

—

–900

–693

163

–200

1.1

20

–20

0

10.2

4.2

–1.8

–3.4

–6.4

–10.6

1.4

0.46

0.88

1.73

3.26

0.7

–0.8

–704

–293

613

132

1.3

35

–5

25

13.2

7.2

–1.3

–2.9

–5.9

–10.1

4.4

0.76

1.18

2.03

3.56

—

–0.5

–500

107

1063

500

—

mV

dB

V

mV

V

FE amplifierTE amplifierAPC

TEST Item

SW conditions (ON switches)

SD

Input pin

Measurement pin

Measurement conditions

Min. Typ. Max. Unit

– 12 –

CXA2542AR

T43

T44

T45

T46

T47

T48

T49

T50

T51

T52

T53

T54

T55

T56

T57

T58

T59

T60

T61

T62

T63

T64

50% limit

30% limit

–50% limit

–30% limit

DC voltage gain

FCS total gain

Feed through 1

FZC threshold value

Max. output voltage – High

Max. output voltage – Low

Search voltage (–)

Search voltage (+)

DC voltage gain

TRK total gain

Feed through 1

Max. output voltage – High

Max. output voltage – Low

Jump output voltage (–)

Jump output voltage (+)

ATSC threshold value (–)

ATSC threshold value (+)

TZC threshold value

8

10, 13

1

20

1

5, 17

18

3C7

3C5

3C7

3C5

08

—

00 08

00

08

02

03

25

—

20 25

2C

28

10

20

35 30

35 36 37

1

—

1

47

1

—

38

—

38

43

44

34

5

—

5

47

5

12

—

12

43

44

I1 = 273µA Output difference with LPC ON/OFF

I1 = 333µA Output difference with LPC ON/OFF

I1 = 742µA Output difference with LPC ON/OFF

I1 = 667µA Output difference with LPC ON/OFF

T9 + T47

I/O gain difference between SD = 00 and SD = 08

Pin 47 voltage when SENS1 (Pin 23) goes from Low to High

V1 = 200mVDC

V1 = –200mVDC

DC gain between TEO and TA_O

T26 + T55

I/O gain difference between SD = 20 and SD = 25.

V1 = –0.3VDC

V1 = 0.3VDC

Input voltage when TG2

(Pin 9) goes from Vcc/2 to Vcc

Input voltage when TG2 (Pin 9) goes from Vcc/2 to Vcc

Pin 44 voltage when SENS1 (Pin 23) is 0V

725

315

–1421

–1215

17.4

37.5

—

123

1

—

–721

399

11.4

16.8

—

1

—

–652

437

–25

7

–20

1330

915

–816

–615

20.9

39.5

—

150

1.3

–1.3

–581

539

14.6

18.8

—

1.3

–1.3

–512

577

–15

15

0

1935

1515

–211

–15

24.4

41.5

–30

177

—

–1

–441

679

17.8

20.8

–39

—

–1

–372

717

–7

25

20

mV

dB

mV

V

mV

dB

V

mV

RF level controllFocus servoTracking servo

TEST Item

SW conditions (ON switches)

SD

Input pin

Measurement conditions

Min. Typ. Max. Unit

Measurement pin

– 13 –

CXA2542AR

T65

T66

T67

T68

T69

T70

T71

T72

T73

T74

T75

T76

T77

T78

T79

T80

T81

T82

BAL COMP threshold value – High

BAL COMP threshold value – Low

GAIN COMP threshold value – High

GAIN COMP threshold value – Low

FOK threshold value

Voltage gain

Feed through

Max. output voltage – High

Max. output voltage – Low

Kick voltage 1

Kick voltage 2

Max. operating frequency 1

Min. input operating voltage 1

Max. input operating voltage 1

Min. operating frequency 1

Max. operating frequency 1

Min. input operating voltage 1

Max. input operating voltage 1

16

14

8

6, 7

6

8

10, 11, 12, 13

300

308 34F

—

25

20 25

25

20

10

42

38

30

13

—

30

36 37

42

41

25

15

24

23

Pin 42 voltage when SENS1 (Pin 23) goes from High to Low

Pin 42 voltage when SENS2 (Pin 24) goes from High to Low

Pin 41 voltage when SENS1 (Pin 23) goes from High to Low

Pin 41 voltage when SENS2 (Pin 24) goes from Low to High

Pin 30 voltage when Pin 25 is 0V

V1 = 100Hz, I/O ratio

I/O

gain difference between

SD = 20 and SD = 25.

V1 = 400mVDC

REV × 1

FWD × 1

Measures at SENS2 pin.

Measures at SENS1 pin.

5

–35

168

127

–560

50

—

1

—

–750

450

30

—

1.8

—

2.5

—

1.6

20

–20

193

145

–510

—

1.3

–1.3

–600

600

—

35

–5

218

163

–450

—

–34

—

–1

–450

750

—

0.3

—

1

—

0.5

—

mV

dB

V

mV

kHz

Vp-p

kHz

Vp-p

Tracking servoFOKSled servoMIRRORDEFECT

TEST Item

SW conditions (ON switches)

SD

Input pin

Measurement conditions

Min. Typ. Max. Unit

Measurement pin

– 14 –

CXA2542AR

GND

R19

10k

C4

0.1µ

S3

S2

R9

47k

C3

1000P

S1

C1 1000P

S19

S16

V2

AC

DC

I2

0.8mA

C5

1µ

R13

30k

S8

C7

0.01µ

C9

0.068µ

S7

R25 13k

S6

C11 47µ

R23

60k

R3

10k

V1

AC

DC

GND

C2 33µ

GND

S17GND

S18GND

GND

S20GND

GND

V

EE

GND

R1 390k

S15

R2 390k

S14

GND

GND GND

R11

13k

GND

R12

100k

S5

R15

10k

V

CC

R16

510k

V

CC

C8

0.01µ

R18

13k

GND

R17

100k

GND

R24 5.1k

GND

V

EE

R26 120k

VCC

GND

CLK

C10 33µ

XLT

DATA

XRST

VCC

R20 10k

VCC

R21 10k

VCC

R22 10k

VCC

GND

C6

0.01µ

GNDGND

R14

10k

R10

1M

V

EEVCC

R8

330

V

EEVCC

I1

0µA

GND

F

E

VEETEO

LPFI

ATSC

TZC

TDFCT

VC

SENS1

C. OUT

XRST

DATA

XLT

CLK

Vcc

ISET

SL_O

SL_M

SL_P

SENS2

FZC

13

14

15

16

17

18

19

20

21

22

23

24

39

38

37

41

42

45

46

47

40

44

43

FDFCT

FGD

FLB

FE_O

FE_M

SRCH

TGU

TG2

FSET

TA_M

TA_O

FEI

PD1

PD

LD

RF_M

RF_O

RF_I

CP

CB

CC1

FOK

RFTC

CC2

PD2

FEO

2

3

4

5

6

7

8

9

10

11

12

1

25

26

27

28

29

30

36

35

34

31

32

33

48

R5

240k

R6 240k

S11S12

R4

34k

R7

34k

S13

S10

S9

R26 100k

Electrical Characteristics Measurement Circuit

– 15 –

CXA2542AR

Application Circuit 1 (±2.5V power supply)

PD1

PD

LD

RF_M

RF_O

RF_I

CP

CB

CC1

FOK

RFTC

CC2

Vcc

MICRO COMPUTER DSP

15k

22µ

3.3µ

DRIVER

100k

0.015µ

60k

V

EE

VEE

100k

150k

0.047µ

0.1µ

F

E

V

EE

TEO

LPFI

ATSC

TZC

TDFCT

VC

82k

F

E

8.2k

SENS1

C. OUT

XRST

DATA

XLT

CLK

Vcc

ISET

SL_O

SL_M

SL_P

SENS2

47k

330k

470p

0.022µ

FZC

13

14

15

16

17

18

19

20

21

22

23

24

39

38

37

41

42

45

46

47

40

44

43

0.01µ

0.1µ

680k

510k

0.015µ

2200p

0.1µ

0.1µ 100k

4.7µ

DRIVER

0.033µ

Vcc

100k

DRIVER

10k

0.068µ

0.01µ

0.033µ

0.01µ

30k

Vcc

22

100µ

1µ

10µH

100

500

V

EE

Vcc

1k

3.3µ

A C

B D

PD

LD

1M

1µ

VEE VEE

FDFCT

FGD

FLB

FE_O

FE_M

SRCH

TGU

TG2

FSET

TA_M

TA_O

FEI

PD2

FEO

2

3

4

5

6

7

8

9

10

11

12

1

25

26

27

28

29

30

36

35

34

31

32

33

48

Application Circuit 2 (Single +5V power supply)

Vcc

MICRO COMPUTER DSP

15k

22µ

3.3µ

DRIVER

100k

0.015µ

60k

100k

150k

0.047µ

0.1µ

F

E

V

EE

TEO

LPFI

ATSC

TZC

TDFCT

VC

82k

F

E

8.2k

SENS1

C. OUT

XRST

DATA

XLT

CLK

Vcc

ISET

SL_O

SL_M SL_P

SENS2

47k

330k

470p

0.022µ

FZC

13

14

15

16

17

18

19

20

21

22

23

24

39

38

37

41

42

45

46

47

40

44

43

0.01µ

0.1µ

680k

510k

0.015µ

2200p

0.1µ

0.1µ 100k

4.7µ

DRIVER

0.033µ

Vcc

100k

DRIVER

10k

0.068µ

0.01µ

0.033µ

0.01µ

30k

Vcc

22

100µ

1µ

10µH

100

500

Vcc

1k

3.3µ

A C

B D

PD

LD

1M

1µ

FDFCT

FGD

FLB

FE_O

FE_M

SRCH

TGU

TG2

FSET

TA_M

TA_O

FEI

PD1

PD

LD

RF_M

RF_O

RF_I

CP

CB

CC1

FOK

RFTC

CC2

PD2

FEO

2

3

4

5

6

7

8

9

10

11

12

1

25

26

27

28

29

30

36

35

34

31

32

33

48

Vcc

10µ

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 16 –

CXA2542AR

Description of Functions

RF Amplifier

The photodiode currents input to the input pins (PD1 and PD2) are each I-V converted through a 58kΩ equivalent resistor by the PD I-V amplifiers. These signals are added by the RF summing amplifier, and the photodiode (A + B + C + D) current-voltage converted voltage is output to the RFO pin. An eye-pattern check can be performed at this pin.

The low frequency component of the RFO output voltage is

30k

VRFO = –

10k

(VA + VB – 2V3) + V3

= –3 {–58kΩ (iPD1 + iPD2) + V1 + V2 – 2V3} + V3, and

the setting is V1 = V2 = V3, then

VRFO = 174kΩ × (iPD1 + iPD2) + V3

1k

3.3µ

A

C

B

D

PD1

iPD1→

PD2

iPD2→

58k

VA

10k

VC

PD1 IV AMP

58k

VB

10k

VC

PD2 IV AMP

RF_M

RF_O

30k

RF SUMMING AMP

32

31

36

37

V1

V2

FOK DEFECT

V3

– 17 –

CXA2542AR

Focus Error Amplifier

FEO

FEI

FE_O

FE_M

PD2

PD1

SENS1

SENS2

R8

100k

VEE

20mV

FOCUS PHASE COMPENSATION

SENS SELECTOR

VH

VIN > VH L VIN < VH H

FOH

–20mV

VL

VIN > VL H VIN < VL L

FOL

VC

R11

100k

DRIVER

GND

C1

2200p

R9

10k

R10

10k

R1

16k

VC

R4

32k

R2

58k

VCC

R7

174k

VC

R5 32k

R3

58k

PD2 IV AMP

PD1 IV AMP

IFB6

×32

IFB5

×16

IFB4

×8

IFB3

×4

IFB2

×2

IFB1

×1

RESET : IFB1 to IFB6 ON

25mV/STEP

B + D

A + C

VIN

R6

174k

VA

VB

FE AMP

48

1

6

5

23

24

×32

37

36

V2

RF

V1

RF

The focus error amplifier calculates the difference between outputs VA and VB of the RF I-V amplifier, and outputs current-voltage converted voltage of the photodiode (A + C – B – D).

The FEO output voltage:

174kΩ

VFEO =

32kΩ

(VA – VB)

174kΩ

=

32kΩ

{(–58kΩ × iPD1) – (–58kΩ × iPD2)}

= 315.4kΩ (iPD2 – iPD1)

The focus error amplifier has a built-in bias adjustment circuit to enable software-based automatic adjustment. The focus bias adjustment is performed by turning the focus bias adjustment switches (IFB1 to IFB6) ON and OFF. The 6-bit focus bias adjustment switches are controlled with commands. IFB1 to IFB6 are all ON after a reset. The voltage is varied by approximately 25mV per step.

– 18 –

CXA2542AR

• Focus error amplifier offset adjustment (when adjusting the IC offset)

The offset adjustment is performed by comparing the FEO when the focus servo is OFF with the reference level. The FEO and reference level are compared by the window comparator, and the comparison results are output from SENS1 and SENS2. (ADDRESS

D11

001110D6) Adjust the offset so that SENS1 and SENS2 are both High. Set the reference level to the center ±20mV.

25mV < 40mV < 50mV

Reference level width

Variable voltage per step Variable voltage per 2 steps

• Focus bias fine adjustment

Fine adjustment is performed by turning the focus bias adjustment switches (IFB1 to IFB6) ON and OFF while monitoring a DSP jitter meter with the microcomputer. The 6-bit focus bias adjustment switches are controlled with commands.

– 19 –

CXA2542AR

The difference between E I-V amplifier output VE and F I-V amplifier output VF is taken and output from TEO.

The tracking error amplifier has built-in balance and gain adjustment circuits to enable software-based automatic adjustment. The balance adjustment is performed by varying the combined resistance value of the T-configured feedback resistance at the E I-V amplifier.

E I-V AMP feedback resistance = R1 + R4 +

F I-V AMP feedback resistance = R2 + R5 + = 403kΩ

Vary the combined resistance value of the E I-V amplifier's feedback resistance by using the balance adjustment switches (BAL1 to BAL4). The gain adjustment is performed by resistance dividing the TE AMP output by the gain adjustment switches (TOG1 to TOG4). The balance and gain adjustment switches are controlled with commands. Set the cut-off frequency of the external LPF between 10Hz and 100Hz.

Tracking Error Amplifier

LPFI

TEO

F

CLK

DATA

XRST

XLT

SENS1

SENS2

VIN > VH L VIN < VH H

BALH

VH

20mV

VC

VIN

–20mV

VC

VL

VIN > VL H VIN < VL L

BALL

VIN > VH L VIN < VH H

TGH

VH

200mV

VC

VIN

150mV

VC

VL

VIN > VL H VIN < VL L

TGL

SENS SELECTOR

COMAND

CONTROL

CPU

R23

100k

R24

150k

C3

0.01µC40.01µ

GND GND

VC

R21

6.6k

R20

15k

R19

32k

R17

20k

R22

3k

R18

15k

R16

96k

TE AMP

NORMAL R14 13k

R9

17k

GAIN UP

R8

17k

VC

R12

96k

R13 13k

V

NORMAL

TGFL

C2

12p

R2

260k

R5

13k

R3 26k

VC

C1

12p

R1

260k

R4

6.8k

VC

E

VF

VE

F I-V AMP

E I-V AMP

R7

110k

R10

56k

R11

27k

R15

13k

R6

75k

RE

VC

+

–

23

41

42

COMAND CONTROL

BAL1

BAL2

BAL3

BAL4

TOG4

TOG3

TOG2

TOG1

38

39

24

21 20

19 18

R1 × R4

RE

R2 × R5

R3

– 20 –

CXA2542AR

• Balance adjustment The balance adjustment is performed by passing the tracking error signal (TEO signal) through the external LPF, extracting the offset DC, and comparing it to the reference level. However, the TEO signal frequency distribution ranges form DC to 2kHz. Merely sending the signal through the LPF leaves lower frequency components, and the complete offset DC can not be extracted. To extract it, monitor the TEO signal frequency at all times, and perform adjustment only when a frequency that can lower a sufficient gain appears on the LPF. Use the C.OUT output to check this frequency. The offset DC and reference level are compared by the window comparator. The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS

D11

001100D6)

Adjust the balance so that the SENS1 and SENS2 pins are both High.

• Gain adjustment Gain adjustment is performed by passing the TEO signal through the HPF and comparing the AC component to the reference level. The AC component is generated by taking the difference between TE and the offset DC input to Pin 42. The AC component and reference level are compared by the window comparator. The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS

D11

001101D6)

The comparison signal is as follows.

SENS1 pin

BALH

SENS2 pin

BALL

H

L

H

L

H

VIN < VL < VH VL < VIN < VH VL < VH < VIN

VH: High level threshold value VIN: Window comparator input signal VL: Low level threshold value

SENS1 pin

TGH

H H

L

SENS2 pin

TGL

VH

VL VIN

(1) (2) (3)

The gain should be adjusted so that the SENS1 and SENS2 pins are as shown in status (2).

When the TEO signal level is low and TGH (SENS1 pin) does not go Low, the gain should be raised with the TGFL command for adjustment. If the adjustment does not bring the result of Low, check the pulse duty of TGL (SENS2 pin).

– 21 –

CXA2542AR

APC & Laser Power Control

LD

RFTC

RF_O

RF_I

PD

VEE

VCC

R8

10k

VEE

R5 55k

R10

56k

R12

56k

R11

10k

R4

10k

R6

1k

LDON

R14

12.5k

V

L

VREF

LPC ON/OFF

50%/30%

670mV

R9

41k

VC

R7

13k

VEE

RF

R13

1M

VEEVEE

C4 1µ

R1

22

C2

100µ

C1 1µ

VEE

R3

100

R2

500

130mV

GND

LD PD

L1

10µH

VCC

C3

0.01µ

30

31

33

34

35

0.684V for 4.5V or more

0.57V for 3.6V or less

FOK

MIRR

• APC

When the laser diode is driven by a constant current, the optical power output has extremely large negative temperature characteristics. The APC circuit is used to maintain the optical power output at a constant level. The laser diode current is controlled according to the monitor photodiode output.

• Laser power control

The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the RF level fluctuations. The RF_O and RF_I levels are compared and the larger of the two is smoothed by the RFTC's external CR. This signal is then compared with the reference level. The laser power is controlled by attaching an offset to VL according to the results of comparison with the reference level. The reference level is set to 0.57V for the power supply of 3.6V or less and to 0.684V for 4.5V or more. LPC ON/OFF and LD ON/OFF control is performed with commands. The laser power control limit can also be switched between ±50% and ±17% with commands.

LPC OFF

ON ON

— ±50% ±30%

Approximately 1.27V Approximately 1.27V ± 625mV Approximately 1.27V ± 375mV

LPCL VL variable range

– 22 –

CXA2542AR

Center Voltage Generation Circuit

(The figure below shows a single voltage application; Connect to GND for dual power supplies.) The maximum current is approximately ±3mA. The output impedance is approximately 50Ω.

50

VCC

VEE

VC

Connected internally to the V

EE pin.

30k

VCC

GND

VC

46

– 23 –

CXA2542AR

Focus Servo

6k

54k

FE

2200p

10k

FEO

FEI

100k

DFCT

FS4

Focus phase Compensation

68k

100k

FE_O

FOCUS COIL

FE_M

100k

ISET

60k

11µ 22µ

FS2

FS1

50k

4.7µ

0.015µ

510k

0.1µ

FSET

FLB

40k

0.1µ

680k

FDFCT

FGD

SRCH

SENS SELECTOR

FS3

10k

0.022µ

FZC

300k

FZC

SENS1

Charge up

47

48

1

2

3

4

10

7

16

6

5

23

The above figure shows a block diagram of the focus servo. Ordinarily the FE signal is input to the focus phase compensation circuit through a 68kΩ resistance; however, when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal 100kΩ resistance and the capacitance connected to Pin 2. When this DFCT prevention circuit is not used, leave Pin 2 open. The defect switch operation can be enabled and disabled with command.

The capacitor connected between Pin 4 and GND is a time constant to boost the low frequency in the normal playback state. The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510kΩ is connected to Pin 10. The focus search level is approximately ±1.1Vp-p when using the constants indicated in the above figure. This level is inversely proportional to the resistance connected between Pin 16 and VEE. However, changing this resistance also changes the level of the track jump and sled kick as well. The FZC comparator inverted input is set to 10% of Vcc and VC (Pin 46); (Vcc – VC) × 10%.

∗

510kΩ resistance is recommended for Pin 10.

– 24 –

CXA2542AR

Tracking and Sled Servo

+ –

TE

TEO

BUFFER AMP

LPFI

0.01µ

150k100k

DFCT

100k

TDFCT

0.1µ

ATSC

470p

330k

47k

0.047µ

0.022µ

TZC

TGU TG2

0.033µ

470k

TG2

20k

510k

0.015µ

FSET

Tracking Phase Compensation

10k 90k

TM4

TM3

11µA

100k

TRACKING COIL

82k

15k

22µ

3.3µ

SL_P

TM2

TM6

TM5

22µA

100k

1k

100k

ATSC

8.2k

120k

0.015µ

M

SLED MOTOR

SL_O

SL_M

TM1

680k

66p

TA_M

TA_O

TG1

TM7

GAIN WINDOW COMPARATOR

BALANCE WINDOW COMPARATOR

SENS SELECTOR

BALH

BALL

TGH TGL

SENS1

SENS2

TE

24 23

15

14

13

11

12

10

9

8

44

43

45

42

41

The above figure shows a block diagram of the tracking and sled servo. The capacitor connected between Pins 8 and 9 is a time constant to cut the high-frequency gain when TG2 is OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510kΩ resistance is connected to Pin 10. In the CXA2542AQ, TG1 and TG2 are inter-linked switches. To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 11. To be more specific,

Track jump peak voltage = TM3 (or TM4) current × feedback resistance value The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 14;

Sled kick peak voltage = TM5 (or TM6) current × feedback resistance The values of the current for each switch are determined by the resistance connected between Pin 16 and VEE. When this resistance is 60kΩ :

TM3 (or TM4) = ±11µA, and TM5 (or TM6) = ±22µA. As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the internal resistance (100kΩ) and the capacitance connected to Pin 45.

The ISET pin is used to connect external resistance. This external resistance sets the current which determines the focus search, track jump, and sled kick levels.

• Focus search current

I1 = ×

(VBG: approximately 1.27V)

I2 = 2I1

• Track jump current (TM3 and TM4 current)

I = ×

• Sled kick current (TM5 and TM6 current, when D1 = D0 = 0 during 1X$ commands)

I =

Use external resistance of between 30kΩ and 240kΩ. Using external resistance outside this range may cause oscillation.

– 25 –

CXA2542AR

FS1

I

2I1

VBG

R

1 2

VBG

R

VBG

R

1 2

– 26 –

CXA2542AR

Focus OK Circuit

RF

15k 56k

VG

44k

20k

V

CC

0.63V

RF_O

RF_I

FOK

× 1

FOCUS OK AMP FOCUS OK

COMPARATOR

C5

0.01µ

31

30

25

DEFECT

LPC MIRR

V4

The focus OK circuit creates the timing window okaying the focus servo from the focus search state. The HPF output is obtained at Pin 30 from Pin 31 (RF signal), and the LPF output (opposite phase) of the focus OK amplifier output is also obtained. V4 is set in V3=V4 to cancel V3 of the RF amplifier voltage VRFO. The focus OK output is inverted when VRFI – VRFO ≈ –0.51V. Note that, C5 determines the time constant of the HPF for the mirror circuit and the LPF of the focus OK amplifier. Ordinarily, with a C5 equal to 0.01µF selected, the fc is equal to 1kHz, and block error rate degradation brought about by RF envelope defects caused by scratched discs can be prevented.

Defect circuit

After differentiated with the capacitance coupling and then inverted, the RF_O signal is bottom held by means of the long and short time constants. The short time-constant bottom hold responds to a disc mirror defect in excess of 0.1ms. The long time-constant bottom hold keeps the mirror level prior to the defect and shifts the level. The long and short time-constant signals are compared to generate the mirror defect detection signal. Be sure to disable DFCT ($34X) during focus search because the focus drive waveform is muted.

43k

× 2

b

DEFECT AMP

CC1 CC2

SENS1

CB

0.01µ

0.068µ

DEFECT SW

DEFECT COMPARATOR

DEFECT BOTTOM HOLD

e

c

d

26

SENS2

SENS SELECTOR

DFCT1

FLIP FLOP

DFCT2

27

24

23

INTERRUPTION COMPARATOR

f

–0.5V

a

RF

FOK

30

e

d

c

b

a

BOTTOM HOLD (1) solid line

DEFECT AMP

RFO

SENS1

BOTTOM HOLD (2) broken line

H

L

f

INT

H

L

– 27 –

CXA2542AR

Mirror Circuit

The mirror circuit performs peak and bottom hold after the RFI signal has been inverting amplified. For the peak hold, a time constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope fluctuation.

The DC restored-envelope signal J is obtained by amplifying the difference between the peak and bottom hold signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by comparing it to the peak hold signal K. If the value of C5 is made smaller, the low frequency component of the RF signal is cut off and the amplification of the signal G gets small. Then, that of the signal J gets also small and the signal K level becomes low, resulting in the short mirror output pulse width. Accordingly, when on the disc track, the mirror output is Low; when between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time constant must be sufficiently large compared with the traverse signal.

RF

0.033µ

RF_O

RF_I

CP

MIRROR COMPARATOR

PEAK & BOTTOM HOLD

× 1.4

K

MIRROR HOLD AMP

J

H

I

× 1

G

MIRROR AMP

SENS SELECTOR

MIRR

SENS2

31

30

29

24

FOK

DEFECT

FOK LPC

C5

0.01µ

1V

51k

22k

1.5k

RF_O

H

L

0V

G

(RF_I)

H

(PEAK HOLD)

I

(BOTTOM HOLD)

(MIRROR HOLD)

J

K

MIRR

– 28 –

CXA2542AR

SENS Selector

SENS1

FZC

DFCT1

TZC

BALH

TGH

FOH

ATSC

SENS2

HIGH-Z

DFCT2

MIRR

BALL

TGL

FOL

23

24

What is output to the SENS1 and SENS2 pins varies according to the address input to the DATA pin.

DATA (Pin 20) 8-bit transfer

SENS1 SENS2

ADDRESS

D7

0 0

1

0 0

0 1

1

0 0

1 0

1

0 1

0 0

1

X X

X

X X

X

X X

X

X X

X

FZC

DFCT1

TZC

H

(HIGH-Z)

H

(HIGH-Z)

DFCT2

MIRR

H

(HIGH-Z)

D6 D5 D4 D3 D2 D1 D0

DATA

DATA (Pin 20) 12-bit transfer

SENS1 SENS2

ADDRESS

D11

0 0 0

0

0 0 0

0

1 1 1

1

1 1 1

1

0 0 1

1

0 1 0

1

X X X

X

X X X

X

X X X

X

X X X

X

X X X

X

X X X

X

BALH

TGH FOH

ATSC

BALL

TGL FOL

H

(HIGH-Z)

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA

Notes)

• 12-bit transfer should be performed during $3XX commands. When 8 bits are transferred, SENS1 and

SENS2 are switched according to the D3 and D2 data.

• SENS1 and SENS2 are switched without latching.

– 29 –

CXA2542AR

Commands

The input data to operate this IC is configured as 8-bit/12-bit data; however, below, this input data is represented by 2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0 and F/$XXX for 12-bit. Commands for the CXA2542AR can be broadly divided into four groups ranging in value from $0X, $1X, $2X, $3XX.

1. $0X (FZC at SENS1 pin (Pin 23), H (Hi-Z) at SENS2 pin (Pin 24))

These commands are related to the focus servo control. The bit configuration is as shown below.

D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 FS4 — FS2 FS1

Four focus related switches exist: FS1, FS2, FS4 and DFCT.

$00 When FS1 = 0, Pin 7 is charged to (22µA – 11µA) × 50kΩ = 0.55V.

If, in addition, FS2 = 0, this voltage is no longer transferred, and the output at Pin 5 becomes 0V.

$02 From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output

to Pin 5. This voltage level is obtained by equation 1 below.

(22µA – 11µA) × 50kΩ × .... Equation 1

The SRCH DOWN speed can be increased by the charge up circuit.

$03 From the state described above, FS1 becomes 1, and a current source of +22µA is split off.

Then, a CR charge/discharge circuit is formed, and the voltage at Pin 7 decreases with the time as shown in Fig. 1 below.

Fig. 1. Voltage at Pin 7 when FS1 goes from 0 → 1

This time constant is obtained with the 50kΩ resistance and an external capacitor.

By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)

Fig. 2. Constructing the search voltage by alternating between $02 and $03. (Voltage at Pin 5)

resistance between Pins 5 and 6

50kΩ

0V

$ 00 02

03 02 03 0002

– 30 –

CXA2542AR

The instant when the signal is brought into focus.

$08

$03($00)

$02

(20ms) (200ms)

Drive voltage

Focus error

SENS1

(FZC)

Focus OK

∗

The broken lines in the figure indicate the voltage assuming the signal not in focus.

1-1. FS4

This switch is provided between the focus error input and the focus phase compensation, and is in charge of turning the focus servo ON and OFF.

$00 → $08 Focus off Focus on

1-2. Procedure of focus activation

For description, suppose that the polarity is as described below. a) The lens is searching the disc from far to near; b) The output voltage (Pin 5) is changing from negative to positive; and c) The focus S-curve is varying as shown below.

Fig. 3. S-curve

The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and turning the focus servo switch ON are performed while the focus S-curve transits the point A indicated in Fig.

3. To prevent misoperation, this signal is ANDed with the focus OK signal. In this IC, the FZC (Focus Zero Cross) signal is output from the SENS1 pin (Pin 23) as the point A transit signal. In addition, focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case). Following the line of the above description, focusing can be well obtained by observing the following timing chart.

t

A

Fig. 4. Focus ON timing chart

– 31 –

CXA2542AR

2. $1X (DFCT1 at SENS1 pin (Pin 23), DFCT2 at SENS2 pin (Pin 24))

These commands deal with switching TG1/TG2, brake circuit ON/OFF, and the sled kick output. The bit configuration is as follows:

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 1 TG1, TG2 Brake Sled kick

circuit level

ON/OFF ON/OFF

TG1, TG2, TM7

The purpose of TG1 and TG2 is to switch the tracking servo gain Up/Normal. TG1 and TG2 are interlinked switches. The brake circuit (TM7) is to prevent the frequently occurred phenomena where the merely 10-track jump has been performed actually though a 100-track jump was intended to be done due to the extremely degraded actuator settling caused by the servo motor exceeding the linear range after a 100 or 10-track jump. For the prevention method, when the actuator travels radially; that is, when it traverses from the inner track to the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the RF envelope and the tracking error is 180° out-of-phase to cut the unneeded portion of the tracking error and apply braking.

Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be minimized. To do this, the software sequence shown in B is better than the sequence shown in A.

FZC ↓ ?

NO

YES

F. OK?

NO

Transfer $08

Latch

FZC ↓ ?

NO

F. OK?

NO

Transfer $08

Latch

(A) (B)

YES

Fig. 5. Poor and good software command sequences

D1

(PS1)

0 0

1 1

D0

(PS0)

0 1

±1 ±2

±3 ±4

Relative

value

Sled kick level

– 32 –

CXA2542AR

Envelope

Detection

Waveform

Shaping

Waveform

Shaping

Edge Detection

[∗B]

[∗E]

RF_I

TZC

CXA2542AR

(Latch)

QD

CK

(MIRR)

[∗C]

[∗F]

[∗G]

BRK

D2

TM7 Low: open High: make

[∗A]

[∗D]

[∗H]

30

44

Fig. 6. TM7 movement during braking operation

From inner to outer track

0V

From outer to inner track

("MIRR")

("TZC")

Braking is applied from here.

[∗A]

[∗B]

[∗C]

[∗D]

[∗E]

[∗F]

[∗G]

[∗H]

Fig. 7. Internal waveform

3. $2X (TZC at SENS1 pin (Pin 23), MIRR at SENS2 pin (Pin 24))

These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse and fast forward pulse during access operations.

D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 0 Tracking Sled

control control 00 off 00 off 01 Servo ON 01 Servo ON 10 F-JUMP 10

F-FAST FORWARD

11 R-JUMP 11

R-FAST FORWARD

↓ ↓

TM1, TM3, TM4, TM2, TM5, TM6

– 33 –

CXA2542AR

4. $3XX

These commands mainly control the balance and gain control circuit switches used during automatic tracking adjustment and the bias circuit switch used during automatic focus bias adjustment. In the initial resetting state, BAL1 to BAL4 switches and TOG1 to TOG4 switches are ON. Also, the IFB1 to IFB6 switches are ON.

• Balance adjustment

The balance adjustment switches BAL1 to BAL4 can be controlled by setting D6 = 0 and D7 = 0. The switches are set using D0 to D3. At this time, SENS1 outputs BALH and SENS2 outputs BALL. Data is set by specifying switch conditions D0 to D3 and sending a latch pulse with D6 = 0 and D7 = 0. Sending a latch pulse with D6, D7 ≠ 0 does not change the balance switch settings.

START

C.OUT

is the frequency high

enough ?

SENS1/2

Balance OK ?

Adjustment Completed

BAL1 to BAL4 Switch Control

YES

NO

• Gain adjustment

The gain adjustment switches TOG1 to TOG4 can be controlled by setting D6 = 1 and D7 = 0. These switches are set using D0 to D3. At this time, SENS1 outputs TGH and SENS2 outputs TGL. In a fashion similar to the method used with the balance adjustment, set the data by specifying switch conditions D0 to D3 and sending a latch pulse with D6 = 1 and D7 = 0.

START

SENS1/2

GAIN OK ?

Adjustment Completed

TOG1 to TOG4 Switch control

YES

NO

Balance adjustment

Gain adjustment

– 34 –

CXA2542AR

• Focus bias adjustment

The focus bias adjustment switches IFB1 to IFB6 can be controlled by setting D6 = 0 and D7 = 1. The switches are set using D0 to D5. At this time, SENS1 outputs FOH and SENS2 outputs FOL. Data is set by specifying switch conditions D0 to D5 and sending a latch pulse with D6 = 0 and D7 = 1.

START

SENS1/2

BIAS OK ?

Adjustment Completed

IFB1 to IFB6 Switch Control

YES

NO

Focus bias adjustment method

• TGFL

The tracking gain can be switched by setting D5 with D6 = 1 and D7 = 0. The tracking gain is GAIN UP with D5 = 1 and NORMAL GAIN with D5 = 0. The TEO signal level can be made higher by approximately 6dB for GAIN UP. When the TEO signal level is low and TGH (SENS1 pin) does not go Low during tracking adjustment, the gain should be raised with the TGFL command for adjustment.

• LPC The laser power control circuit can be turned ON and OFF by setting D0 with D6 = 1 and D7 = 1. The circuit is ON with D0 = 1 and OFF with D0 = 0.

• LPCL The laser power control limit can be switched between ±30% and ±50% by setting D1 with D6 = 1 and D7 = 1. The control limit is ±30% with D1 = 0 and ±50% with D1 = 1.

• LDON The laser diode can be turned ON and OFF by setting D2 with D6 = 1 and D7 = 1. The laser diode is ON with D2 = 1 and OFF with D2 = 0.

• ATSC The anti-shock function can be controlled by setting D3 with D6 = 1 and D7 = 1. This function is disabled with D3 = 1 and enabled with D3 = 0. At this time, SENS1 outputs ATSC. Even if ATSC is disabled, ATSC is output to SENS1. When an anti-shock signal is generated during the enable status, TG1 and TG2 switch to GAIN UP mode. (In the Block Diagram, TG1 is set to the side and TG2 is OFF. Even if TG1 and TG2 are in NORMAL mode, they switch to GAIN UP mode in conjunction with ATSC.) When the anti-shock function is not used, Pin 43 (ATSC) should be connected to VC.

• RDFCT2 DFCT2 can be reset by setting D4 with D6 = 1 and D7 = 1. DFCT2 is reset with D4 = 1. After a reset, High is held when DFCT1 rises. During $1X commands, DFCT2 is output from SENS2. DFCT2 operates even if DFCT is disabled. Whether or not DFCT rises at the proper timing for the microcomputer can also be confirmed.

• INT The interruption (scratched disc) countermeasure circuit can be set to the operating status by setting D5 with D6 = 1 and D7 = 1. This circuit is enabled when D5 = 1 and disabled when D5 = 0. Even if DFCT1 does not rise, this circuit is effective for scratched discs which cause MIRR to rise. When MIRR rises, the DFCT switch is routed through the low-pass filter. The interruption countermeasure circuit is forcibly turned OFF regardless of the command when the tracking gain is increased. (including when the gain is increased by ATSC) Even if DFCT is disabled, the interruption countermeasure circuit operates when INT is enabled.

– 35 –

CXA2542AR

– 36 –

CXA2542AR

CPU Serial Interface Timing Chart

tWCK

D0 D1 D2 D3 D4 D5 D6 D7 D0 t

WCK

tSU

1/fck

t

h

tCD

tWL

tD

DATA

CLK

XLT

Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width Data transfer interval Low level input voltage High level input voltage

Symbol

fck fwck

tsu th tD tWL tCD

VIL VIH

Min.

500 500 500

500 1000 1000

0.0

(VCC – VEE) × 0.9

Typ. Max. Unit

MHz

ns ns ns ns ns ns

V V

1

(VCC – VEE) × 0.1

VCC

(VCC = 3.0V)

– 37 –

CXA2542AR

System Control

FOCUS

CONTROL

TRACKING

CONTROL

TRACKING

SLED MODE

D7 D6 D5 D4

FS4

Focus

1 = ON

0 = OFF

TG1, TG2

1 = GAIN UP

0 = NORMAL

0

1

0

1

0

—

BRAKE

1 = ENABLE

0 = DISABLE

FS2

SRCH ON

1 = ON

0 = OFF

SLED

KICK + 2

FS2

SRCH UP

1 = UP

0 = DOWN

SLED

KICK + 1

FZC

DFCT1

TZC

TRACKING MODE

∗

1

SLED MODE

∗2

ADDRESS

D3 D2 D1 D0

DATA

DATA (Pin 20) 8-bit transfer

SENS1

H

(HIGH-Z)

DFCT2

MIRR

SENS2

∗

1

TRACKING MODE

FWD JUMP

REV JUMP

D3

0

1

D2

0

1

0

1

OFF

ON

∗2

SLED MODE

FWD MOVE

REV MOVE

D1

0

1

D0

0

1

0

1

OFF

ON

Item

– 38 –

CXA2542AR

E-F

BALANCE

TRACKING

GAIN

FOCUS

BIAS

Others

D11 D10 D9 D8

DFCT

1 = DISABLE

0 = ENABLE

TGFL

1 = GAIN UP

0 = NORMAL

IFB6

1 = OFF

0 = ON

INT

1 = ENABLE

0 = DISABLE

0

1

0

1

0

1

0

1

D7 D6

—

IFB5

1 = OFF

0 = ON

RDFCT2

1 = RESET

0 = NORMAL

BAL4

1 = OFF

0 = ON

TOG4

1 = OFF

0 = ON

IFB4

1 = OFF

0 = ON

ATSC

1 = DISABLE

0 = ENABLE

BAL3

1 = OFF

0 = ON

TOG3

1 = OFF

0 = ON

IFB3

1 = OFF

0 = ON

LDON

1 = ON

0 = OFF

BALH

TGH

FOH

ATSC

ADDRESS

D5 D4 D3 D2

BAL2

1 = OFF

0 = ON

TOG2

1 = OFF

0 = ON

IFB2

1 = OFF

0 = ON

LPCL

1 = ±50%

0 = ±30%

BAL1

1 = OFF

0 = ON

TOG1

1 = OFF

0 = ON

IFB1

1 = OFF

0 = ON

LPC

1 = ON

0 = OFF

D1 D0

DATA

DATA (Pin 20) 12-bit transfer

SENS1

BALL

TGL

FOL

H

(HIGH-Z)

SENS2

Item

Notes)

• When ATSC is enabled, even if TG1 and TG2 are in NORMAL mode, TG1 and TG2 switch to GAIN UP mode in conjunction with ATSC.

• INT is forcibly disabled regardless of the command when the tracking gain is increased. (including when the gain is increased by ATSC)

When reset

• SENS1 = FZC

• SENS2 = High (Hi-Z)

• RDFCT2 = 1 (Reset)

• IFB1 to IFB6 = 0 (switch ON)

• TOG1 to TOG4 = 0 (switch ON)

• BAL1 to BAL4 = 1 (switch ON)

• Other data is "0".

– 39 –

CXA2542AR

Serial Data Truth Table

Serial Data

FOCUS CONTROL

0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 1011 0000 1100 0000 1101 0000 1110 0000 1111

0001 0000 0001 0001 0001 0010 0001 0011 0001 0100 0001 0101 0001 0110 0001 0111 0001 1000 0001 1001 0001 1010 0001 1011 0001 1100 0001 1101 0001 1110 0001 1111

$00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

$10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

HEX Functions

FS4

BRAK

SLD KICK

KICK

+1

KICK

+2

Fig. 6

D2

TG1 TG2

TRACKING CONTROL

FS2 FS1

Notes) • FS1

1: OFF 0: ON

• FS2 1: ON 0: OFF

• FS4 In the Block Diagram: 1: SW side 0: SW side

Notes) • TG1

In the Block Diagram: 1: SW side 0: SW side

• TG2 1: OFF 0: ON

• BRAKE When D2 in Fig. 6 is: 1: 1 0: 0

• Sled kick level

D1

0 0 1 1

0 1 0 1

±1 ±2 ±3 ±4

D0 Relative value

– 40 –

CXA2542AR

Serial Data

TRACKING/SLED MODE

0010 0000 0010 0001 0010 0010 0010 0011 0010 0100 0010 0101 0010 0110 0010 0111 0010 1000 0010 1001 0010 1010 0010 1011 0010 1100 0010 1101 0010 1110 0010 1111

$20 $21 $22 $23 $24 $25 $26 $27 $28

$29 $2A $2B $2C $2D $2E $2F

0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0

HEX Function

TM6 TM5 TM4 TM3

0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

TM2

0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0

TM1

Notes) • TM1/TM2

In the Block Diagram: 1: SW side 0: SW side

• TM3/TM4/TM5/TM6 1: ON 0: OFF

– 41 –

CXA2542AR

Serial Data

$3XX

0011 0000 0000 0011 0000 0001 0011 0000 0010 0011 0000 0011 0011 0000 0100 0011 0000 0101 0011 0000 0110 0011 0000 0111 0011 0000 1000 0011 0000 1001 0011 0000 1010 0011 0000 1011 0011 0000 1100 0011 0000 1101 0011 0000 1110 0011 0000 1111

0011 0001 0000 0011 0001 0001 0011 0001 0010 0011 0001 0011 0011 0001 0100 0011 0001 0101 0011 0001 0110 0011 0001 0111 0011 0001 1000 0011 0001 1001 0011 0001 1010 0011 0001 1011 0011 0001 1100 0011 0001 1101 0011 0001 1110 0011 0001 1111

0011 0010 0000 0011 0010 0001 0011 0010 0010 0011 0010 0011 0011 0010 0100 0011 0010 0101 0011 0010 0110 0011 0010 0111 0011 0010 1000 0011 0010 1001 0011 0010 1010 0011 0010 1011 0011 0010 1100 0011 0010 1101 0011 0010 1110 0011 0010 1111

$300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30A $30B $30C $30D $30E $30F

$310 $311 $312 $313 $314 $315 $316 $317 $318 $319 $31A $31B $31C $31D $31E $31F

$320 $321 $322 $323 $324 $325 $326 $327 $328 $329 $32A $32B $32C $32D $32E $32F

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

— — — — — — — — — — — — — — — —

E E E E E E E E E E E E E E E E

D D D D D D D D D D D D D D D D

— — — — — — — — — — — — — — — —

HEX BAL SW

4 3 2 1 4 3 2 1 456 3 2 1

TOG SW IFB SW

INT

RDF

CT2

ATSC

LDON

LPCL LPC

DFCT

TGFL

– 42 –

CXA2542AR

Serial Data

$3XX

0011 0011 0000 0011 0011 0001 0011 0011 0010 0011 0011 0011 0011 0011 0100 0011 0011 0101 0011 0011 0110 0011 0011 0111 0011 0011 1000 0011 0011 1001 0011 0011 1010 0011 0011 1011 0011 0011 1100 0011 0011 1101 0011 0011 1110 0011 0011 1111

0011 0100 0000 0011 0100 0001 0011 0100 0010 0011 0100 0011 0011 0100 0100 0011 0100 0101 0011 0100 0110 0011 0100 0111 0011 0100 1000 0011 0100 1001 0011 0100 1010 0011 0100 1011 0011 0100 1100 0011 0100 1101 0011 0100 1110 0011 0100 1111

0011 0101 0000 0011 0101 0001 0011 0101 0010 0011 0101 0011 0011 0101 0100 0011 0101 0101 0011 0101 0110 0011 0101 0111 0011 0101 1000 0011 0101 1001 0011 0101 1010 0011 0101 1011 0011 0101 1100 0011 0101 1101 0011 0101 1110 0011 0101 1111

$330 $331 $332 $333 $334 $335 $336 $337 $338

$339 $33A $33B $33C $33D $33E

$33F

$340

$341

$342

$343

$344

$345

$346

$347

$348

$349 $34A $34B $34C $34D $34E

$34F

$350

$351

$352

$353

$354

$355

$356

$357

$358

$359 $35A $35B $35C $35D $35E

$35F

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

— — — — — — — — — — — — — — — —

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

— — — — — — — — — — — — — — — —

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

— — — — — — — — — — — — — — — —

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

— — — — — — — — — — — — — — — —

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

— — — — — — — — — — — — — — — —

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

— — — — — — — — — — — — — — — —

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

— — — — — — — — — — — — — — — —

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

— — — — — — — — — — — — — — — —

D D D D D D D D D D D D D D D D

— — — — — — — — — — — — — — — —

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HEX BAL SW

4 3 2 1 4 3 2 1 456 3 2 1

TOG SW IFB SW

INT

RDF

CT2

ATSC

LDON

LPCL LPC

DFCT

TGFL

– 43 –

CXA2542AR

Serial Data

$3XX

0011 0110 0000 0011 0110 0001 0011 0110 0010 0011 0110 0011 0011 0110 0100 0011 0110 0101 0011 0110 0110 0011 0110 0111 0011 0110 1000 0011 0110 1001 0011 0110 1010 0011 0110 1011 0011 0110 1100 0011 0110 1101 0011 0110 1110 0011 0110 1111

0011 0111 0000 0011 0111 0001 0011 0111 0010 0011 0111 0011 0011 0111 0100 0011 0111 0101 0011 0111 0110 0011 0111 0111 0011 0111 1000 0011 0111 1001 0011 0111 1010 0011 0111 1011 0011 0111 1100 0011 0111 1101 0011 0111 1110 0011 0111 1111

0011 1000 0000 0011 1000 0001 0011 1000 0010 0011 1000 0011 0011 1000 0100 0011 1000 0101 0011 1000 0110 0011 1000 0111 0011 1000 1000 0011 1000 1001 0011 1000 1010 0011 1000 1011 0011 1000 1100 0011 1000 1101 0011 1000 1110 0011 1000 1111

$360

$361

$362

$363

$364

$365

$366

$367

$368

$369

$36A

$36B

$36C

$36D

$36E

$36F

$370

$371

$372

$373

$374

$375

$376

$377

$378

$379

$37A

$37B

$37C

$37D

$37E

$37F

$380

$381

$382

$383

$384

$385

$386

$387

$388

$389

$38A

$38B

$38C

$38D

$38E

$38F

— — — — — — — — — — — — — — — —

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

— — — — — — — — — — — — — — — —

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

— — — — — — — — — — — — — — — —

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

— — — — — — — — — — — — — — — —

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

— — — — — — — — — — — — — — — —

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

— — — — — — — — — — — — — — — —

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

— — — — — — — — — — — — — — — —

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

— — — — — — — — — — — — — — — —

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

— — — — — — — — — — — — — — — —

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

— — — — — — — — — — — — — — — —

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

— — — — — — — — — — — — — — — —

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

— — — — — — — — — — — — — — — —

HEX BAL SW

4 3 2 1 4 3 2 1 456 3 2 1

TOG SW IFB SW

INT

RDF

CT2

ATSC

LDON

LPCL LPC

DFCT

TGFL

– 44 –

CXA2542AR

Serial Data

$3XX

0011 1001 0000 0011 1001 0001 0011 1001 0010 0011 1001 0011 0011 1001 0100 0011 1001 0101 0011 1001 0110 0011 1001 0111 0011 1001 1000 0011 1001 1001 0011 1001 1010 0011 1001 1011 0011 1001 1100 0011 1001 1101 0011 1001 1110 0011 1001 1111

0011 1010 0000 0011 1010 0001 0011 1010 0010 0011 1010 0011 0011 1010 0100 0011 1010 0101 0011 1010 0110 0011 1010 0111 0011 1010 1000 0011 1010 1001 0011 1010 1010 0011 1010 1011 0011 1010 1100 0011 1010 1101 0011 1010 1110 0011 1010 1111

0011 1011 0000 0011 1011 0001 0011 1011 0010 0011 1011 0011 0011 1011 0100 0011 1011 0101 0011 1011 0110 0011 1011 0111 0011 1011 1000 0011 1011 1001 0011 1011 1010 0011 1011 1011 0011 1011 1100 0011 1011 1101 0011 1011 1110 0011 1011 1111

$390

$391

$392

$393

$394

$395

$396

$397

$398

$399

$39A

$39B $39C $39D

$39E

$39F

$3A0

$3A1

$3A2

$3A3

$3A4

$3A5

$3A6

$3A7

$3A8

$3A9 $3AA $3AB $3AC $3AD $3AE $3AF

$3B0

$3B1

$3B2

$3B3

$3B4

$3B5

$3B6

$3B7

$3B8

$3B9 $3BA $3BB $3BC $3BD $3BE $3BF

— — — — — — — — — — — — — — — —

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

— — — — — — — — — — — — — — — —

HEX BAL SW

4 3 2 1 4 3 2 1 456 3 2 1

TOG SW IFB SW

INT

RDF

CT2

ATSC

LDON

LPCL LPC

DFCT

TGFL

– 45 –

CXA2542AR

Serial Data

$3XX

0011 1100 0000 0011 1100 0001 0011 1100 0010 0011 1100 0011 0011 1100 0100 0011 1100 0101 0011 1100 0110 0011 1100 0111 0011 1100 1000 0011 1100 1001 0011 1100 1010 0011 1100 1011 0011 1100 1100 0011 1100 1101 0011 1100 1110 0011 1100 1111

0011 1101 0000 0011 1101 0001 0011 1101 0010 0011 1101 0011 0011 1101 0100 0011 1101 0101 0011 1101 0110 0011 1101 0111 0011 1101 1000 0011 1101 1001 0011 1101 1010 0011 1101 1011 0011 1101 1100 0011 1101 1101 0011 1101 1110 0011 1101 1111

0011 1110 0000 0011 1110 0001 0011 1110 0010 0011 1110 0011 0011 1110 0100 0011 1110 0101 0011 1110 0110 0011 1110 0111 0011 1110 1000 0011 1110 1001 0011 1110 1010 0011 1110 1011 0011 1110 1100 0011 1110 1101 0011 1110 1110 0011 1110 1111

$3C0

$3C1

$3C2

$3C3

$3C4

$3C5

$3C6

$3C7

$3C8

$3C9 $3CA $3CB $3CC $3CD $3CE

$3CF

$3D0

$3D1

$3D2

$3D3

$3D4

$3D5

$3D6

$3D7

$3D8

$3D9 $3DA $3DB $3DC $3DD $3DE

$3DF

$3E0

$3E1

$3E2

$3E3

$3E4

$3E5

$3E6

$3E7

$3E8

$3E9

$3EA

$3EB $3EC $3ED

$3EE

$3EF

— — — — — — — — — — — — — — — —

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

E E E E E E E E D D D D D D D D

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

— — — — — — — — — — — — — — — —

HEX BAL SW

4 3 2 1 4 3 2 1 456 3 2 1

TOG SW IFB SW

INT

RDF

CT2

ATSC

LDON

LPCL LPC

DFCT

TGFL

Notes) • 0 means OFF and 1 means ON for TOG SW and BAL SW. These are not equal to the setting values

of each bit for serial data.

• "—" in the Truth Table indicates that the status does not change.

• TGFL

In the Block Diagram: 1: SW side 0: SW side

• ATSC E: enable/D: disable

• DFCT E: enable/D: disable

– 46 –

CXA2542AR

Serial Data

$3XX

0011 1111 0000 0011 1111 0001 0011 1111 0010 0011 1111 0011 0011 1111 0100 0011 1111 0101 0011 1111 0110 0011 1111 0111 0011 1111 1000 0011 1111 1001 0011 1111 1010 0011 1111 1011 0011 1111 1100 0011 1111 1101 0011 1111 1110 0011 1111 1111

$3F0

$3F1

$3F2

$3F3

$3F4

$3F5

$3F6

$3F7

$3F8

$3F9 $3FA $3FB $3FC $3FD $3FE $3FF

— — — — — — — — — — — — — — — —

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

E E E E E E E E D D D D D D D D

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

— — — — — — — — — — — — — — — —

HEX BAL SW

4 3 2 1 4 3 2 1 456 3 2 1

TOG SW IFB SW

INT

RDF

CT2

ATSC

LDON

LPCL LPC

DFCT

TGFL

– 47 –

CXA2542AR

Initial State (resetting state)

Item

FOCUS CONTROL TRACKING CONTROL TRACKING SLED MODE

ADDRESS

D7

0 0 0

0 0 1

0 1 0

0 0 0

$00 $10 $20

D6 D5 D4 D3 D2 D1 D0

DATA

HEX

Item

E-F BALANCE TRACKING GAIN FOCUS BIAS Others

ADDRESS

D11

0 0 0 0

1 1 1 1

0 0 1 1

0 1 0 1

0 0 0 0

0 0 0 1

$300 $340 $380

$3D0

D10 D9 D8 D7 D6 D5 D4

0 0 0 0

D3

0 0 0 0

D2

0 0 0 0

D1

0 0 0 0

D0

DATA

HEX

The above data means the following operation modes.

FOCUS CONTROL : FOCUS OFF, FOCUS SEARCH OFF, FOCUS SEACH DOWN TRACKING CONTROL : TG1-TG2 NORMAL, BRAKE DISABLE, SLED KICK relative level value ±1 TRACKING SLED MODE : TRACKING OFF, SLED OFF E-F BALANCE : BAL1 to BAL4 = 0 (switch ON). DFCT ENABLE TRACKING GAIN : TOG1 to TOG4 = 0 (switch ON), TGFL NORMAL FOCUS BIAS : IFB1 to IFB6 = 0 (switch ON) Others : INT DISABLE, DFCT2 RESET, ATSC ENABLE, LDON OFF, LPCL ±30%, LPC OFF

– 48 –

CXA2542AR

2. Sled amplifier The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately 20dB.

3. Focus/Tracking internal phase compensation and reference design material

Notes on Operation

1. Focus OK circuit

1) Refer to the "Description of Operation" for the time constant setting of the focus OK amplifier LPF and the mirror amplifier HPF.

2) The equivalent circuit for the output pin (FOK) is shown in the diagram below.

VCC

20k

40k

100k

VEE VEE

RL

FOK

V

CC

25

The FOK and comparator output are as follows:

Output voltage High : VFOKH ≈ near Vcc Output voltage Low : VFOKL ≈ Vsat (NPN) + VEE

Item SD Measurement pin Conditions Typ. Unit

1.2kHz gain

1.2kHz phase

1.2kHz gain

1.2kHz phase

2.7kHz gain

2.7kHz phase

08 08 25 25 25 → 13 25 → 13

6

CFLB = 0.1µF CFGD = 0.1µF

21.5 63 13

–125

26.5

–130

dB

deg

dB

deg

dB

deg

CTGU = 0.1µF

13

FCS

TRK

4. Laser Poser Control The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the RF level fluctuations. The laser life is shortened by increasing the laser power when the less light is reflected from the disc. It is recommended that the typical laser power value is set lower to maintain the laser life. Take care of the laser maximum ratings when using the laser power control circuit.

– 49 –

CXA2542AR

Package Outline Unit: mm

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT LEAD MATERIAL PACKAGE MASS

EPOXY RESIN

PLATING

42/COPPER ALLOY

PACKAGE STRUCTURE

48PIN LQFP (PLASTIC)

9.0 ± 0.2

∗ 7.0 ± 0.1

1

12

13

24

25

36

37

48

(0.22)

0.18 – 0.03

+ 0.08

0.2g

LQFP-48P-L01

LQFP048-P-0707

(8.0)

0.5 ± 0.2

0.127 – 0.02

+ 0.05

A

1.5 – 0.1

+ 0.2

0.1

SOLDER/PALLADIUM

NOTE: Dimension “∗” does not include mold protrusion.

0.1 ± 0.1

0.5 ± 0.2

0° to 10°

DETAIL A

0.13

M

0.5

S

B

DETAIL B:SOLDER

(0.18)

(0.127)

DETAIL B:PALLADIUM

0.127 ± 0.04

0.18 – 0.03

+ 0.08

0.127 – 0.02

+0.05

0.18 ± 0.03