Page 1
CXA1946BQ/BR
For the availability of this product, please contact the sales office.
Electronic Volume
Description
The CXA1946BQ/BR is a serial control electronic
volume IC designed for use in audio systems.
Features
• Loudness
• Volume control (0dB to –87dB in 1dB step, –∞dB)
• Balance
• Tone control (15 steps, 2 bands, –16dB to +16dB)
• Fader
(2dB-step to –20dB, –25dB, –35dB, –45dB, –60dB, –∞dB)
• Input selector (4 channels)
• Gain can be set for each input channel (common for channels 3 and 4)
• Serial data control (DATA, CLK, CE)
• Single 8V power supply
• Zero-cross detection circuit (with timer)
• Power-off mute
• Volume control and tone control input/output pins are separate.
• Portable phone noise countermeasure
48 pin QFP (Plastic)
48 pin LQFP (Plastic)
Absolute Maximum Ratings
• Supply voltage VCC 13 V
• Operating temperature Topr –40 to +85 °C
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation PD 350 mW (Ta = 85°C)
Operating Conditions
Supply voltage VCC 6 to 12 V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E96X03A7Y
Page 2
Block Diagram and Pin Configuration
CXA1946BQ/BR
GAIN12
GAIN11
IN14
IN13
IN12
IN11
IN21
IN22
44
37
38
39
40
41
42
43
GAIN134
36
INPUT SW
LDLC1
35
ZCDET
LOUD
LDHC1
34
INAO1
33
8dB STEP
VOLUME
VRIN1
32
LATCH
SHIFT REGISTER
VOUT1
31
1dB STEP
VOLUME
VCTBUFF
VCTBUFF
VCTBUFF
30
TIN1
TCHC1
29
LATCH CONTROL
28
TONE
TCLC11
TCLC12
27
26
TCO1
FADER
100k
100k
FDIN1
25
24
23
22
21
20
19
18
17
FNTO1
REO1
CE
CLK
DGND
GND
CC
V
VCT
IN23
IN24
GAIN21
GAIN22
45
46
47
48
INPUT SW
GAIN234
2
LDLC2
LOUD
3
LDHC2
VOLUME
8dB STEP
4
INAO2
5
VRIN2
VCTBUFF
VCTBUFF
VCTBUFF
VOLUME
1dB STEP
6
VOUT2
7
TIN2
8
TCHC2
TONE
9
TCLC21
10
TCLC22
11
FADER
TCO2
121
FDIN2
16
15
14
13
DATA
TIMER
REO2
FNTO2
– 2 –
Page 3
Pin Description
CXA1946BQ/BR
Pin
No.
1
36
2
35
Symbol
GAIN234
GAIN134
LDLC2
LDLC1
I/O resistance
Pin voltage
~
∞
–
VCT
6.18kΩ
VCT
36
35
Equivalent circuit
V
CC
1
GND
CC
V
2
Sets gain for IN3 and IN4.
Sets loudness low cut-off
frequency.
Description
3
34
4
33
LDHC2
LDHC1
INAO2
INAO1
8.92kΩ
VCT
—
VCT
33
3
34
GND
V
CC
Sets loudness high cut-off
frequency.
GND
V
CC
4
Input selector output
– 3 –
GND
Page 4
CXA1946BQ/BR
Pin
No.
5
32
6
31
Symbol
VRIN2
VRIN1
VOUT2
VOUT1
I/O resistance
Pin voltage
9.5kΩ
VCT
—
VCT
32
31
Equivalent circuit
CC
V
5
Description
Volume input
GND
VCC
6
Volume output
7
30
8
29
TIN2
TIN1
TCHC2
TCHC1
19kΩ
VCT
5kΩ
VCT
30
7
29
GND
V
CC
Tone input
GND
V
CC
8
Sets tone high frequency.
– 4 –
GND
Page 5
CXA1946BQ/BR
Pin
No.
9
28
10
27
Symbol
TCLC21
TCLC11
TCLC22
TCLC12
I/O resistance
Pin voltage
8kΩ
VCT
8kΩ
VCT
28
Equivalent circuit
V
CC
9
GND
CC
V
10
27
Sets tone low frequency.
Sets tone low frequency.
Description
11
26
12
25
TCO2
TCO1
FDIN2
FDIN1
—
VCT
24kΩ
VCT
12
11
26
25
GND
VCC
GND
V
CC
Tone control output
Fader input
– 5 –
GND
Page 6
CXA1946BQ/BR
Pin
No.
13
24
14
23
Symbol
FNTO2
FNTO1
REO2
REO1
I/O resistance
Pin voltage
—
VCT
—
VCT
14
13
23
24
Equivalent circuit
V
CC
GND
VCC
Description
Front output
Rear output
15
16
TIMER
DATA
GND
VCC
—
—
~
∞
–
—
15
16
Sets timer.
GND
VCC
Serial data input
– 6 –
GND
Page 7
CXA1946BQ/BR
Pin
No.
17
18
19
20
21
Symbol
VCT
VCC
GND
DGND
CLK
I/O resistance
Pin voltage
—
VCT
VCC
GND
—
~
∞
–
—
21
Equivalent circuit
V
CC
GND
VCC
Description
Center electric potential
+ power supply
GND
Digital GND
Serial clock input
22
37
48
CE
GAIN12
GAIN22
~
∞
–
—
~
∞
–
VCT
37
48
22
Latch enable input
GND
VCC
Sets gain for IN2.
GND
– 7 –
Page 8
CXA1946BQ/BR
Pin
No.
38
47
39
40
41
42
43
44
45
46
Symbol
GAIN11
GAIN21
IN14
IN13
IN12
IN11
IN21
IN22
IN23
IN24
I/O resistance
Pin voltage
~
∞
–
50kΩ
VCT
47
41
39
40
42
38
Equivalent circuit
43
44
45
46
VCC
GND
V
CC
GND
Description
Sets gain for IN1.
Signal input
– 8 –
Page 9
Data Format
(a) Data allocation
CXA1946BQ/BR
FAST BIT
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
NOP
ISW
LOUD
VRC1
VRF1
VRC2
VRF2
TONE BASS
MSB
LAST BIT
D24
D25
D26
D27
D28
D29
D30
D31
D32
TONE TREBLE
FADER
FADER SELECT
LSB
– 9 –
Page 10
(b) Setting table
• NOP
Setting value
D1
CXA1946BQ/BR
D2
—
• ISW
Setting value
IN14/IN24
IN13/IN23
IN12/IN22
IN11/IN21
• LOUD
Setting value
ON
OFF
• VRC1/VRC2
Setting value
0
–8
–16
–24
–32
–40
–48
–56
–64
–72
–80
–∞
–∞
0
D3
1
1
0
0
D5
1
0
D6/D13
1
1
1
1
1
1
1
1
0
0
0
0
0
0
D4
1
0
1
0
D7/D14
1
1
1
1
0
0
0
0
1
1
1
1
0
D8/D15
1
1
0
0
1
1
0
0
1
1
0
0
0
D9/D16
1
0
1
0
1
0
1
0
1
0
1
0
0
• VRF1/VRF2
Setting value
0
–1
–2
–3
–4
–5
–6
–7
D10/D17
1
1
1
1
0
0
0
0
D11/D18
1
1
0
0
1
1
0
0
D12/D19
1
0
1
0
1
0
1
0
– 10 –
Page 11
• TONE BASS/TREBLE
CXA1946BQ/BR
Setting value
14
12
10
8
6
4
2
0
• BOOST/CUT
Setting value
BOOST
CUT
• FADER
Setting value
–∞
–60
–45
–35
–25
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
D20/D24
1
1
1
1
0
0
0
0
D23/D27
1
0
D28
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D21/D25
1
1
0
0
1
1
0
0
D29
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D22/D26
1
0
1
0
1
0
1
0
D30
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D31
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
• FADER SELECT
Setting value
Attenuation of front signal
Attenuation of rear signal
D32
1
0
• RESET
Reset is performed automatically when power is first supplied to the IC; there is no reset pin.
The following table shows the respective statuses of various settings after a reset has been performed.
However, from the time when power is first supplied until the first data transfer, keep CE high by pulling it up
to Vcc, etc.
MODE
INPUT
VRC1
VRF1
VRC2
VRF2
LOUD
TONE BASS
TONE TREBLE
FADER
Setting value
1
–∞
–7dB
–∞
–7dB
OFF
0dB
0dB
0dB, REAR
– 11 –
Page 12
CXA1946BQ/BR
Electrical Characteristics (Unless otherwise specified, Vcc = 8V, Ta = 25°C)
Item Symbol Measurement conditions Min. Typ. Max. Unit
Current consumption
Total harmonic distortion
Output noise voltage
Maximum output voltage
Separation
Volume maximum attenuation
Loudness
Low
High
Bass max. boost gain
Bass max. cut gain
Treble max. boost gainn
Treble max. cut gain
Low
Input voltage
High
Input voltage range
ICC
THD
Vn
Vom
CS
ATTm
Glb
Glh
Gbb
Gbc
Gtb
Gtc
Vsl
Vsh
Vin
No signal
1kHz, 5dBm output
input shorted, A weight
1kHz
1kHz
1kHz
100Hz, VRC = –16dB
10kHz, VRC = –16dB
DATA, CLK, CE
IN11 to 14, IN21 to 24, VRIN1, VRIN2,
TIN1, TIN2, FDIN1, FDIN2
—
—
—
8
72
85
7
5
14
14
14
14
0
3
1
20
0.005
7
—
90
90
8
6
16
16
16
16
—
—
—
25
0.01
10
—
—
—
9
7
18
18
18
18
1.5
6
VCC–1
mA
%
µVrms
dBm
dB
dB
dB
dB
dB
dB
dB
dB
V
V
V
– 12 –
Page 13
Electrical Characteristics Measurement Circuit
CXA1946BQ/BR
V14
AC
V13
AC
V12
AC
V11
AC
V21
AC
V22
AC
V23
AC
V24
AC
10k
AC
V3
V2
V1
0.01µ
10k
ON
V5
OP AMP
VCT-50mV
1k
1k
1k
220p
VEE
3 to 6V
10µ
LDHC1
LDHC2
0.0022µ
33
4
0.0022µ
A
S2
32
INAO1
INAO2
10µ
10k
10k
36
GAIN12
37
GAIN11
10k
S14
S13
S12
S11
S21
S22
S23
S24
10k
10k
10k
10k
10k
10k
10k
10k
44
45
46
47
48
38
39
40
41
42
43
IN14
IN13
IN12
IN11
IN21
IN22
IN23
IN24
GAIN21
GAIN22
1
10k
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
0.047µ
35
34
LDLC1
GAIN134
LDLC2
GAIN234
10k
3
2
0.047µ
V6
AC
B
A
B
S3
30
31
VRIN1
VRIN2
5
TIN1
VOUT1
VOUT2
TIN2
7
6
29
8
TCHC1
TCHC2
0.0027µ
28
9
0.0027µ
10µ
TCLC11
TCLC21
10µ
10µ
0.39µ
26
27
TCO1
TCLC12
TCLC22
TCO2
11
10
0.39µ
10µ
V7
AC
B
A
S5-1
25
FDIN1
FNTO1
24
REO1
23
CE
22
CLK
21
DGND
20
GND
19
CC
V
18
S6
VCT
17
DATA
16
TIMER
15
REO2
14
FNTO2
13
FDIN2
12
S5-2
A
B
V8
AC
10k
10k
10k
10k
OFF
S1
1k
1k
CC
V
3 to 6V
OF
F
ON
1k
B
S4
A
– 13 –
Page 14
Application Circuit 1
CXA1946BQ/BR
37
38
39
40
41
42
43
44
45
46
47
48
GAIN12
GAIN11
IN14
IN13
IN12
IN11
IN21
IN22
IN23
IN24
GAIN21
GAIN22
0.047µ
36
1
0.047µ
0.0022µ
10µ
35
34
LDLC1
GAIN134
GAIN234
LDHC1
LDLC2
LDHC2
3
2
33
INAO1
INAO2
4
0.0022µ
10µ
32
VRIN1
VRIN2
5
0.0027µ
30
31
VOUT1
VOUT2
6
TIN1
TIN2
7
0.0027µ
29
TCHC1
TCHC2
8
0.39µ
10µ
28
TCLC11
TCLC21
9
10µ
10µ
26
0.39µ
25
TCO1
FDIN1
24
FNTO1
REO1
23
CE
22
CLK
21
DGND
20
GND
19
V
CC
18
VCT
17
DATA
16
TIMER
15
REO2
14
FNTO2
13
TCO2
FDIN2
12
11
10µ
33µ
10µ
0.01µ
27
TCLC12
TCLC22
10
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 14 –
Page 15
Application Circuit 2
CXA1946BQ/BR
37
38
39
40
41
42
43
44
45
46
47
48
GAIN12
GAIN11
IN14
IN13
IN12
IN11
IN21
IN22
IN23
IN24
GAIN21
GAIN22
0.047µ
36
35
GAIN134
GAIN234
1
0.0022µ
10µ
32
33
34
INAO1
LDLC1
LDHC1
LDLC2
LDHC2
3
2
VRIN1
INAO2
VRIN2
5
4
30
31
VOUT1
VOUT2
7
6
0.0027µ
28
29
TIN1
TCHC1
TIN2
TCHC2
8
0.39µ
10µ
TCLC11
TCLC21
9
10µ
26
27
TCLC12
TCLC22
10
25
TCO1
FDIN1
24
FNTO1
REO1
23
CE
22
CLK
21
DGND
20
GND
19
V
CC
18
VCT
17
DATA
16
TIMER
15
REO2
14
FNTO2
13
FDIN2
TCO2
12
11
33µ
10µ
0.01µ
0.047µ
10µ
0.0022µ
0.0027µ
10µ
0.39µ
10µ
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 15 –
Page 16
CXA1946BQ/BR
20
Tone control characteristics
16
12
8
4
0
–4
Response [dB]
–8
–12
–16
–20
10 100 1k 10k 100k
Frequency [Hz]
+16dB
0dB
–16dB
0
–5
–10
–15
Response [dB]
–20
–25
10 100 1k 10k 100k
Frequency [Hz]
VRC = 0dB
VRC = –8dB
VRC = –16dB
VRC = –24dB
Loudness characteristics
– 16 –
Page 17
CXA1946BQ/BR
Description of Operation
The CXA1946BQ/BR is a serial control electronic volume IC designed for use in audio systems.
The internal circuit of the IC consists of the following blocks:
1. Input selector
2. Volume
3. Loudness
4. Tone control
5. Fader
6. VCT buffer
7. Serial data I/O
8. Zero-cross detector (with timer)
9. Power-off mute
The operation of each block and notes on their use are described below.
Note that when the circuits for channels 1 and 2 are identical, the suffix “X” is added to pin names and device
names in order to distinguish between the two channels.
1. Input selector
There are two channels (stereo), each with four systems of input pins; the input selector selects one of
those input systems.
The gain between the input pins and the output pin of the input selector can be set independently for each
input system, except the gain for inputs 3 and 4 is common.
Determine the gain for each system through the settings of the feedback circuit constants as shown in Figs.
1 and 2. When each input gain is set to × 1, short INAOX and GAIN × 1,GAIN × 2,GAIN × 34.
The input impedance is 50kΩ (typ.) for each input.
The output impedance for INAO1 and INAO2 is low impedance (roughly 0Ω). The gain is not affected by the
load impedance.
VCT
GAINX2
GAINX1 GAINX34 INAOX
INX4
50k
INX3
INX2
INX1
50k
50k
50k
Fig. 1. Input Selector (1)
– 17 –
Page 18
VCT
GAINX2
GAINX1 GAINX34 INAOX
INX4
50k
INX3
50k
INX2
50k
INX1
50k
CXA1946BQ/BR
Fig. 2. Input Selector (2)
2. Volume
The volume circuit consists of two sections, an 8dB/step section and a 1dB/step section, as shown in Fig. 3.
This circuit also serves as a balance control because the volume for channel 1 and channel 2 can be set
independently.
To mute the output signal, send –∞dB data.
The input impedance is 9.5kΩ (typ.) for VRIN1 and VRIN2.
The output impedance for VOUT1 and VOUT2 is low impedance (roughly 0Ω). The volume step width and
gain are not affected by the load impedance.
3. Loudness
The configuration of the loudness circuit is shown in Fig. 3. CLDHCX and CLDLCX are connected externally,
and the loudness frequency characteristics are determined by these constants. The relationships between
CLDHCX/CLDLCX and the frequency characteristics are as follows:
1/fL = 2πCLDLCXR1
1/fH = 2πCLDHCXR2
The loudness characteristics are not affected by the load impedance of VOUT1 and VOUT2.
Loudness is turned on and off by serial data bit D5.
fH
VOUTX
C
LDHCX
0.0022µ
LDLCX
C
0.047µ
VRINX (input impedance 9.5kΩ)
20k
20k
8.92k
LDHCX
R2
4.98k
25.7k
OFF
ON
LOUD
R1
6.18k
Total 40k
fL
Loudness frequency
characteristics
LDLCX
Loudness Volume
Fig. 3. Volume and Loudness
– 18 –
Page 19
CXA1946BQ/BR
4. Tone control
The configuration of the tone control circuit is shown in Fig. 4. CTCLCX2 and CTCHCX are connected
externally, and the tone control frequency characteristics can be changed by changing these constants.
The relationships between CTCLCX2/CTCHCX and the frequency characteristics are as follows:
1/fL = 2πCTCLCX2 (R3//R4)
1/fH = 2πCTCHCXR5
The maximum bass boost and cut can be made smaller than in the Application Circuit by connecting an
external resistance to the TCLCX1 pin in series, or else connecting an external resistance to CTCLCX2 in
parallel. (See Fig. 5.) Furthermore, the maximum treble boost and cut can be made smaller than in the
Application Circuit by connecting an external resistance to CTCHCX in series. (See Fig. 6.) However, when
these methods are used, variations in the absolute value of the CXA1946B internal resistance (±20% max.)
and in the external resistance will cause variations in the tone control characteristics. Set these constants
after studying all considerations carefully. Note that when the method illustrated in the Application Circuit is
used, variations in the internal resistance of the CXA1946B have no effect on the tone control
characteristics.
The input impedance is 19kΩ (typ.) for TIN1 and TIN2.
The output impedance for TCO1 and TCO2 is low impedance (roughly 0Ω). The tone step width and gain
are not affected by the load impedance.
12k
TINX
input impedance
19kΩ
Tone control frequency
TCLCX1 TCLCX2
characteristics
C
TCLCX2
0.39µ
TCOX
R4
8k
R3
8k
10k
fHfL
10k
TCHCX
R5
5k
10k10k
BASS
TREBLE
ON
OFF
ON
OFF
ON
OFF
ON
OFF
14.1k
CUT
BOOST
CUT
BOOST
14.1k
12k
14.1k
14.1k
TCHCX
C
0.0027µ
Fig. 4. Tone Control
– 19 –
Page 20
CXA1946BQ/BR
TINX
TCLCX2
RexA
TCLCX1
R4
8k
(A)
C
TCLCX2
R3
8k
Fig. 5. Method for Reducing Bass Boost/Cut
10k10k
10k
10k
R3
5k
TCLCX1
TCLCX2
C
R4
(B)
RexB
TCLCX2
8k
R3
8k
TCHCX
RexC
TCHCX
C
Fig. 6. Method for Reducing Treble Boost/Cut
5. Fader
The configuration of the fader circuit is shown in Fig. 7. The fader operates by specifying the amount of
attenuation for either the front or rear output signal and by specifying which output signal (front or rear) is to
be attenuated.
The input impedance is 24kΩ (typ.) for FDIN1 and FDIN2.
The output impedance for FNTO1, FNTO2, REO1, and REO2 is low impedance (roughly 0Ω). The gain and
fader step width are not affected by the load impedance.
FDINX (input impedance 24kΩ)
Center
ATT
Center
FNTOX
REOX
ATT
Fig. 7. Fader
– 20 –
Page 21
CXA1946BQ/BR
6. VCT buffer
The internal circuit for the VCT pin is shown in Fig. 8.
This circuit generates the electric potential for the center between Vcc and GND (Vcc/2). The IC internal
operation reference potential is equal to the output potential of VCT buffer. The impedance for the VCT pin
(Pin 17) is high since it is connected to a bypass capacitor. Add an external buffer when using the electric
potential of the VCT pin as the external reference potential for the CXA1946.
VCC
100k
VCT
10µ
100k
Fig. 8. VCT Buffer
7. Serial data I/O
The serial data has a 32-bit structure as indicated in the specifications. Data input is conducted using three
inputs: DATA, CLK, and CE. DATA is shifted in the CXA1946B internal shift register at the rising edge of
CLK. The data in the shift register is latched at the falling edge of CE. Refer to this specification for details
on the timing.
The CXA1946B does not have a reset (initialize) pin. The internal shift register and latch are reset
automatically when power is first supplied to the IC. To execute a reset at other times, send the data
(statuses after reset ) shown in the item "RESET" of this specification to the CXA1946B.
8. Zero-cross detector (with timer)
Using the zero-cross detector, the internal latch data is overwritten the first time the input signal becomes
roughly 0 after serial data is sent (after CE goes low). This operation reduces noise when overwriting data.
Although there are usually no problems when a normal audio signal is input, in rare cases there may be
nothing except a large-amplitude input signal of the high band, causing the slew rate to become abnormally
high; the zero-cross detection signal is not output in such a case because the zero-cross detector response
speed is too slow. Another rare situation would be that the zero-cross detection signal is output very
infrequently because the input signal frequency is extremely low. In these types of instances, it is
conceivable that the internal latch data will not be overwritten after data is sent, or that it will take much time
until the data is overwritten. Therefore, to an external observer it will appear that the data is not being
overwritten regardless of the fact that data is being sent.
As a countermeasure, the IC is designed to permit the internal latch data to be forcibly overwritten if the
zero-cross detection signal is not output within a certain waiting period after the data is sent (after CE goes
low). This function is called the “timer.” If the zero-cross detection signal is output within a certain waiting
period, the internal latch data is overwritten in synchronization with the zero-cross of the input signal.
The waiting period mentioned above can be changed according to the value of the external capacitor
connected to the TIMER pin. When the value of the capacitor is 0.01µF, the waiting period is approximately
500µs.
9. Power-off mute
When Vcc goes below 5V, the output stage bias of the fader output pins FNTO1, FNTO2, REO1, and
REO2 is turned off and the pins go to high impedance. This operation prevents popping noises caused by
the output pin potential deviating from Vcc/2 when the power is turned off.
– 21 –
Page 22
CXA1946BQ/BR
Connections and Characteristics of Each Block
In the Application Circuit, the signal path goes from the input selector to the volume (+loudness) to the tone
control to the fader. The sequence of the blocks in the signal path can be changed because the I/O pins for
each block are independent of each other. For example, it is possible to switch the sequence of the volume
circuit and the tone control so that the signal path goes from the input selector to the tone control to the volume
(+loudness) to the fader. When this connection method is used, the noise voltage in the fader output can be
reduced in actual use because the noise and signal up to the tone control are attenuated by the volume.
However, because the maximum output amplitude of the tone control circuit is limited by the supply voltage,
care should be given to the setting of the input signal level.
Although blocks in the Application Circuit are linked either by coupling capacitors or by direct connection, it is
also possible to insert external circuits between blocks. In this case, the gain will change according to the input
impedance of the following block and the impedance of the external circuit. In addition, the input impedance of
each block can vary by ±20% due to the characteristics of the IC. Consequently, the overall gain also varies.
Give careful consideration to the effects of this variation when setting the constants. The step widths (control
characteristics) of the volume, tone control, and fader are not affected.
Timing Chart
CE
DATA
CLK
CE
t1 tck tsu th t2 tL
t
1 ≥ 0.5µs
t2 ≥ 0.5µs
tck ≥ 1.0µs
tsu ≥ 0.5µs
th ≥ 0.5µs
ce ≥ 4.0µs
t
D1 D2 D30 D31 D32 Invalid
L ≥ tT + 0.5µs
t
(tT is the maximum value for the timer operation time)
tce
Timer Waiting Period Setting Chart (Vcc = 6 to 12V, operating temperature = –35 to +85°C)
TIMER pin
capacitance C
C = 100pF
C = 0.001µF
C = 0.01µF
C = 0.1µF
C = 1µF
C = 10µF
Waiting peroid
Min. Typ. Max.
3µs
30µs
300µs
3ms
30ms
300ms
5µs
50µs
500µs
5ms
50ms
500ms
90µs
900µs
9ms
90ms
900ms
9µs
– 22 –
Page 23
Package Outline Unit: mm
CXA1946BQ/BR
CXA1946BQ
48PIN QFP (PLASTIC)
15.3 ± 0.4
+ 0.4
12.0 – 0.1
2536
37
48
112
0.8 0.3 – 0.1
SONY CODE
EIAJ CODE
JEDEC CODE
+ 0.15
QFP-48P-L04
∗QFP048-P-1212-B
24
13
M
± 0.12
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
+ 0.1
0.15 – 0.05
0.15
+ 0.2
0.1 – 0.1
EPOXY RESIN
SOLDER / PALLADIUM
PLATING
COPPER / 42 ALLOY
0.7g
13.5
0.9 ± 0.2
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
CXA1946BR
36
37
48
1
0.5 ± 0.08
SONY CODE
EIAJ CODE
JEDEC CODE
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗ 7.0 ± 0.1
25
12
+ 0.08
0.18 – 0.03
0.1 ± 0.1
0° to 10°
DETAIL A
LQFP-48P-L01
LQFP048-P-0707
24
A
13
(0.22)
+ 0.2
1.5 – 0.1
0.5 ± 0.2
NOTE: Dimension “∗” does not include mold protrusion.
(8.0)
+ 0.05
0.127 – 0.02
0.1
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER/PALLADIUM
42/COPPER ALLOY
0.2g
0.5 ± 0.2
PLATING
– 23 –
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