Page 1
CXA1854AR
For the availability of this product, please contact the sales office.
Decoder/Driver/Timing Generator for Color LCD Panels
Description
The CXA1854AR is an IC designed exclusively to
drive color LCD panels LCX009AK/AKB/LCX005BK/
BKB. This IC greatly reduces the number of circuits
and parts required to drive LCD panels by
incorporating RGB decoder functions for video
signals, driver functions, and a timing generator for
driving panels onto a single chip.
64 pin LQFP (Plastic)
Features
• Color LCD panels
LCX009AK/AKB/LCX005BK/BKB driver
• Both NTSC/PAL compatible
• Supports composite inputs, Y/C inputs and Y/color
difference inputs
• Band-pass filter, trap and delay line
• Sharpness function
• 2-point γ compensation circuits
• R, B output delay time adjustment circuit
(supports both right and left inversion)
• Polarity reversed circuit / line inverted mode
• Supports external RGB input
• Supports line inversion
• Supports AC drive for LCD panel during no signal
Applications
• Color LCD viewfinders
• Liquid crystal projectors
• Industrial monitors
Structure
Bipolar CMOS IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VCC1 – GND 6 V
• Supply voltage VCC2 – GND 14 V
• Supply voltage VDD – VSS 6V
•Analog input pin voltage
VINA –0.3 to VCC1V
•Digital input pin voltage
VIND –0.3 to VDD + 0.3 V
• Operating temperature range
Topr –15 to +70 °C
• Storage temperature range
Tstg –40 to +150 °C
• Allowable power dissipation
PD (Ta ≤ 70°C) 400 mW
Operating conditions
• Supply voltage VCC1 – GND 4.6 to 5.3 V
• Supply voltage VCC2 – GND 11.0 to 13.0 V
• Supply voltage
LCX009 mode VDD – VSS 4.5 to 5.5 V
LCX005 mode VDD – VSS 2.7 to 5.5 V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E95X01A73
Page 2
Block Diagram
CXA1854AR
B-YIN
R-YIN
COUT
HUE/RST
COLOR
XVXO
R-BRT
B-BRT
RGB-GAIN
GAMMA2
GAMMA1
BRIGHT
CONTRAST
CIN
R-GAIN
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
REG
48
REG.
REGV
VXO HUE
COLOR
CONT
BPF
ACC AMP
BLKLIM
46
KILLER
XCLR
2
CC
V
45
1
CC2
V
2
FB B
44
PIC CONT
AGC
DL 2
DL 1TRAP
B OUT
43
DEMOD
LPF
MATRIX
CONTRAST
RGB
SUB
CONTRAST
EXT SW
42
FB G
FB R
G OUT
40
POL SW
SUB
BRIGHT
RGB GAIN
GAMMA
BRIGHT
S/H
HALF-H
KILLER
H-SYNC DET
H-SKEW DET
R OUT
39
bufbufbuf
38
V-POS
RESET GEN
V-CTL
COUNTER
V-CTL
DECODER
AUX-V
COUNTER
FRP
SH1
SH2
SH3
SH4
1
CC
V
47
+5V +12V +5VGND2
INT/EXTCLAMP
PAL ID
PAL SW
RESET
APC
PS
ACC DET
FILT CAL
AGG DET
GND2
37
V-SYNC SEP
TEST8
FIELD & LINE
TEST7
35
36
V-POS
COUNTER
H-CTL
DECODER
DECODER
PLL
COUNTER
CTL
PULSE GEN
V-TIMING
MASTERCKSUB
TEST6
RGT
34
EQP
BGP
CLP
BLK
H-POS
COUNTER
DECODER &
H-TIMING
PULSE GEN
PAL PULSE
ELIM &
MODE SEL
CK
1/7
3341
DD
V
TEST
S/R
TEST5
32
VD
31
HD
30
HCK1
29
HCK2
28
HST1
27
TEST4
26
CLR
25
EN
24
VCK1
23
VCK2
22
VST1
21
TEST3
20
SLCK
19
TEST0
18
B-GAIN
EXT-G
PLL PHASE
11
EXT-B
COMP
12
RPD
TEST1
17
V
SS
13
14
15
SS
CKI
V
CKO
16
TEST2
SYNC SEP
64
YC/YRB/COMP
6
GND1
MODE
SELECT
7
MODE1
8
MODE2
SPAL/DPAL/NTSC
9
10
EXT-R
H. FILTER
1
SYNCIN
CLAMP
2
YIN
3
AGCADJ
4
AGCTC
GND1
5
PICT
– 2 –
Page 3
CXA1854AR
Pin Description (H: Pull up, M: Intermediate setting, L: Pull down)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Symbol I/O Description
I
SYNC IN
Y IN
AGCADJ
AGCTC
PICT
GND1
MODE1
MODE2
EXT-R
EXT-G
EXT-B
RPD
VSS
CKI
CKO
Sync input
I
Y signal input
I
AGC level adjustment
O
AGC time constant
I
Y signal frequency characteristics adjustment
Analog 5V GND
I
Switches between NTSC (H), DPAL∗(M) and SPAL∗(L)
I
Switches between composite (H), Y/color difference (M) and YC input (L)
I
External digital input R (input conditions noted separately)
I
External digital input G (input conditions noted separately)
I
External digital input B (input conditions noted separately)
O
Phase comparator output
Digital GND
I
Oscillation cell input
O
Oscillation cell output
Input pin for
open status
M
M
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TEST2
TEST1
TEST0
SLCK
TEST3
VST1
VCK2
VCK1
EN
CLR
TEST4
HST1
HCK2
HCK1
HD
VD
TEST5
I
Test
I
Test
I
Test
I
Switches between LCX005BK (H) and LCX009AK (L)
O
Leave this pin open.
O
V start pulse 1 output
O
V clock pulse 2 output
O
V clock pulse 1 output
O
EN pulse output
O
CLR pulse output
O
Leave this pin open.
O
H start pulse 1 output
O
H clock pulse 2 output
O
H clock pulse 1 output
O
HD pulse output
O
VD pulse output
I
Leave this pin open.
L
L
L
L
L
∗
DPAL supports demodulation methods which use an external delay line during demodulation; SPAL supports
methods which internally process chroma demodulation.
– 3 –
Page 4
CXA1854AR
Pin
No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Symbol I/O Description
VDD
RGT
TEST6
TEST7
TEST8
GND2
R OUT
FB R
G OUT
FB G
B OUT
FB B
VCC2
BLKLIM
VCC1
Digital 5V power supply
I
Switches between Normal scan (H) and Reverse scan (L)
I
Leave this pin open.
I
Leave this pin open.
I
Leave this pin open.
Analog 12V GND
O
R output
I
R signal DC voltage feedback input
O
G output
I
G signal DC voltage feedback input
O
B output
I
B signal DC voltage feedback input
Analog 12V power supply
I
Black peak limiter level adjustment
Analog 5V power supply
Input pin for
open status
H
H
H
H
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
REG
B-YIN
R-YIN
COUT
HUE/RST
COLOR
XVXO
R-BRT
B-BRT
RGB-GAIN
GAMMA2
GAMMA1
BRIGHT
CONTRAST
CIN
R-GAIN
B-GAIN
O
Constant voltage capacitor connection
I
B-Y demodulator input (or B-Y/color difference signal input)
I
R-Y demodulator input (or R-Y/color difference signal input)
O
Chroma signal output (for PAL 1HDL)
I
Hue adjustment/system reset
I
Color adjustment
I
VXO crystal oscillator connection
I
R brightness adjustment
I
B brightness adjustment
I
RGB gain adjustment
I
γ 2 adjustment
I
γ 1 adjustment
I
Brightness adjustment
I
Contrast adjustment
I
Chroma signal input
I
R gain adjustment
I
B gain adjustment
– 4 –
Page 5
Analog Block Pin Description
CXA1854AR
Pin
No.
Symbol Pin voltage Equivalent circuit Description
1 SYNC IN
2 YIN 3.2V
CC1
V
1
GND1
V
GND1
CC1
2
200
50p
1k
Sync input.
Normally inputs the Y signal.
The standard signal input level
is 0.5Vp-p (up to 100% white
level from the sync chip).
Y signal input.
The standard signal input level
is 0.5Vp-p (up to 100% white
level from the sync chip).
Input at low impedance (75Ω or
less).
50µA
VCC1
3 AGCADJ VCC1/2 AGC gain adjustment pin.
4 AGCTC AGC detection filter connection.
5 PICT VCC1/2
3
GND1
VCC1
4
GND1
CC1
V
5
40k
50µA
20k
47k
2k
2.5V
1k
1k
Adjusts frequency
characteristics of luminance
signal.
Increasing the voltage
GND1
50µA
2.5V
emphasizes contours.
– 5 –
Page 6
CXA1854AR
Pin
No.
Symbol Pin voltage Equivalent circuit Description
9 EXT-R
10 EXT-G
11 EXT-B
39 R OUT
41 G OUT
VCC2
2
VCC1
9
10
11
GND1
CC2
V
39
41
43
200
50
50
External digital signal input.
There are two threshold
values: Vth1 (approximately
1.2V) and Vth2 (approximately
2.2V). When one of the EXTRGB signals exceeds Vth1, all
of the RGB outputs go to
black level (black side clip
level); when an input exceeds
Vth2, only the corresponding
output goes to white level
(white side limiter level).
RGB primary color signal
output.
43 B OUT
40 FB R
42 FB G
44 FB B
46 BLKLIM
GND2
CC2
V
40
42
44
GND2
V
CC1
46
GND1
2k
2k
Smoothing capacitor
connection for the feedback
circuit of RGB output DC level
control.
Use a low-leakage capacitor
because of high impedance.
50k
Sets the RGB output amplitude
(black-black) clip level.
48 REG 4.2V
VCC1
48
GND1
60k
40k 40k
– 6 –
Smoothing capacitor
connection for the internally
generated constant voltage
source circuit.
Connect a capacitor of 1µF or
more.
Page 7
CXA1854AR
Pin
No.
Symbol Pin voltage Equivalent circuit Description
49 B-YIN
50 R-YIN
51 COUT 2.3V
V
CC1
49
50
GND1
VCC1
51
GND1
2k
50µA
200
50µA
Color difference demodulation
circuit inputs during DPAL
mode.
Leave this pin open for NTSC.
Color difference signal is input
respectively when Y/color
difference input. (Standard
input is 0.15Vp-p.)
At this time, the bias is 3.5V.
Color adjusted chroma signal
is output.
When taking the chroma
signal, connect to GND with a
load resistor (approximately
5kΩ).
VCC1
6k
52
HUE/RST
3.2V
53 COLOR 3.2V Color adjustment.
54 XVXO 3.5V Crystal oscillator connection.
52
GND1
VCC1
53
GND1
VCC1
54
100k
12k
3.2V
100k
25k
3.2V
2k
5p
50µA
5p
50µA
500
Color phase adjustment pin
during NTSC.
Use for detective axis
adjustment of the R-Y/B-Y
axes during SPAL.
Also doubles as the reset pin.
The system is reset when this
pin is connected to GND.
GND1
– 7 –
Page 8
CXA1854AR
Pin
No.
Symbol Pin voltage Equivalent circuit Description
55 RBRT
56 BBRT
57
RGB-GAIN
VCC1/2
VCC1/2
VCC1
55
56
GND1
VCC1
57
GND1
47k
47k
3k
3k
Fine adjustment for R and B
signal brightness.
2.5V
Adjusts RGB output amplitude
gain.
2.5V
58 GAMMA2 VCC1/2
59 GAMMA1 VCC1/2
60 BRIGHT VCC1/2
VCC1
58
GND1
VCC1
59
GND1
VCC1
60
GND1
47k
47k
47k
3k
3k
4k
Adjusts voltage gain change
point γ 2.
2.5V
Adjusts voltage gain change
point γ 1.
2.5V
RGB output brightness
adjustment. It does not
influence the γ compensation
curve.
2.5V
– 8 –
Page 9
CXA1854AR
Pin
No.
61
CONTRAST
62 CIN
Symbol Pin voltage Equivalent circuit Description
VCC1
VCC1/2 Contrast adjustment.
61
GND1
VCC1
62
47k
4k
2.5V
20k
500
100µA 50µA
15p
Video signal input when using
composite input.
Chroma signal input when
using Y/C input.
Leave this pin open when
Y/color difference input.
GND1
63 R-GAIN
64 B-GAIN
VCC1/2
VCC1
63
64
GND1
47k
3k
Fine adjustment for R and B
signal contrast.
2.5V
– 9 –
Page 10
CXA1854AR
Setting Conditions for Measuring Electrical Characteristics
When measuring the DC characteristics, the TG block must be horizontally synchronized by performing Setting 2.
Setting 2 must also be performed when measuring the AC characteristics. When measuring items with bands
greater than 2MHz such as the Y frequency response or sharpness characteristics, settings 1 and 3 must also
be performed and measurements made with the sample-and-hold circuit set to through status.
Setting 1. System reset
After turning on the power, set SW52 to ON and start up V52 from GND in order to activate the
timing controller system reset. (See Fig. 1-1.)
Setting 2. Horizontal AFC adjustment
Input SIG6 (VL = 0mV) to (A) and adjust VR12 so that WL and WH of the TP12 output waveform are
the same. (See Fig. 1-2.)
Setting 3. S/H off
Input the signals shown in Fig. 1-3 to Pins 16, 17, 18 and 19 in order to set the sample-and-hold
circuit to through status.
VDD (VCC1)
V52 (RESET)
Fig. 1-1. System reset Fig. 1-2. Horizontal AFC adjustment
Pin 19
Pin 18
Pin 17
TR
R > 10µs
T
SIG6
TP12
WS
WL
WH
WL = WH
VDD
GND
V
DD
GND
DD
V
GND
Pin 16
VDD
GND
Fig. 1-3. S/H off input pattern
– 10 –
Page 11
CXA1854AR
Electrical Characteristics – DC Characteristics (1)
Unless otherwise specified, Setting 2 and the following setting conditions are required.
VCC1 = 5.0V, VCC2 = 12.0V, GND1 = GND2 = GND, VDD = 5.0V, VSS = GND
V3, V5, V46, V55, V56, V57, V58, V59, V60, V61, V63, V64 = 2.5V
V52, V53 = 3.2V
SW3, SW5, SW46, SW52, SW53, SW55, SW56, SW57, SW58, SW59, SW60, SW61, SW63, SW64 = ON
Set SW7, SW8, SW9, SW10, SW11 and SW19 are setting A.
Item Symbol Conditions Min. Typ. Max. Unit
Power supply characteristics
Input SIG5 to (A) and SIG3 (0dB) to (B).
Current
consumption V
CC1
ICC11
I
CC12
ICC13
Measure the I
Input SIG5 to (A) and SIG3 (0dB) to (B).
Set SW8 to C.
Measure the I
Input SIG5 to (A) and SIG5 to (F) and (G).
Set SW8 to B.
Measure the I
CC1 current value.
CC1 current value.
CC1 current value.
Y/color difference input mode
COMP input mode
Y/C input mode
35
34
32
44
42.5
40
53
51
48
mA
mA
mA
Current
consumption V
Current
consumption V
CC2
DD
CC2
I
IDD1
I
DD2
IDD3
Input SIG5 to (A) and SIG3 (0dB) to (B).
Measure the I
CC2 current value.
Input SIG5 to (A) and SIG3 (0dB) to (B).
Measure the I
DD current value.
Input SIG5 to (A) and SIG3 (0dB) to (B).
Set SW19 to B.
Measure the I
DD current value.
Input SIG5 to (A) and SIG3 (0dB) to (B).
Set SW19 to B.
Measure the I
DD current value.
LCX009 mode
LCX005 mode
V
DD = 3.0V
LCX005 mode
3
5.5
7
10.5
5
2
8
mA
14
mA
8
10.5
3
4.5
mA
mA
– 11 –
Page 12
Item Symbol Conditions Min. Typ. Max. Unit
Digital block I/O characteristics
∗
Input current 1
Input current 2
II1
II2
Input pin with pull-up resistor
VIN = VSS
Input pin with pull-down resistor
VIN = VDD
1
∗
2
VDD = 5.0V
VDD = 3.0V
VDD = 5.0V
VDD = 3.0V
–240
–144
40
24
–100
–60
100
60
CXA1854AR
–40
µA
–24
240
µA
144
High level output
voltage
Output pins except
CKO and RPD
Low level output
voltage
Output pins except
CKO and RPD
High level output
voltage
CKO pin
Low level output
voltage
CKO pin
High level output
voltage
RPD pin
Low level output
voltage
RPD pin
Output off leak
current
RPD pin
VOH1
VOL11
VOL12
VOH2
VOL2
VOH3
VOL3
IOFF
∗
IOH = –2mA
IOL = 2mA
IOL = 500µA
3
∗
3
∗
3
IOH = –3mA
IOL = 3mA
IOH = –1mA
IOL = 1.5mA
High impedance status
VOUT = V
SS or VOUT = VDD
DD = 5.0V
V
VDD = 3.0V
V
DD = 5.0V
VDD = 3.0V
VDD
–
V
–
0.5V
VDD
–1.2
–40
0.8
DD
1.0
DD
0.5
0.6
0.3
0.5VDD
1.0
40
V
V
V
V
V
V
V
µA
High level input
voltage
VIH
CMOS input cell
0.7VDD
SLCK and RGT pins
Low level input
voltage
VIL
CMOS input cell
0.3V
SLCK and RGT pins
Ternary input
switching
MDTHL
threshold voltage
(MODE1/MODE2)
∗1
Input pins with pull-up resistors: RGT, TEST6, TEST7, TEST8
∗2
Input pins with pull-down resistors: SLCK, TEST0, TEST1, TEST2, TEST5
∗3
Output pins except CKO and RPD: HD, VD, VST1, VCK1, VCK2, CLR, EN, HST1, HCK1, HCK2, TEST3,
MDTHH
MODE M → L level threshold
SW7, SW8 = B
MODE M → H level threshold
SW7, SW8 = B
0.2VDD
0.6VDD
0.3VDD
0.7VDD
0.4VDD
0.8VDD
TEST4
– 12 –
DD
V
V
V
V
Page 13
CXA1854AR
Electrical Characteristics – AC Characteristics (1)
Unless otherwise specified, Setting 2 and the following setting conditions are required.
Vcc1 = 5.0V, Vcc2 = 12.0V, GND1 = GND2 = GND, (VDD = 5.0V, VSS = GND)
V5, V55, V56, V57, V60, V61, V63, V64 = 2.5V V3, V58 = 0V V46, V59 = 5.0V
V52, V53 = 3.2V
SW3, SW5, SW46, SW52, SW53, SW55, SW56, SW57, SW58, SW59, SW60, SW61, SW63, SW64 = ON
Set SW7, SW8, SW9, SW10, SW11 and SW19 are setting A.
Unless otherwise specified, measure the non-reversed outputs for TP39, TP41 and TP43.
Item Symbol Conditions Min. Typ. Max. Unit
Y signal block
Video maximum
gain
Y signal frequency
Characteristics
Sharpness
characteristics
MAX
Sharpness
characteristics
MIN
GV
FCYYC
FCYCMN
FCYCMP
GSHPMXC
GSHPMXY
GSHPMNC
GSHPMNY
Input SIG5 to (A) and measure the ratio between the
output amplitude (white-black) and input amplitude at
TP41.
Assume the output amplitude at
TP41 when SIG2 (0dB, no burst,
100kHz) is input to (A) as 0dB. Vary
the frequency of the input signal to
obtain the frequency with an output
amplitude of –3dB. Settings 1 and 3
are required.
Assume the output amplitude at TP41 when SIG8
(100kHz) is input to (A) as 0dB. Obtain the output
amplitude ratio for the input SIG8 (2.0MHz).
V5 = 4.0V
Settings 1 and 3 are required.
Assume the output amplitude at TP41 when SIG8
(100kHz) is input to (A) as 0dB. Obtain the output
amplitude ratio for the input SIG8 (2.5MHz).
V5 = 4.0V, SW8 = C
Settings 1 and 3 are required.
Assume the output amplitude at TP41 when SIG8
(100kHz) is input to (A) as 0dB. Obtain the output
amplitude ratio for the input SIG8 (2.0MHz).
V5 = 0V
Settings 1 and 3 are required.
Assume the output amplitude at TP41 when SIG8
(100kHz) is input to (A) as 0dB. Obtain the output
amplitude ratio for the input SIG8 (2.5MHz).
V5 = 0V, SW8 = C
Settings 1 and 3 are required.
Y/C input,
SW8 = C
Composite input
(NTSC)
Composite input
(PAL), SW7 = C
Composite input
Y/C input
Composite input
Y/C input
13.5
5.0
2.5
3.0
7
10
16.5
12
16
–1
1
19.5
2
4
dB
MHz
MHz
MHz
dB
dB
dB
dB
– 13 –
Page 14
Item Symbol Conditions Min. Typ. Max. Unit
Adjust the output amplitude at TP41 when SIG1 (APL:
50%) is input to (A) to 1.5Vp-p with V61. Assume this as
APL = 90%
APL = 10%
AGC characteristics
GAPL90
GAPL10
0 dB, and obtain the TP41 output amplitude ratio when
input SIG1 (APL: 90%) is input.
V3 = 2.5V, V60 = 3.5V
Adjust the output amplitude at TP41 when SIG1 (APL:
50%) is input to (A) to 1.5Vp-p with V61. Assume this as
0dB, and obtain the TP41 output amplitude ratio when
input SIG1 (APL: 10%) is input.
V3 = 2.5V, V60 = 3.5V
–4
–2.5
1
2.5
CXA1854AR
dB
–1
dB
4
Contrast
characteristics
MAX
Contrast
characteristics MIN
Carrier leak
(residual carrier)
Y signal I/O delay
time
GCNTMX
GCNTMN
CRRLK
TDYYC
TDYCMN
TDYCMP
Input SIG5 to (A) and obtain the ratio between the TP41
output amplitude when V61 = 2.5V and the TP41 output
amplitude when V61 = 5V.
Input SIG5 to (A) and obtain the ratio between the TP41
output amplitude when V61 = 2.5V and the TP41 output
amplitude when V61 = 1V.
Input SIG3 (0dB) to (A) and (B). Adjust the chroma signal
phase so that the amplitude (black – white) at TP43 is at a
maximum. Using a spectrum analyzer, measure the input
and the 3.58MHz or 4.43MHz component, and obtain
CRRLK = 150mV × 10
∆d/20
using their difference ∆d.
SW7 = A for NTSC measurement, and C for PAL
measurement.
Input SIG6 (VL = 150mV) to (A).
Measure the delay time from the
rising edge of the input signal to the
rising edge of the non-reversed
output.
V5 = 2V
Y/C input
SW8 = C
Composite input
(NTSC)
Composite input
(PAL), SW7 = C
2
250
630
610
5
–10
400
780
760
–6
30
550
930
910
dB
dB
mVpp
ns
ns
ns
– 14 –
Page 15
Electrical Characteristics – AC Characteristics (2)
Item Symbol Conditions Min. Typ. Max. Unit
Chroma signal block
CXA1854AR
ACC amplitude
characteristics 1
ACC amplitude
characteristics 2
APC pull-in range
Color adjustment
characteristics MAX
Color adjustment
characteristics MIN
ACC1N
ACC1P
ACC2N
ACC2P
FAPCNU
FAPCND
FAPCPU
FAPCPD
GCOLMX
GCOLMN
Input SIG6 (VL = 0mV) to (A) and SIG3
(0dB/+6dB/–20dB, 3.58MHz burst/chroma
phase = 180°, or 4.43MHz burst/chroma
phase = ±135°) to (B). Measure the output
amplitude at TP51, assuming the output
corresponding to 0dB, +6dB and –20dB as
V0, V1 and V2, respectively.
ACC1 = 20log (V1/V0)
ACC2 = 20log (V2/V0)
Input SIG6 (VL = 0mV) to (A) and SIG3
(0dB, 3.58MHz burst/chroma phase = 180°,
or 4.43MHz burst/chroma phase = ±135°) to
(B), and measure the output amplitude at
TP43. Changing the SIG3 burst frequency,
mesure the frequency fl which TP43 output
changes (the killer mode is canceled).
(The crystal parallel floating capacitance is
2pF or less)
NTSC: FAPCN = fl – 3579545Hz
PAL: FAPCP = fl – 4433619Hz
Input SIG6 (VL = 0mV) to (A) and SIG3 (0dB, 3.58MHz
burst/chroma phase = 180°) to (B). Assume the chroma
amplitude when V53 = 3.2V, 5V and 2.1V as V0, V1
and V2, respectively, and calculate GCOLMX = 20log
(V1/V0) and GCOLMN = 20log (V2/V0).
NTSC
PAL
SW7 = C
NTSC
PAL
SW7 = C
NTSC
upper limit
CL = 20pF
NTSC
lower limit
CL = 20pF
PAL
upper limit
SW7 = C
CL = 16pF
PAL
lower limit
SW7 = C
CL = 16pF
–3 0 +3 dB
–3 0 +3 dB
–3 0 +3 dB
–3
350 Hz
350 Hz
0+3dB
–350 Hz
–350 Hz
3 5.5 dB
–20 –15 dB
HUE adjustment
range MAX
HUE adjustment
range MIN
Killer operation
input level
TNTMX
TNTMN
ACKN
ACKP
Input SIG6 (VL = 0mV) to (A) and SIG3 (0 dB) to (B).
Assume the phase at which the output amplitude at TP43
reaches a minimum when V53 = 3.2V, 5V and 1.6V as
θ0, θ1 and θ2, respectively, and calculate TNTMX
= θ1 – θ0 and TNTMN = θ2 – θ0.
Input SIG6 (VL = 0mV) to (A) and SIG3
(level variable, 3.58MHz burst/chroma
phase = 180°, or 4.43MHz burst/chroma
phase = ±135°) to (B), and measure the
output amplitude at TP43. Gradually reduce
the SIG3 amplitude and measure the level
at which the killer operation is activated.
NTSC
PAL
SW7 = C
30 deg
–30 deg
–36 –30 dB
–33 –27 dB
– 15 –
Page 16
Item Symbol Conditions Min. Typ. Max. Unit
Input SIG6 (VL = 0mV) to (A) and SIG3 (0dB, 3.58MHz)
0.63
Demodulation
output amplitude
ratio (NTSC)
Demodulation
output phase
difference (NTSC)
Demodulation
output amplitude
ratio (PAL)
VRBN
VGBN
θRBN
θGBN
VRBP
VGBP
to (B) and change the chroma phase. Assume the
maximum amplitude at TP39 as VR, the maximum
amplitude at TP41 as VG, and the maximum amplitude
at TP43 as VB, and calculate VRBN = VR/VB and VGBN
= VG/VB. V60 = 3.5V
Input SIG6 (VL = 0mV) to (A) and SIG3 (0dB, 3.58MHz)
to (B) and change the chroma phase. Assume the phase
at which the maximum amplitude at TP39, TP41 and
TP43 as θR, θG and θB, respectively, and calculate
θRBN = θR – θB and θGBN = θG – θB.
V60 = 3.5V
Input SIG6 (VL = 0mV) to (A) and SIG3 (0 dB, 4.43MHz)
to (B) and change the chroma phase. Assume the
maximum amplitude at TP39 as VR, the maximum
amplitude at TP41 as VG, and the maximum amplitude
at TP43 as VB, and calculate VRBP = VR/VB and VGBP
= VG/VB. V60 = 3.5V, SW7 = C
0.53
0.25
99
230
0.65
0.33
0.32
109
242
0.75
0.40
CXA1854AR
0.73
0.39
119
deg
254
deg
0.85
0.47
Demodulation
output phase
difference (PAL)
θRBP
θGBP
Input SIG6 (VL = 0mV) to (A) and SIG3 (0 dB, 4.43MHz)
to (B) and change the chroma phase. Assume the phase
at which the maximum amplitude at TP39, TP41 and
TP43 as θR, θG and θB, respectively, and calculate
θRBP = θR – θB and θGBP = θG – θB.
V60 = 3.5 V, SW7 = C
80
232
90
244
100
256
deg
deg
– 16 –
Page 17
Electrical Characteristics – AC Characteristics (3)
CXA1854AR
Item
Symbol Conditions Min. Typ. Max. Unit
RGB signal output characteristics
RGB output DC
voltage
RGB output DC
voltage difference
Amount of change
in brightness
Amount of change
in sub-brightness
Amount of change
in sub-contrast
VOUT
∆VOUT
BRTMX
BRTMN
SBBRT
SBCNT
Input SIG6 (VL = 0mV) to (A). Adjust V60 so that the
output (black-black) at TP41 is 9Vp-p and measure the
DC voltage at TP39, TP41 and TP43.
Input SIG6 (VL = 0mV) to (A). Adjust V60 so that the
output (black-black) at TP41 is 9Vp-p, measure the DC
voltage at TP39, TP41 and TP43, and obtain the
maximum difference between these values.
Input SIG6 (VL = 0mV) to (A) and measure the output
(black-black) at TP39, TP41 and TP43 when V60 = 0V.
Input SIG6 (VL = 0mV) to (A) and measure the output
(black-black) at TP39, TP41 and TP43 when V60 = 5V.
Input SIG6 (VL = 0mV) to (A) and measure the
difference between the outputs (black-black) at TP39 and
TP43 and the output (black-black) at TP41 when V55
and V56 = 1V and when V55 and V56 = 4V.
Input SIG5 to (A) and measure the difference between
the outputs (white-black) at TP39 and TP43 and the
output (white-black) at TP41 when V63 and V64 = 1V
and when V63 and V64 = 4V.
5.85
9.0
±2
±2
6.05
0
±4
6.25
100
3.0
V
mV
V
V
V
dB
Difference in RGB
reversed/
non-reversed gain
γ characteristics
γ gain
V γ 1 adjustment
variable range
V γ 2 adjustment
variable range
∆G (NR)
G γ 1
G γ 2
G γ 3
V γ 1MN
V γ 1MX
V γ 2MN
V γ 2MX
Input SIG5 to (A) and obtain the gain difference between
the non-reversed output amplitudes (white-black) and the
reversed output amplitudes at TP39, TP41 and TP43.
Input SIG9 to (A) and adjust the non-reversed output
amplitude (white-black) at TP41 to 4Vp-p with V61.
Calculate the following:
G γ 1 = 20log (VG1/0.0357)
G γ 2 = 20log (VG2/0.0357)
G γ 3 = 20log (VG3/0.0357)
(See Fig. 6 for definitions of VG1, VG2 and VG3.)
Input SIG4 to (A) and adjust the output amplitude (white-
black) at TP41 to 4Vp-p with V61 when V57 and V58
= 0V and V59 = 5V. Measure the point where the gain of
the non-reversed output at TP41 changes and the
voltage difference V γ 1 between this output and V
when V59 = 0V and when V59 = 2.7V. V γ 1MN when
V59 = 0V, and V γ 1MX when V59 = 2.7V (See Fig. 7.)
Input SIG4 to (A) and adjust the output amplitude (whiteblack) at TP41 to 4Vp-p with V61 when V57 and V58
= 0V. Measure the point where the gain of the
non-reversed output at TP41 changes and the voltage
difference V γ 2 between this output and V
V58 = 5V and when V58 = 1.5V. V γ 2MN when V58
= 5V and V γ 2MX when V58 = 1.5V. (See Fig. 7.)
CC2/2 when
CC2/2
–0.6
21.5
9.5
18.5
3.5
2.0
0
25.5
12.5
23.5
0.6
29.5
15.5
26.5
2.0
0.9
dB
dB
dB
dB
V
V
V
V
– 17 –
Page 18
Electrical Characteristics – AC Characteristics (4)
CXA1854AR
Item
Symbol Conditions Min. Typ. Max. Unit
Sync separation, TG block
Sync separation
input voltage
sensitivity
HD output delay
time
Horizontal pull-in
range
VSSEP
TDHDH
TDHDL
HPLLN
HPLLP
External I/O characteristics
External RGB
input threshold
voltage
VT1EXT
VT2EXT
Input SIG6 (VL = 0mV, WS = 4.7µs, VS variable) to (A) and
confirm that it is synchronized with the output at TP30.
Gradually reduce the VS of SIG6 from 143mV and obtain the
VS at which input and output become non-synchronized.
Input SIG6 (VL = 0mV, VS = 143mV, WS = 4.7µs) to (A)
and measure the delay time with the output at TP30.
TDHDH is from the falling edge of the input sync signal to
the rising edge of TP30, and TDHDL from the rising edge
of the input sync signal to the falling edge of TP30.
Input SIG6 (VL = 0mV, VS = 143mV, WS = 4.7µs,
horizontal frequency variable) to (A) and confirm that
it is synchronized with the output at TP30. Obtain the
frequency fH where the input and output are
synchronized by changing the horizontal frequency
of SIG6 from the non-synchronized condition.
HPLLN = fH – 15734, HPLLP = fH – 15625
Input SIG6 (VL = 0mV) to (A) and SIG7 (VL variable) to (C),
(D) and (E). Raise the amplitude from 0 V and assume the
voltage, where the outputs at TP39, TP41 and TP43 go to
black level as VT1EXT. Then raise the amplitude further and
assume the voltage where these outputs go to white level as
VT2EXT. SW9 = B, SW10 = B, SW11 = B
NTSC
PAL
SW7 = C
2.9
4.4
±500
±500
1.0
2.0
40
3.2
4.7
1.2
2.2
60
3.5
5.0
1.4
2.4
mV
µs
µs
Hz
Hz
V
V
Propagation delay
time between
external RGB
input and output
Black level voltage
during external
RGB input
White level voltage
during external
RGB input
TD1EXT
TD2EXT
EXTBK
EXTWT
Input SIG6 (VL = 0 mV) to (A) and SIG7 (VL = 3 V) to (C),
(D) and (E), and adjust the output amplitudes at TP39, TP41
and TP43 to 2.0V with V57. Measure the rise delay time
TD1EXTand the fall delay time TD2EXT.
SW9 = B, SW10 = B, SW11 = B (See Fig. 2.)
Input SIG6 (VL = 0mV) to (A) and SIG7 (VL = 1.7V) to
(C), (D) and (E), and measure the difference from the
black level of the outputs at TP39, TP41 and TP43.
SW9 = B, SW10 = B, SW11 = B
Input SIG6 (VL = 0mV) to (A) and SIG7 (VL = 2.7V) to
(C), (D) and (E), and measure the difference from the
black level of the outputs at TP39, TP41 and TP43.
SW9 = B, SW10 = B, SW11 = B
100
100
1.8
200
200
2.2
300
300
0
ns
ns
V
V
– 18 –
Page 19
Electrical Characteristics – AC Characteristics (5)
CXA1854AR
Item
Filter characteristics
F0BPFN
BPF center
frequency
F0BPFP
Amount of BPF
attenuation
Amount of TRAP
attenuation
R-Y, B-Y and LPF
characteristics
ATBPF
ATRAPN
ATRAPP
DEMLP
Symbol Conditions Min. Typ. Max. Unit
Input SIG6 (VL =0 mV) to (A) and SIG2 (0dB,
frequency variable) to (B). Obtain frequencies
fc1 and fc2 which reduce the output amplitude
by 3dB from the maximum output at TP51 by
changing the frequency, and calculate F0BPF
= (fc1 + fc2)/2. Settings 1 and 3 are required.
Input SIG6 (VL = 0mV) to (A) and SIG2
(0dB, frequency variable) to (B).
Assume TP51 when the center
frequency is input as 0dB and measure
the output level at TP51 when the
frequencies noted on the right are
input. Settings 1 and 3 are required.
Input SIG2 (0dB, 3.58MHz, 4.43MHz) to (A) and
measure the output at TP41 with a spectrum
analyzer. Assume the output during Y/C mode
(SW8 = A) as 0dB and measure the amount of
attenuation during COMP mode (SW8 = C).
Settings 1 and 3 are required.
Input SIG6 (VL = 0mV) to (A) and SIG2 (amplitude
100mV, frequency variable) to (F) and (G). Assume the
output amplitude at TP41 when 100kHz is input as 0dB,
and measure the frequency which attenuates the output
amplitude by –3dB.
NTSC
PAL
SW7 = C
NTSC
PAL
SW7 = C
2.78MHz
1.50MHz
3.23MHz
2.00MHz
NTSC
PAL
SW7 = C
3.33
4.13
–7
–8
0.6
3.58
4.43
–3
–23
–3
–20
0.8
3.83
4.73
–1
–15
–1
–15
–35
–35
1.2
MHz
MHz
dB
dB
dB
dB
dB
dB
MHz
Digital block I/O characteristics
Output transition
time (Note 3 pins)
Cross-point time
difference
HCK duty
tTLH
tTHL
∆T
DTYHC
Input SIG6 (VL = 0mV) to (A).
Load 30pF (See Fig. 4.)
V3, V46, V58, V59 = 2.5V
Input SIG6 (VL = 0 mV) to (A).
Load 30pF (see Fig. 5.) HCK1/HCK2
V3, V46, V58, V59 = 2.5V
Input SIG6 (VL = 0mV) to (A).
Measure the HCK1 and HCK2 output duty.
Load 30pF
V3, V46, V58, V59 = 2.5V
47
50
30
25
10
53
ns
ns
ns
%
– 19 –
Page 20
Description of Electrical Characteristics Measurement Methods
3V
SIG7
CXA1854AR
CMAX
GND
TP39, 41, 43
non-reversed output
TD1EXT TD2EXT
2V
1V
Fig. 2. Measuring the delay between external
RGB input and output
tTLH
tTHL
90%
10%
Chroma output
CMAX – 3dB
BPF center frequency
FOBPF =
fc1 fc2 f
Fig. 3. BPF center frequency
∆T
∆T
fc1 + fc2
2
50%
Fig. 4. Output transition time measurement
condition
White
Non-reversed output
Black
G γ1
White peak limiter
1/2 V
Gγ3
Gγ2
Input
CC
2
Fig. 5. Cross-point time difference measurement
condition
White
Vγ1
Non-reversed output
Black
Input
Vγ2
Fig. 6. γ characteristics measurement condition Fig. 7. γ adjustment variable range
1/2 V
CC
2
– 20 –
Page 21
Input Waveforms (1)
SG No. Waveform
APL variable, 5-step waveform
CXA1854AR
SIG1
SIG2
APL10%
APL50%
APL90%
0.15V
0.143V
Chroma signal:Burst, chroma frequency (3.579545MHz, 4.433619MHz)
Chroma phase and burst frequency variable
0.357V
0.143V
0.179V
0.357V
Sine wave video signal with burst.
(Amplitude and frequency are variable.)
0.15V
VSWEEP
SIG3
SIG4
SIG5
0.15V
0.143V
Lamp waveform
0.357V
0.143V
1H
5-step waveform
0.15V
0.143V
– 21 –
Page 22
Input Waveforms (2)
SG No. Waveform
SIG6
fH
VS
WS
5µs
VL amplitude is variable.
VS variable:143mV unless otherwise
VL
specified
WS variable:4.7µs unless otherwise
specified
fH variable: 15.734kHz (NTSC) or
15.625kHz (PAL) unless
otherwise specified
CXA1854AR
SIG7
SIG8
GND
SYNC
timing
0.175V
10-step waveform
30µs
0.075V
0.143V
VL
VL amplitude is variable.
Frequency variable
SIG9
0.357V
0.143V
– 22 –
Page 23
Electrical Characteristics Measurement Circuit
CXA1854AR
TP51
(G)
(F)
4.7k
V52
V53
V55
V56
V57
V58
V59
V60
V61
V63
V64
1µ
1µ
SW52
SW53
∗
1
SW55
SW56
SW57
SW58
SW59
SW60
SW61
SW63
SW64
(B)
CL
CC1
+V
+5V
47µ
49
B-YIN
50
R-YIN
51
COUT
52
HUE/RST
53
COLOR
54
XVXO
55
R-BRT
56
B-BRT
57
RGB-GAIN
58
GAMMA2
GAMMA1
59
60
BRIGHT
CONTRAST
61
62
CIN
63
R-GAIN
B-GAIN
64
0.1µ
34
RGT
TEST6
A
33
+VCC1
+5V
DD
V
47µ 0.1µ
TEST5
VD
HD
HCK1
HCK2
HST1
TEST4
CLR
EN
VCK1
VCK2
VST1
TEST3
SLCK
TEST0
TEST1
32
TP31
31
TP30
30
TP29
29
TP28
28
TP27
27
TP26
26
TP25
25
TP24
24
TP23
23
TP22
22
TP21
21
20
19
S18
18
S17
17
+5V
10k
B
A
10k
SW19
+VCC2
+12V
TP43
0.1µ
V46
47µ
SW46
1µ
A
A
46
47
REG
1
CC
V
45
BLKLIM
48
100p
1µ
330k
330k
43
44
FB B
42
B OUT
2
CC
V
TP39
TP41
100p
1µ
1µ
330k
40
41
FB R
FB G
G OUT
CXA1854AR
39
R OUT
100p
38
GND 2
37
36
TEST7
TEST8
35
YIN
SYNCIN
AGCADJ
∗1
Used crystal: KINSEKI CX-5F
1
(A)
2
SW3
V3
4
3
1µ
SW5
V5
Frequency deviation: within ±30ppm,
frequency temperature characteristics: within ±30ppm
During NTSC: 3.579545MHz, load capacity: 16pF, CL = 20pF
During PAL: 4.433619MHz, load capacity: 16pF, CL = 16pF
Measure under the condition that the crystal parallel floating
capacitance is within 2pF.
∗2
Vari-cap diode: 1T369 (SONY)
∗3
L value: 10µH when using the LCX005
4.7µH when using the LCX009
PICT
AGCTC
5
1µ
CA
GND1
6
SW7
B
MODE1
7
MODE2
EXT-R
9
8
SW9
(C) (D) (E)
AC
+5V
B
SW8
10k
3.3µ
EXT-G
10
SW10
EXT-B
11
SW11
RPD
12
1k
220p
3300p
13
33k
SS
V
CKI
14 15
0.01µ
TEST2
CKO
16
∗
3
L
∗
2
10k
S16
30p
+12V
47k
VR12
S19
– 23 –
Page 24
CXA1854AR
Description of Operation
The CXA1854AR incorporates the three functions of an RGB decoder block, an RGB driver block and a timing
generator (TG) block onto a single chip using BiCMOS technology. This section describes these functions and
their mutual relationship.
1) Description of the overall configuration
CXA1854AR
Corresponding LCD panels
SYNC
Y
C
R
G
B
RGB driver
R OUT
G OUT
B OUT
R-Y
B-Y
EXT-R
EXT-G
EXT-B
RGB decoder
SYNC
BLK
3.58MHz
or 4.43MHz
TG
RPD
VCO
FRP
CKI
HCK1
HCK2
HST1
VCK1
VCK2
VST1
CLR
ENB
LCX009AK/AKB
1.8cm 180K dots
LCX005BK/BKB
1.4cm 113K dots
2) Description of RGB decoder block operation
• Input mode switching
Signal input: Composite input, Y/C input and Y/color difference input switching is supported by Pin 8
(MODE2).
During composite input: The composite signal is input to Pins 1, 2 and 62.
During Y/C input: The Y signal is input to Pins 1 and 2, and the C signal to Pin 62.
During Y/color difference input: The Y signal is input to Pins 1 and 2, the R-Y signal to Pin 50, and the B-Y
signal to Pin 49.
(Chroma signal input (delay line output) is also used during PAL, but is
switched with the MODE1 setting.)
Recommended input signal voltages for each mode are shown in the Pin Description table. The Y signal
enters the TRAP circuit in composite mode, but through operation is performed in all other modes. Also, the
picture center frequency is set separately for composite input and Y/C input. (See the AC Characteristics
tables.)
• NTSC/PAL switching
NTSC and PAL (DPAL using an external delay line and SPAL) are switched by MODE1.
The built-in TRAP and BPF center frequencies are switched automatically according to the external crystal.
The center frequency is stabilized by the APC operation.
The R-Y demodulation detective axis is set internally to 90° during SPAL/DPAL. However, optimally adjust
the demodulation phase axis with the HUE adjustment pin.
• Video AGC/ACC circuit
Different AGC characteristics are obtained depending on the APL level of the luminance signal. The gain for
the luminance signal is adjusted with the average value. The sync amplitude of the burst signal output is
detected and used to adjust the ACC amplifier gain.
– 24 –
Page 25
CXA1854AR
• VXO, APC detection
The VXO local oscillation circuit is crystal oscillation circuit. The phases of the input burst signal and the VXO
oscillator output are compared in the APC detection block, and the detective output is used to form a PLL
loop that controls the VXO oscillation frequency, which means that the need for adjustments is eliminated. In
addition, the filter f0 is automatically adjusted, since the BPF and TRAP center frequency is feedback
controlled by VXO.
• Crystal oscillator for the XVXO pin connection
A 3.579545MHz crystal vibrator is connected to the XVXO pin during NTSC, and a 4.433619MHz crystal
vibrator during PAL. (Use KINSEKI CX-5F crystal vibrator with a load capacity of 16pF, frequency deviation
within ±30ppm, and frequency temperature characteristics within ±30ppm.)
• External inputs
Digital input with two thresholds is optimal for multiplexed character output to screens. When one of the RGB
inputs is higher than the lower threshold Vth1, all RGB outputs go to black level. When the higher threshold
Vth2 is exceeded, the output for only the signal in question goes to white level, while the other outputs
remain at black level. Externally connect a pull-down resistor (10kΩ or more).
3) Description of RGB driver block operation
• 2-point γ compensation circuit
In order to support the characteristic of LCD panels, the I/O characteristics are as shown in Fig. 1. The
voltage at γ gain change point A can be changed to that shown in Fig. 2 by adjusting the GAMMA1 pin (Pin
59). Also, the voltage at the γ 2 gain change point can be changed to that shown in Fig. 3 by adjusting the
GAMMA2 pin (Pin 58). The drive for LCD panels can be optimized by adjusting the overall gain with these
two gain change points and the RGB-GAIN pin (Pin 57).
Output
γ1
A
Input
Fig. 1
γ2
γ2
B
Output
γ1
A
Fig. 2
Input
B
Output
γ1
A
Input
Fig. 3
γ2
B
– 25 –
Page 26
CXA1854AR
• Sample-and-hold circuit
As the LCD panels sample-and-hold RGB signals simultaneously, RGB signal output from CXA1854R must
be synchronized to LCD panel drive pulses and sample-and-hold performed. Sample-and-hold is performed
by receiving the SH1 to SH4 pulses from the TG block. Since LCD panels perform color coding using an
RGB delta arrangement, each horizontal line must be compensated by 1.5 dots. This relationship is reversed
during right/left inversion. These timing pulses are generated by the TG block. Accordingly, RGB signals are
each sampled-and-held at the optimal timing and output by the RGB driver block.
Normal scan
B
R
G
S/H
S/H
S/H
SH1 SH3SH2 SH4
S/H
S/H
S/H
HCK
SH3
SH1
SH4
SH2
Reverse scan
HCK
SH2
SH1
SH4
SH3
Example of sample-and-hold circuits and S/H timing
• RGB output
RGB outputs (Pins 39, 41, and 43) are reversed each horizontal line by the FRP pulse supplied from the TG
block as shown in the figure below. Feedback is applied so that the center voltage of the output signal
matches the reference voltage (VCC2 + GND1)/2. In addition, the white level output is clipped by the Vsig
center voltage level, and the black level output is clipped by the limiter operation point that is adjusted at the
BLKLIM pin (Pin 46).
Video IN
FRP
RGB OUT
waveform
Black level limiter
(reversed side)
Vsig center voltage
Black level limiter
(non-reversed side)
– 26 –
Page 27
CXA1854AR
4) Description of TG block operation
This section describes the main functions of the TG block. (See individual description materials for details.)
• PLL circuit block
The PLL circuit block contains a phase comparator and frequency division counter circuit in order to
accurately align the timing, and performs PLL operation by externally connecting a VCO circuit. The average
voltage of the RPD pin (Pin 12) is locked roughly in the center by adjusting it to VDD/2. (See the attached
Application Circuit for the external circuit diagram. The 1T369 is recommended as the vari-cap diode used in
the VCO circuit.)
• SYNC detection circuit
This circuit separates the input SYNC signal into HSYNC and VSYNC, and recognizes the EVEN and ODD
fields and line numbers, etc. This circuit is necessary for the reasons (1) and (2).
(1) Shifts 1.5 dots each horizontal line for the RGB delta arrangement.
(2) Field recognition and accurate line number recognition for changing the eliminated lines for each EVEN
and ODD field and smoothing the picture during PAL.
In addition, if the SYNC waveform is not detected for more than a certain interval, the unit shifts automatically
to the free running state and the LCD panel is driven by self oscillation.
• Pulse generator block
The pulse generator circuit is synchronized to the previously mentioned SYNC detection circuit and PLL
circuit, and generates the pulses necessary to drive the LCD panel. (The main output pulse timings are
shown for each mode in a later section.) At the same time, the pulse generator circuit also generates the
BGP, BLK and other waveforms for the RGB decoder. Therefore, TG block PLL circuit operation is necessary
for RGB decoder functions.
• AC drive during no signal
HST1, HCK1, HCK2, FRP, VST1, VCK1, VCK2, HD and VD are made to run free so that the LCD panel is
AC driven even when there is no composite sync from the SYNC pin. During this time, the HSYNC
separation circuit stops and the PLL counter is made to run free. In addition, the reference pulse for
generates VD and VST, and the auxiliary V counter creates the reference pulse for generates VD and VST.
The VSYNC separation circuit is also stopped and The period of the V counter is designed to be 269H for
NTSC and 321H for PAL. When there is no VSYNC during 269H or 321H, the free running state is assumed.
In addition, RPD is kept at high impedance in order to prevent the AFC circuit from producing a phase error
due to phase comparison when there is no signal.
• AFC circuit (702/1050fh generation)
A fully synchronized AFC circuit is built in. PLL error signal is generated at the following timing. The phase
comparison output of the entire bottom of SYNC and the internal H counter becomes RPD. RPD output is
converted to DC error with the lag-lead filter, and then it changes the vari-cap diode capacitance and the
oscillation frequency is stabilized at 702fh in the LCX005BK/BKB and 1050fh in the LCX009AK/AKB.
SYNC
RPD
V
DD/2
0V
4.7µs
– 27 –
DD
V
SYNC center
Page 28
5) Description of TG block mode settings
• SLCK: Selects the driven LCD panel.
CXA1854AR
L
H
Selects the LCX009
Selects the LCX005
Note) The VCO frequency varies depending on the used panel.
VCO center frequency
LCX005 (702fh) LCX009 (1050fh)
NTSC
PAL
11.06MHz
10.97MHz
The external VCO circuit diagram is shown in the Application Circuit.
Recommended value: L value LCX005: 10µH, LCX009: 4.7µH
• RGT: Switches the horizontal scan direction.
H
L
Normal scan mode
Reverse scan mode
The HST1, HCK1 and HCK2 timing are switched by the RGT selection. The timing of the internal
sample-and-hold pulse is also switched at the same time. Connect the panel RGT pin directly, as it
does not support output.
NTSC
PAL
16.52MHz
16.41MHz
• MODE1/MODE2: Sets the type of video signal input.
MODE1 MODE2
H
M
L
NTSC
D-PAL
SPAL
H
M
Composite input
Y/color difference input
L
Y/C input
Signal input connections for each mode are noted in the RGB decoder block.
– 28 –
Page 29
CXA1854AR
LCX009AK/AKB and LCX005BK/BKB Color Coding Diagram
The delta arrangement is used for the color coding in the LCD panels with which this IC is compatible. Note
that the shaded region within the diagram is not displayed.
LCX009AK/AKB pixel arrangement
dummy1 to 4 HSW1 HSW2 HSW267 HSW268 dummy5 to 8
dummy1
dummy2
Vline1
Vline2
Vline3
Vline224
Vline225
dummy3
B R G B R G B R G B R G B
R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R
B R G B R G B R G B R G B R G B R
R G B R G B R G B R G B R G B R G
LCX005BK/BKB pixel arrangement
B R G
Display area
800 1314
827
R G B
Photo-shielding
area
G B R G
G B R GG B R G B RB RR G B R G
B RB RR G B R G
G B R GG
G B R GG B R G B RB RR G B R G
G B R GG B R G B RB RR G B R G
R
2
225 228
1
dummy1 HSW2
dummy1
dummy2
Vline1
Vline2
Vline3
Vline217
Vline218
dummy3
dummy4
HSW1 HSW3 HSW174 HSW175 dummy2 to 5
RGBRGBRGBRGBRGBR
BRGBRGBRGBRGBRGB
RGBRGBRGBRGBRGBR
BRGBRGBRGBRGBRGB
RGBRGBRGBRGBRGBR
BRGBRGBRGBRGBRGB
RGBRGBRGBRGBRGBR
BRGBRGBRGBRGBRGB
RGBRGBRGBRGBRGBR
BRGBRGBRGBRGBRGB
RGBRGBRGBRGBRGBR
Display area
521 133
537
Photo-shielding
area
2
218 222
2
– 29 –
Page 30
Application Circuit – NTSC (COMP and Y/C input)
CXA1854AR
CC1
+V
+5V
B-LIM
0.01µ
HUE
COLOR
R-BRT
B-BRT
RGB
GAM2
GAM1
BRT
CONT
R-G
B-G
AGC
PIC
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
1.7k
0.01µ
0.01µ
∗
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
47µ
49
50
51
52
53
20pF
54
1
55
56
57
58
59
60
61
62
63
64
0.1µ
B-YIN
R-YIN
COUT
HUE/RST
COLOR
XVXO
R-BRT
B-BRT
RGB-GAIN
GAMMA2
GAMMA1
BRIGHT
CONTRAST
CIN
R-GAIN
B-GAIN
Y/C COMP
COMP/Y INC IN
∗1
Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm,
frequency temperature characteristics: within ±30ppm
3.579545MHz, load capacity: 16pF
∗2
Vari-cap diode: 1T369 (SONY)
∗3
L value: 10µH when using the LCX005
4.7µH when using the LCX009
1µ
48
47
REG
SYNCIN
1
YIN
2
47µ
46
1
CC
V
3
CC2
+V
+12V
0.1µ
330k
45
44
2
CC
V
BLKLIM
AGCTC
AGCADJ
4
1µ1µ
1µ
FB B
PICT
5
Blue
43
6
330k
42
B OUT
GND1
Y/C
To panel
Green
1µ
330k
40
41
FB G
G OUT
CXA1854AR
EXT-R
MODE2
MODE1
9
8
7
10k
+VDD
+5V
10k
COMP
Red
1µ
39
FB R
10
10k
3.3µ
38
GND 2
R OUT
EXT-B
EXT-G
11
10k
37
TEST8
RPD
12
1k
220p
33k
3300p
36
TEST7
SS
V
13
35
TEST6
CKI
14 15
∗
0.01µ
34
2
10k
33
RGT
CKO
16
∗
3
L
30p
+VDD
+5V
47µ 0.1µ
DD
V
TEST2
+VCC2
+12V
TEST5
HCK1
HCK2
HST1
TEST4
CLR
VCK1
VCK2
VST1
TEST3
SLCK
TEST0
TEST1
47k
VD
HD
EN
17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
To panel
+V
+5V
005
009
DD
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 30 –
Page 31
Application Circuit – PAL (COMP and Y/C input)
CXA1854AR
B-LIM
HUE
COLOR
R-BRT
B-BRT
RGB
GAM2
GAM1
BRT
CONT
R-G
B-G
AGC
PIC
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
0.01µ
1.7k
0.01µ
0.01µ
16pF
∗
1
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
Y/C COMP
CC1
+V
+5V
47µ
49
B-YIN
50
R-YIN
51
COUT
52
HUE/RST
53
COLOR
54
XVXO
55
R-BRT
56
B-BRT
57
RGB-GAIN
58
GAMMA2
GAMMA1
59
60
BRIGHT
CONTRAST
61
62
CIN
63
R-GAIN
B-GAIN
64
0.1µ
COMP/Y INC IN
1µ
48
REG
SYNCIN
1
47
YIN
2
47µ
46
1
CC
V
3
CC2
+V
+12V
0.1µ
330k
45
44
2
CC
V
BLKLIM
AGCTC
AGCADJ
4
1µ1µ
1µ
FB B
PICT
5
Blue
43
B OUT
GND1
6
Y/C
To panel
Green
1µ
330k
330k
40
41
42
FB G
G OUT
CXA1854AR
MODE2
MODE1
9
8
7
10k
+VDD
+5V
COMP
Red
1µ
39
FB R
R OUT
EXT-G
EXT-R
10
10k
10k
3.3µ
38
GND 2
EXT-B
11
10k
37
TEST8
RPD
12
1k
220p
3300p
36
13
33k
35
TEST7
TEST6
SS
CKI
V
14 15
34
RGT
CKO
L
∗
2
10k
0.01µ
33
16
∗
30p
3
+VDD
+5V
47µ 0.1µ
DD
V
TEST2
+VCC2
+12V
TEST5
VD
HD
HCK1
HCK2
HST1
TEST4
CLR
EN
VCK1
VCK2
VST1
TEST3
SLCK
TEST0
TEST1
47k
30
25
22
19
17
32
31
29
28
27
26
24
23
21
20
18
To panel
+V
+5V
005
009
DD
1
∗
Used crystal: KINSEKI CX-5F
Frequency deviation: within ±30ppm,
frequency temperature characteristics: within ±30ppm
4.433619MHz, load capacity: 16pF
∗2
Vari-cap diode: 1T369 (SONY)
∗3
L value: 10µH when using the LCX005
4.7µH when using the LCX009
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 31 –
Page 32
Application Circuit – Y/color difference input (NTSC/PAL)
CXA1854AR
B-LIM
HUE
COLOR
R-BRT
B-BRT
RGB
GAM2
GAM1
BRT
CONT
R-G
B-G
AGC
PIC
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
47k
0.01µ
1.7k
0.01µ
R-YIN
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
0.01µ
B-YIN
0.01µ
0.01µ
1µ
1µ
47µ
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
+V
+5V
CC1
0.1µ
B-YIN
R-YIN
COUT
HUE/RST
COLOR
XVXO
R-BRT
B-BRT
RGB-GAIN
GAMMA2
GAMMA1
BRIGHT
CONTRAST
CIN
R-GAIN
B-GAIN
1µ
48
REG
SYNCIN
1
47
2
1
CC
V
YIN
47µ
46
3
+V
CC2
+12V
0.1µ
330k
45
44
2
CC
V
BLKLIM
AGCTC
AGCADJ
4
1µ1µ
1µ
FB B
PICT
5
Blue
43
6
To panel
330k
42
B OUT
GND1
Green
1µ
330k
40
41
FB G
G OUT
CXA1854AR
MODE2
MODE1
9
8
7
10k
Red
1µ
39
FB R
R OUT
EXT-G
EXT-R
10
10k
38
11
10k
37
GND 2
TEST8
EXT-B
RPD
12
1k
36
13
35
TEST6
TEST7
SS
CKI
V
14
34
15
33
RGT
CKO
16
∗
L
+VDD
+5V
DD
V
TEST2
2
47µ 0.1µ
TEST5
VD
HD
HCK1
HCK2
HST1
TEST4
CLR
EN
VCK1
VCK2
VST1
TEST3
SLCK
TEST0
TEST1
30
29
23
20
19
18
17
32
31
28
27
26
25
24
22
21
To panel
+VDD
+5V
005
009
∗
1
10k
0.01µ
30p
+VCC2
+12V
47k
∗1
Vari-cap diode: 1T369 (SONY)
∗2
L value: 10µH when using the LCX005
Y IN
PAL
+VDD
+5V
NTSC
10k
220p
33k
3300p
3.3µ
4.7µH when using the LCX009
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 32 –
Page 33
13fh
CXA1854AR
23.5fh
RGT: H (Normal scan) Composite In
4.7µs (52fh)
4.5µs (50fh)
702
18.5fh
EVEN FIELD
0.5µs (6fh)
3.0µs (33fh)
ODD LINE
2.0µs (22fh)
4.7µs (52fh)
653 663 673 683 693 1 11 21 31 41 51 61 71 81 91
CLK
SYNC
(BLK)
HD
HST
HCK1
HCK2
FRP
LCX005 Horizontal Direction Timing Chart (NTSC, PAL)
– 33 –
ODD FIELD
VCK1
(Internal pulse)
VCK2
CLR
EN
(PAL)
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
Page 34
13fh
CXA1854AR
22fh
RGT: H (Normal scan) Composite In
4.5µs (50fh)
4.7µs (52fh)
702
18.0fh
ODD FIELD
0.5µs (6fh)
3.0µs (33fh)
EVEN LINE
2.0µs (22fh)
4.7µs (52fh)
653 663 673 683 693 1 11 21 31 41 51 61 71 81 91
CLK
SYNC
(BLK)
HD
HST
HCK1
HCK2
FRP
LCX005 Horizontal Direction Timing Chart (NTSC, PAL)
– 34 –
EVEN FIELD
VCK1
(Internal pulse)
VCK2
CLR
EN
(PAL)
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
Page 35
13fh
CXA1854AR
23fh
RGT: L (Reverse scan) Composite In
4.7µs (52fh)
4.5µs (50fh)
702
18.0fh
EVEN FIELD
0.5µs (5fh)
3.0µs (34fh)
ODD LINE
2.0µs (22fh)
4.7µs (52fh)
653 663 673 683 693 1 11 21 31 41 51 61 71 81 91
CLK
SYNC
(BLK)
HD
HST
HCK1
HCK2
FRP
LCX005 Horizontal Direction Timing Chart (NTSC, PAL)
– 35 –
ODD FIELD
VCK1
(Internal pulse)
VCK2
CLR
EN
(PAL)
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
Page 36
13fh
CXA1854AR
24.5fh
RGT: L (Reverse scan) Composite In
4.5µs (50fh)
4.7µs (52fh)
702
18.5fh
EVEN FIELD
0.5µs (5fh)
3.0µs (34fh)
EVEN LINE
2.0µs (22fh)
4.7µs (52fh)
653 663 673 683 693 1 11 21 31 41 51 61 71 81 91
CLK
SYNC
(BLK)
HD
HST
HCK1
HCK2
LCX005 Horizontal Direction Timing Chart (NTSC, PAL)
– 36 –
ODD FIELD
FRP
VCK1
(Internal pulse)
VCK2
CLR
EN
(PAL)
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
Page 37
3.0H
3.0H3.0H
275
263
20H
243
Display start
12 3456 78
12 3 4
11.5H
CXA1854AR
EVEN FIELDODD FIELD
2013
Display start
12345678
12 34
12H
1
3.0H3.0H
20H
3.0H
505
HD
(VD)
SYNC
(BLK)
VST
VCK1
VCK2
FRP
LCX005 Vertical Direction Timing Chart (NTSC)
EN
HST
(Internal pulse)
– 37 –
CLR
FRP
(1F inversion)
FLD
(Internal pulse)
(Internal pulse)
Note) The second and fourth rows of the timing chart "VD" and "BLK" are pulses indicated as a reference and are not pulses output from pins.
VD
VRST
(Internal pulse)
Page 38
6, 8 decimation
2.5H
2.5H2.5H
32816
314
25H
Display start
3
12345678123456123
14H
CXA1854AR
EVEN FIELDODD FIELD
2.5H2.5H
288
26600
1
25H
Display start
4
3 412
1234 5678 123456123456 78 12345678
2
1
14.5H
2.5H
65432187
HD
(VD)
SYNC
(BLK)
VST
VCK1
VCK2
LCX005 Vertical Direction Timing Chart (PAL)
HST
FRP
(Internal pulse)
– 38 –
EN
(1F inversion)
CLR
FRP
VD
FLD
(Internal pulse)
(Internal pulse)
Note) The second and fourth rows of the timing chart "VD" and "BLK" are pulses indicated as a reference and are not pulses output from pins.
VRST
(Internal pulse)
Page 39
20.5fh
RGT: H (Normal scan) Composite In
CXA1854AR
12fh
43.5fh
0.5µs (8fh)
1050
4.7µs (78fh)
3.0µs (50fh)
ODD LINE
EVEN FIELDODD FIELD
2.0µs (33fh) 4.5µs (73fh)
4.7µs (78fh)
971 981 991 1001 1011 1021 1031 1041 1 11 21 31 41 51 61 71 81 91 101 111
CLK
SYNC
(BLK)
HD
HST
HCK1
HCK2
LCX009 Horizontal Direction Timing Chart (NTSC, PAL)
– 39 –
FRP
VCK1
(Internal pulse)
VCK2
CLR
EN
(PAL)
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
Page 40
19fh
CXA1854AR
12fh
43.0fh
RGT: H (Normal scan) Composite In
4.7µs (78fh)
1050
2.0µs (33fh) 4.5µs (73fh)
0.5µs (8fh)
3.0µs (50fh)
EVEN LINE
ODD FIELDEVEN FIELD
4.7µs (78fh)
971 981 991 1001 1011 1021 1031 1041 1 11 21 31 41 51 61 71 81 91 101 111
CLK
SYNC
(BLK)
HD
HST
HCK1
HCK2
LCX009 Horizontal Direction Timing Chart (NTSC, PAL)
– 40 –
FRP
VCK1
(Internal pulse)
VCK2
CLR
EN
(PAL)
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
Page 41
20fh
RGT: L (Reverse scan) Composite In
CXA1854AR
12fh
43.0fh
0.5µs (7fh)
1050
4.7µs (78fh)
3.0µs (51fh)
ODD LINE
EVEN FIELDODD FIELD
2.0µs (33fh) 4.5µs (73fh)
4.7µs (78fh)
971 981 991 1001 1011 1021 1031 1041 1 11 21 31 41 51 61 71 81 91 101 111
CLK
SYNC
(BLK)
HD
HST
HCK1
HCK2
LCX009 Horizontal Direction Timing Chart (NTSC, PAL)
– 41 –
FRP
VCK1
(Internal pulse)
VCK2
CLR
EN
(PAL)
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
Page 42
21.5fh
RGT: L (Reverse scan) Composite In
CXA1854AR
12fh
43.0fh
0.5µs (7fh)
1050
4.7µs (78fh)
3.0µs (51fh)
EVEN LINE
EVEN FIELDODD FIELD
2.0µs (33fh) 4.5µs (73fh)
4.7µs (78fh)
971 981 991 1001 1011 1021 1031 1041 1 11 21 31 41 51 61 71 81 91 101 111
CLK
SYNC
(BLK)
HD
HST
HCK1
HCK2
LCX009 Horizontal Direction Timing Chart (NTSC, PAL)
– 42 –
FRP
VCK1
(Internal pulse)
VCK2
CLR
EN
(PAL)
The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified.
Note) During Y/C input, the HST timing is delayed 6fh from the above timing.
Page 43
272
65432187
Display start
4
321
CXA1854AR
3.0H
3.0H3.0H
2632010
20H
243
8.5H
65432187
Display start
4321
EVEN FIELDODD FIELD
9H
1
3.0H3.0H
20H
3.0H
505
HD
(VD)
SYNC
(BLK)
VST
VCK1
VCK2
FRP
(Internal pulse)
LCX009 Vertical Direction Timing Chart (NTSC)
HST
– 43 –
EN
CLR
FRP
(1F inversion)
FLD
(Internal pulse)
(Internal pulse)
VD
VRST
Note) The second and fourth rows of the timing chart "VD" and "BLK" are pulses indicated as a reference and are not pulses output from pins.
(Internal pulse)
Page 44
32165432187
CXA1854AR
6, 8 decimation
2.5H
2.5H2.5H
314 324
25H
288
65432187654321
Display start
4321
6.0H
10.0H
EVEN FIELDODD FIELD
HD
2.5H
(VD)
2.5H2.5H
SYNC
26600
Display start
112
5.5H
10.5H
25H
VST
(BLK)
4321
6543218765432187654321654321871
VCK1
VCK2
FRP
HST
EN
CLR
(1F inversion)
FLD
FRP
VD
VRST
Note) The second and fourth rows of the timing chart "VD" and "BLK" are pulses indicated as a reference and are not pulses output from pins.
LCX009 Vertical Direction Timing Chart (PAL)
(Internal pulse)
– 44 –
(Internal pulse)
(Internal pulse)
(Internal pulse)
Page 45
Package Outline Unit: mm
CXA1854AR
64PIN LQFP (PLASTIC)
12.0 ± 0.2
10.0 ± 0.2
48 33
49
64
116
1.25
0.5
+ 0.08
0.18 – 0.03
0.1 ± 0.1
(0.5)
32
17
0.1
0.15 ± 0.05
0.1
A
1.7 MAX
M
SONY CODE
EIAJ CODE
JEDEC CODE
0° to 10°
DETAIL A
LQFP-64P-L061
LQFP064-P-1010-AY
0.5 ± 0.2
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER PLATING
42 ALLOY
0.3g
– 45 –
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