Datasheet CT2565-FP, CT2565-201-2, CT2565-201-1, CT2565-001-2, CT2565-001-1 Datasheet (ACT)

CT2565

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www.aeroflex.com

Bus Controller, Remote Terminal and BUS Monitor

FOR MIL-STD-1553B

Features

■ Second Source Compatible to the BUS-65600

■ RTU implements all dual redundant mode codes

■ Selective mode code illegalization available

■ 16 bit microprocessor compatibility

■ BC checks status word for correct address and set flags

■ RTU illegal mode codes externally selectable

■ 16 bit µProcessor compatibility

■ DMA handshaking for subsystem message transfers

■ MIL-PRF-38534 compliant circuits available

■ DESC SMD #5962–88585 Pending

■ Packaging – Hermetic Metal

• 78 Pin, 2.1" x 1.87" x .25" Plug-In type package

• 82 Lead, 2.2" x 1.61" x .18" Flat package

CIRCUIT TECHNOLOGY

ISO

9001

I

General Description

The CT2565 is a dual redundant MIL-STD-1553 Bus Controller (BC), Remote Terminal (RT), and
Bus Monitor, (BM) Bus packaged in a 1.9" x 2.1" hermetic hybrid. It provides all the functions
required to interface a MIL-STD-1553 dual redundant serial data bus transceiver, (Aeroflex's
ACT4487 for example) and a subsystem parallel three-state data bus. Utilizing a custom monolithic
IC, the CT2565 provides selectable operation as a Bus Controller, Remote Terminal or a Bus
Monitor (BM).

The CT2565 is compatible with most µprocessors. It provides a 16 bit three-state parallel data bus
and uses direct memory access (DMA type) handshaking for subsystem transfers. All message
transfer timing as well as DMA and control lines are provided internally. Subsystem overhead
associated with message transfers is therefore minimized. Interface control lines are common for
both BC and RT operation.

The CT2565 features the capability for implementing all dual redundant MIL-STD-1553 mode
codes. In addition, any mode code may (optional) be illegalized through the use of an external
(200ns access time) PROM. Complete error detection capability is provided, for both BC and RTU
operation. Error detection includes: response time-out, inter message gaps, sync, parity,
Manchester, word count and bit count. The CT2565 complies with all the requirements of
MIL-STD-1553.

The hybrid is screened in accordance with the requirements of MIL-STD-883 and operates over the
full military temperature range of -55°C to +125°C.

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BUSGRNT

BUSREQ

SOM

BUSACK

INCMD

EOMOECS

WR

CHA/CHB

BCSTART

MSGERR

LOOPERR

LWORD

STATERR

STATEN

HSFAIL

NBGRNT

BITEN

NODT

ADRINC

BSCTRCV

TIMEOUT

I/O LOGIC

BUFFERS

BUFENA

I/O0 - I/O16

LMC

WC0-WC4

ILLCMD

T/R

SERREQ

DBACCEPT

SSBUSY

SSERR

SSFLAG

DATA

BUFFERS

REMOTE

TERMINAL

LOGIC

BUS

CONTROLLER

LOGIC

DATA BUS

STATUS INPUTS

MODE CODE CONTROL

CH B

CONTROL

CH A

ENCODE/

DECODE

CH B

ENCODE/

DECODE

TXDATA A

TXINH A

RXDATA A

RXDATA A

TXDATA A

RTADDR

PARITY

CHECKER

TXDATA B

TXINH B

RXDATA B

RXDATA B

TXDATA B

RTADDR

RTADDR

RTADR2

RTADR0

RTADR4

RTADR3

RTADR1

RTADRP

CONTROL BUS

Figure 1 – CT2565 Block Diagram

12MHz

MT

RT/BC

TESTOUT

TESTIN

CH A

CONTROL

I/O BUS

ENR/W

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Values at nominal Power Supply Voltages unless otherwise specified

PARAMETER VALUE UNITS

Logic

V

IH

V

IL

V

OH

V

OL

I

IH

I

IL

* ±1.2 max mA

I

OL

* ±0.4 max mA

I

OH

C

(f = 1MHz) 20 max pF

IN

(f = 1MHz) 20 max pF

C

OUT

2.0 min V

0.8 max V

3.7 min V

0.4 max V

±100 max µA

-0.4 max mA

Power Supply

+5VDC

Tolerances ±10 max %
Supply Current 50 typ (70 max) mA
Internal Decoupling 1.5 typ µF

Temperature Range

Operating (Case)
Storage

−55 to +125 °C

−65 to +150 °C

Physical Characteristics

Size

78 pin DDIP 1.9 x 2.10 x 0.25

82 pin flatpack 1.6 x 2.19 x 0.15

Weight 1.7 (48) oz (g)

* I

and I

OL

both parameters.

parameters are indicated for all logic outputs except Data Bus (DB0 – DB15) which are ±5mA for

OH

Table 1 – CT2565 Specifications

GENERAL

The CT2565 uses a custom CMOS ASIC for
protocol logic and I/O buffering to provide low
power dissipation in its small package.

The CT2565 performs a continuous on-line
Built-In-Test (BIT); in this test the last transmitted
word of each message transfer is wrapped
around through the active receiver channel and
verified against the captured encoded word. A
user-defined loop test under subsystem control
can also be implemented. Numerous error flags
are provided to the subsystem including
message error, status error, response time out
and loop test error.

in

(48.30 x 53.34 x 6.35)

(mm)

in

(40.64 x 55.63 x 3.81)

(mm)

DDIP package are made throughout this
document. For flatpack model pin numbers, refer
to Table 10.

BC/RTU/MT Initialization

The CT2565 provides BC, RTU, and MT
operating modes. The operating mode if
dynamically selectable through two static control
inputs as listed in Table 2. It is recommended
that a master RESET signal be issued (80ns min)
prior to mode selection to clear the internal
registers.

An external 12 MHz, TTL clock connected to Pin
39 is required.

Where appropriate, references to signal names
and their associated pin numbers for the 78 pin

MIL-STD-1553 Word Types

Figure 2 illustrates the three MIL-STD-1553 word
types: Command, Data, and Status.

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BIT TIMES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

COMMAND WD 5 5 5 1

SYNC REMOTE TERMINAL T/R SUBADDRESS DATA WORD P

DATA WORD 16 1

SYNC DATA P

STATUS WORD 5 1 1 1 3 1 1 1 1 1 1

SYNC REMOTE TERMINAL RESERVED

Note: T/R – Transmit/Receive, P – Parity

ADDRESS MODE COUNT/MODE CODE

ADDRESS

INSTRUMENTATION

SERVICE REQUEST

Figure 2 – MIL-STD-1553 Word Types

triggers an address increment (ADRINC pin) low

MODE

RT/BC

(PIN 1)

BC 0 1

RT

MT

1 1

0 0

Table 2 – Operating Modes

DMA-Type Handshake

All BC and RT word transfers are preceded by a
request-grant-acknowledge format DMA
handshake procedure. Timing information is
provided in BC, RTU and MT sections.
In MT mode, the 1553 transmission is transferred
along with an identification Word using a single
DMA handshake containing two memory-write
operations. The DMA format requires that the
subsystem provide a bus grant (BUSGRNT

45) low within a timeout period. Note that
BUSGRNT
another bus request (BUSREQ

Memory Read/Write

With the single exception of an RT command
word transfer, all subsystem transfers take the
form of a static memory read or write. A low
pulse on both the chip select (CS
enable (OE
enable (WE
indicates data is valid on the parallel data bus for
the duration of the pulse. The rising edge of CS

should be set to logic "1" before

) is issued.

) or a low pulse on CS and write

) (pins 17, 18 and 44 respectively)

MT

(PIN 2)

pin

) and output

output pulse used to increment the subsystem
memory address for successive transfers.

BC OPERATION

In the BC mode, the CT2565 initiates all
MIL-STD-1553 data and control message
transfers. Figure 3 details specific message
transfer flow and Table 3 lists subsystem memory
allocation. The subsystem, or host processor,
must provide a CT2565 protocol Control Word
(See Figure 4) and MIL-STD-1553 command and
data words. The CT2565 will transfer the RTU
status response and provide message transfer
validation during an active transfer. All parallel
word transfers occur in the form of a DMA
(request-grant-acknowledge) handshake with
memory read or operation as shown in Figures 5
and 6.

Command Transfer

In the BC mode pulse BCSTART
Following the pulse, the CT2565 will initiate a
DMA handshake and memory read for; the
control, word, command word(s) and up to 32
data words. No handshake timeout is enforced in
the BC mode (CT2565) remains idle during
BUSREQ

to BUSGRNT), however 1553 protocol

must be maintained.

Note that commands are named from the BC's
point-of-view (for example, a TRANSMIT CMD
indicates the addressed RTU must transmit data).

PARITY
TERMINAL FLAG

DYNAMIC BUS
CONTROL
ACCEPTANCEMESSAGE ERROR

SUBSYSTEMFLAG

BUSY

BROADCAST
COMMAND RCVD

(pin 41) low.

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RECEIVE TRANSMIT

Control Word Control Word

Receive Command

Data 1

Transmit Command

Looped Command Word

• RTU Status

• Data 1

Last Data

Looped Data Word

RTU Status

•

•

Last Data

Table 3 – BC Memory Allocation

15 8 0

NOT USED

Loop Test

Upon receipt from the subsystem, the last word
to be transmitted within a given message
transfer (command or Data word) is stored in a
CT2565 internal register. As this word is
transmitted to the 1553 bus, it is looped back
through the active receiver channel for auto-BC,
Short Loop verification. A LOOPERR

(.5us typ)
low pulse indicates a mismatch between the
stored and looped word. The CT2565 also
initiates a handshake with a memory write to the
subsystem for user-defined, "long loop"
(subsystem, CT2565, subsystem) verification.
Note that both short and long loop testing are
initiated for all transfers (on the last word
transmitted to 1553). Subsystems response to
use Long Loop Test is to compare the loaded
word to what was looped back into memory.

BUS CHANNEL A/B

NOT USED

MASK BROADCAST BIT

NOT USED

MODE CODE

BROADCAST

RT-RT

BIT DEFINITION

BUS CHANNEL A/B When logic "1" transmits over 1553 Bus A.

When logic "0" transmits over 1553 Bus B
(See note)

MASK BROADCAST BIT

MODE CODE

BROADCAST

RT-RT

Always set to "0"

Command Word count field signifies mode code type

Multiple RTU’s addressed, no status word expected

When set, RTU(b) transmits, RTU(a) receives. Both RTU Status Words
are validated and sent to subsystem.

Note: Messages-transmission (routing) status pin (pin 16, Chan A/B) becomes active after loading the control word and command word

respectively. The signal is cleared by RESET

or EOM low.

Figure 4 – BC Control Word

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CONTROL & COMMAND WORDS

DATA WORDS

START BC OPERATION

HANDSHAKE

(DMA)

MEMORY READ

CONTROL WORD

FROM SSIU

INCREMENT MEM ADDR

OUTPUT

HANDSHAKE

(DMA)

MEMORY READ

COMMAND WORD

FROM SSIU

SHORT LOOP

LONG LOOP

NO

STATUS

FROM

RT

YES

HANDSHAKE

(DMA)

MEMORY WRITE

STATUS WORD

TO SSIU

STATERR

INCREMENT MEM ADDR

A

RX

CMD

HANDSHAKE

MEMORY READ

DATA WORD

FROM SSIU

INCREMENT MEM ADDR

DATA TO 1553

SHORT LOOP

LONG LOOP

YESNO

(DMA)

MORE

DATA

YES

NO

CMD WORD TO 1553

CMD WORD TO 1553

TIMEOUT

A

Notes:
(1) Steps marked with " ___" indicates operation is transparent to user.

MSGERR

NO

STATUS

FROM

HANDSHAKE

(DMA)

MEMORY WRITE

DATA WORD

TO SSIU

MORE

(2) Steps marked with " ___" indicates user interaction required.

Figure 3 – BC Message Transfer Flow

RT

YES

DATA

NO

END OF MESSAGE PULSE

YES

STOP

STATUS

FROM

RT

YES

STATERR

MEMORY WRITE

STATUS WORD

TO SSIU

NO

TIMEOUT

MSGERR

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TRANSFER/CONDITION DESCRIPTION ERROR SIGNAL PIN

CONTROL/COMMAND WORD 1

Handshake Failure

LOOPED WORD

Short Loop Failure
Long Loop Failure

RT-RT Status-RT1, data, status-RT2 response

STATUS WORD

No Status Received within 15.5µS

RT Address Mismatch

Error Flag(s) Set Status Word Response from RT:

Broadcast Received bit Set Response to Transmit Status Word mode

DATA WORD

Handshake Failure

Transmit Command
Receive Command

Data Received from RTU

Less than word count
Greater than word count

Data after Status Set

(all extra words)

FORMAT ERROR

Memory read by BC subsystem.

No response to Bus Request within timeout
period.

Looped back through receiver.

Received Word
DMA/Write looped word to subsystem.

to follow receive, transmit, commands.

timeout TIMEOUT

NODT

Command RTU Address

RTU Address

Error Condition

command may allow this, all others ERROR.

No subsystem response to Bus Request.

Data lost: Word Count fails.
1553 transmission gap.

Transmit Command (RTU response)
More data received than requested.

Transmit Command: data words received

after status to subsystem.

≠ last xmitted word.

≠ Status Word

-

BC waits for Grant
(no 1553 timing error)

LOOPERR
User Defined

(See definitions in

STATUS/DATA WORD
below)

EOM
STATERR

STATERR

Broadcast Mask not set
(See BC Control Word)
STATERR

BC waits for Grant.
MSGERR
Status Word response:
STATERR

MSGERR
MSGERR and EOM

DMA/memory write
(for each)

MSGERR

and EOM

-

46

-

-

4
57

68

68

68

30

68

4
30

-

30

Notes:
(1) LOOPERR

(2) TIMEOUT
(3) STATERR is a 120/166nS pulse which occurs during the status word DMA handshake.
(4) MSGRR is a 40/160nS pulse which occurs approximately 100nS before INCMD goes high. It is triggered by NODT going inactive (i.e.,

low word count).

is a .5µS pulse which occurs near DMA handshake for loop back word.

is a 40/160nS pulse which occurs 19.5µS ±0.5µS after the mid-bit parity of the last word onto the bus.

Table 4 – BC Error Handling

RTU Response

The addressed RTU(s) must respond (to
non-broadcast commands) within a timeout
period as shown in Figures 7, 8, and 9. Figures
10 and 11 illustrate the BC Mode Code Timing.
Status and data words received from the 1553
port are transferred to the subsystem via a
handshake and memory write operation for each
(See Message Length Checking).

BC Status/Error Handling

Message transfer errors are indicated using the
TIMEOUT

, MSGERR, LOOPERR and STATERR
BC status outputs (pins 4, 30, 46 and 68
respectively). Additional error detection
methods include user evaluation of status, data
and (long) loop words and/or use of the 1553B
dual redundant mode codes. Note that certain
error conditions not reflected in the current
Status Word (SW) can occur; Broadcast CMD
RT-status and post RT status response may be

accessed via the Transmit Status Word mode
command.

Transmit Bit Word. Additional status informa
tion is generated by an RTU (CT2565 for each
transfer in the form of a BIT word). This word
may be accessed by the BC using the
TRANSMIT B-I-T WORD mode command. See
RTU Error Handling and Mode Code sections).

Message Length Checking. The BC stores the
command word, word-count field in an internal
register. By decrementing this register following
each data word transfer (See BC Memory
Read/Write Timing), the BC can detect an
incorrect message length.
For a description of the possible BC error,
indicators occurring during each stage of
message transfer read from left to right in
Table4. For a description of the possible causes
of errors within a transfer, read from right to left.

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BUSREQ

BUSGRNT

(19)

(45)

t1

t2

t3

4

t

BUSACK

OE

WR

CS (17)

BUSACK

(59)

HSFAIL (5)

TRI-STATE

SYMBOL DESCRIPTION MIN MAX UNITS

t1

t2

t3

t4

BUSREQ pulse width

BUSREQ to BUSGRNT delay

BUSGRNT pulse width

BUSGRNT to BUSACK delay

867 1667 ns

0 800 ns

166 - ns

50 200 ns

Figure 5 – BC Handshake Timing

(59)

t1

(18)

t9

t8

(44)

t7

t2

t

4

t9

ADRINC (49)

D0 - D15

t3

MEMORY READ

t5

t6

MEMORY WRITE

t10

DATA VALIDDATA VALID

t5

t6

CYCLE SYMBOL DESCRIPTION MIN MAX UNITS

Read t1

t2

t3

t4

t5

t6

Write t7

t8

t9

t10

BUSACK to OE delay

OE to CS delay
Data setup time

CS (OE) pulse width

CS to ADRINC delay
ADRINC pulse width

BUSACK to WR delay
WR to CS delay

CS and WR pulse width

Data valid setup

- 25 ns

- 25 ns

- 250 ns

650 680 ns

- 25 ns

80 166 ns

- 378 ns

- 25 ns

150 175 ns

100 - ns

Figure 6 – BC Read/Write Timing

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1553 BUS

BC START

INCMD

(41)

(9)

HANDSHAKE

(REQ, GRNT, ACK)

MEM-READ

, OE, ADRINC)

(CS

MEM-WRITE

(CS

, WR, ADRINC)

50

200

330
700

ns

ns

166µs

4µs

2µs

P

A

DATA

P

10.75±0.75µs

STAT RT

24±0.5µs43.5±0.5µs

PCMD RT

A

D0 - D15

7.5±0.5µs

(71)

NODT

LWORD

STATERR

Notes for Figures 7-9
T/R and HSFAIL are static at logic "1" in BC mode. All timing is typical unless otherwise noted.

(29)

(68)

EOM (57)

OUTPUTS

200ns

CHA

/CHB LATCHED

5.5±0.5µs

44±0.5µs

LOOP STATCMDCLT STATDATA

7.5±0.5µs

5.5±0.5µs

5.5µs TYP

120
166

ns

166
332

200
500

ns

ns

Figure 7 – BC Receive One Word Command Timing

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1553 BUS

CMD RT

P STAT RTAP

A

DATA

P

BC START

INCMD

(41)

(9)

HANDSHAKE

(REQ, GRNT, ACK)

MEM-READ

, OE, ADRINC)

(CS

MEM-WRITE

(CS

, WR, ADRINC)

D0 - D15

(71)

NODT

LWORD

STATERR

(29)

(68)

EOM (57)

OUTPUTS

10.75±0.75µs

LOOP

7.5±0.5µs (B)

20±0.5µs

(a)

EX: LOW WD COUNT

20±0.5µs30±0.5µs

STATCMDCLT DATA

150ns (NOM)

120

ns

166

MESS ERR.

(a) 5.5±0.5µs

200ns

50

200

ns

330
700

ns

166µs

CHA

/CHB LATCHED

Figure 8 – BC Transmit One Word Command Timing

(B)

5±0.5µs

200
500

100ns

40

ns

160

ns

1553 BUS

BC START

INCMD

(41)

(9)

HANDSHAKE

(REQ, GRNT, ACK)

MEM-READ

, OE, ADRINC)

(CS

MEM-WRITE

(CS

, WR, ADRINC)

D0 - D15

(71)

NODT

LWORD

STATERR

(29)

(68)

CMD

RTARXP RTBTXP

330

ns

700

2µs

CTL STAT

CMD

5.5±0.5µs

STAT

LOOP

7.5±0.5µs

RTBP DATA P

STATCMD

5±0.5µs

DATA

STAT

RTAP

5.5±0.5µs

7.5±0.5µs7.5±0.5µs

150ns (NOM)

5.5±0.5µs

120

ns

166

EOM (57)

Figure 9 – BC RT-RT Transfer Timing

10

200
500

ns

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1553 BUS

CMD

RTAP

STAT

RTAP DATA LCMD P

INCMD (9)

BUSREQ

ADRINC

D0 - D15

LWORD

EOM (57)

1553 BUS

INCMD (9)

BUSREQ

70/80µs

(19)

(49)

CTL CMD LOOP STAT LCMD

(29)

900ns

80/166ns

5.0±0.5µs

400/500ns

Figure 10 – BC Mode Code Transmit Last Command (10010) Timing

CMD

(19)

RTAP

50/80µsec

STAT

900ns

RTAP

ADRINC

LWORD

(49)

D0 - D15

(29)

EOM (57)

CTL CMD LOOP STAT

Notes:
All timing is typical unless otherwise noted.

Figure 11 – BC Mode Code Transmit Status Word (00010) Timing

RTU Operation

Each RTU is assigned a unique address on the
1553 bus. It processes commands issued by the
BC to its address or through Broadcast
commands.
Upon receipt of a valid command in the RTU
mode, the CT2565 will attempt to (1) transfer
1553 data received to the subsystem, (2) read
data from the subsystem for transmission on the
1553 bus, (3) transmit status information to 1553,
or (4) set status conditions. All data block
transfers are accompanied by a 1553 Status
Word. Figure 12 details a RTU single message
transfer.

80/166ns

40/60µsec

400/500ns

RTU Address

RTU Address pins 33-34 and 72-74 and Address
Parity pin (odd parity) should be programmed to
a unique RTU (1553) address. These inputs
have internal pull-ups and will default a high state
if left unconnected. The CT2565 will not respond
if odd parity is compromised (See Error
Handling).

RTU Initialization

Initialize the CT2565 as an RTU per Table 2.
Upon receipt of valid command word from the
serial bus (RTU addressed or broadcast CMD),
the CT2565 will pulse NBGRNT

(New Bus Grant)

pin 42 low.

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COMMAND WORD

DATA WORD(S)

STOP

NO

RT-RT

TXFER

YES

RT-RT

YES

STATUS TO 1553

STATEN

PULSED

STOP

CMD WORD RECEIVED

FROM 1553

WORD VALIDATION

RT

ADDR

YES

WORD COUNT LATCHED

BIT LATCHED

T/R

MODE CODE PULSE
(MODE CODE ONLY)

CMD

ILLEGALIZED

?

NO

HANDSHAKE

(DMA)

HS FAIL

STOP

YES

STATUS TO 1553

STOP

INCREMENT MEM ADDR

NO

SSU

BUSY

NO

STATUS TO 1553

STATEN PULSED

MORE

DATA?

YES

HANDSHAKE

(DMA)

MEMORY READ

DATA WORD

FROM SSIU

OUTPUT

A

RX

CMD

DATA FROM 1553

WORD VALIDATION

NO

INCREMENT MEM ADDR

YES

HANDSHAKE

(DMA)

MEMORY WRITE

DATA WORD

TO SSIU

OUTPUT

MORE
DATA?

NO

STATUS TO 1553

HS FAIL

YES

DATA TO 1553

HS FAIL

SOM PULSED

NO

STOP

Notes:
(1) Steps marked with " ___" indicates operation is transparent to user.
(2) Steps marked with " ___" indicates user interaction required.

DATA

EXPECTED

?

YES

A

SHORT LOOP

END OF MESSAGE

PULSED

STOP

Figure 12 – RTU Single Message Transfer Flow Diagram

12

STATEN PULSED

SHORT LOOP

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Mode Code Illegalization (Optional)

The word count and TX/RX

pins will be latched
800ns (typ) after the falling edge of NBGRNT
(See Figure 13, RTU Command Word Handling).
Table 5 lists the CT2565 pins associated with
mode code illegalization. If the current command
is a mode code, LMC (pin 55) will go high. Mode
codes can be illegalized, using an external PROM
(<200ns access time recommended), by setting
ILLCMD

low after the NBGRNT flag. This will set
the message error (status word) and illegal Mode
Code (BIT word) bits followed by transmission of
the status word. Using the method, mode
commands can be "auto-screened" without
interrupting subsystem operation. For a complete
list of mode codes, refer to Table 8.

NBGRNT (42)

t

1

LMC (55)

t

WC

T/R (15)

0-4

ILLCMD

INCMD

BUSREQ

2

(48)

(9)

(19)

t

3

VALID UNTIL NEXT VALID COMMAND WORD RECEIVED

t

4

LATCHED UNTIL NEXT VALID COMMAND WORD RECEIVED

t

5

Table 5 – Mode Code Illegalization

PIN # SYMBOL DESCRIPTION

51 WC0 Word Count LSB

12 WC1 Word Count 1

52 WC2 Word Count 2

13 WC3 Word Count 3

53 WC4 Word Count MSB

15 T/R

Note: A word count field of all 0’s indicates 32 data words; all 1’s

= 31 words.

TX/RX

BUSACK

STATUS INPUTS

(59)

(78)

SOM

D0 - D15

SYM DESCRIPTION MIN TYP MAX UNITS

Illegalize t1

Legal t5

Status Inputs t9

DBACCEPT, SSFLAG, SVCREQ, SSER

NBGRNT pulse width

t2

t3

t4

NBGRNT to LMC delay

LMC to WC-T/R latch

LMC to ILLCMD latch

NBGRNT to INCMD delay

t6

t7

t8

BUSACK to SOM delay

SOM pulse width

CMD VALID setup

NBGRNT low to status latch

and

t

SSBUSY

t

6t7

t

8

CMD VALID

9

INPUTS

151 - 181 ns

500 - 667 ns

- 200 - ns

- - 333 ns

- 1.0 1.5 µs

- 166 - ns

- 166 - ns

60 - 100 ns

- - 3 µs

LATCHED

Note: Memory read/write signals CS, OE, and ADRINC remain static at logic "1".

Figure 13 – RTU Command Word Handling/Status Inputs

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RTU Commands

A command word transfer will be initiated by the
CT2565 after the rising edge of NBGRNT

(See
Figure14). In order to allow the command word to be
stored in user-defined memory space (separate from
data), no memory write operation (CS

, WR, ADRINC
outputs) will be initiated following the usual DMA-type
handshake; a Start Of Message (pin 78: SOM low)
pulse indicates that the CMD word is currently valid on
the data bus. Note that commands are named from
the BC point-of-view (i.e., a TRANSMIT CMD dictates
that the addressed RTU must transmit data).

Transmit CMD (RT-BC)

If the subsystem is available (pin 47: SSBUSY high):
following transmission of the status word, the CT2565
will initiate a handshake/memory-read respectively for
the total number of (data) words defined by the
Command Word-word count field. Figure 15 shows
the RTU Read/Write Timing. Note that possible data
word transfer and short-loop test errors will be
reflected in the following status word/bit word. A low
on the SSBUSY

input will set the corresponding status
word flag, and no data transfer will be requested
(BUSREQ

low) following transmission of the status

word.
Receive CMD (BC-RT). A DMA handshake will be

initiated for each word received over the 1553 data bus
(See Figure 16). If successful, the respective
handshake will be followed by a corresponding
memory write. Transfer errors such as handshake
timeout or SS BUSY will not terminate transfer
attempts for the remaining data words, error flagging
or status word transmission.

RTU(b)-RTU(a) (Transmit/Receive). An RT-RT

transfer will appear to both RTU subsystems as a
standard transmit or receive command except: (1)
transmission of the data block will not be continuous
with that of the receive CMD, and, (2) upon detection
of a command-sync field following the receive CMD,
RTU(a) will recognize an RT-RT transfer and store the
transmit CMD-address field for comparison with the
address field of the following (RTU(b) status) word
(See Figures 17 and 18). If a mismatch is detected,
RTU(a) will issue a message error. The transmitting
RTU will respond as in an RT-BC Transmit CMD.

RTU Status/Error Handling

Message transfer errors are indicated using the
TIMEOUT

, HSFAIL, MSGERR and LOOPERR
RTU-status outputs (pins 4, 5, 30 and 46 respectively).
Additional error detection mechanisms available
include status input manipulation (below) and
evaluation of the status and BIT words (See BIT
Word).

Table 6 describes error handling mechanisms related
to each stage in a message transfer (reading left to
right) as well as noting errors associated with a
specific CT2565 status output (reading right to left).

Short Loop Test. The last word to be transmitted in a
given message transfer (Status word, BIT word or
Data word) is stored in a CT2565 internal register. As
this word is transmitted to the 1553 bus, it is "looped
back" through the active receiver channel for
auto-RTU, "SHORTLOOP" verification. A LOOPERR
low pulse indicates a mismatch between the stored
and looped words. Note that short loop testing is
initiated for all RTU transfers except a Broadcast
transfer.

TRANSFER/CONDITION DESCRIPTION ERROR SIGNAL PIN

COMMAND WORD

Invalid Word Format
Invalid Command (format error)

Handshake Failure BUSREQ

Illegal Mode Command Subsystem set ILLCMD
RT-RT Transfer

Response Timeout

Address mismatch

DATA WORD

Handshake Failure

Transmit Command
Receive Command

Number Transmitted

LOOP WORD

Short Loop

Long Loop

Notes:
(1) The HSFAIL low output is reset (high) at the start of the next message transfer (NBGRNT low).
(2) The subsystem can use the status input pins (SW) to report incorrect word count type errors.
(3) MSGERR

set 7.5µS after last mid parity bit of last data word.

(2)

Sync, bit count invalid.
Operation disagreement (e.g. Broadcast and

Transmit bits set)

to BUSGRNT timeout HSFAIL, suppress

(pin 48). SW message error bit set

(Transmit) Command to Status Word time.

Transmit Command Address

address.

BUSREQ to BUSGRNT timeout
(Continue)
(Message terminated)
Low data word-count received.
High data word count

Looped back through receiver.
Received word

(BC only)

≠ to last xmitted 1553 word.

≠ Status Word

None; input ignored
MSGERR

SOM, continue

TIMEOUT
(also; MSGERR bit)
MSGERR
(also; MSGERR bit)

HSFAIL
Continue message transfer
INCMD

MSGERR
MSGERR
(no transfer) SW and BIT­Word also set.

LOOPER
Flag bit).

(also; SW bit)

(transmitting RT)

(Receiving RT)

(1)

high, EOM

(3)

(SW bit)

after validation

(also sets Ter-

­30

5
78

4

30

5

9,57
30
30

46

Table 6 – RTU Error Handling

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BUSREQ

(19)

t1

t2

BUSGRNT

BUSACK

(45)

(59)

HSFAIL (5)

3

t

SYMBOL DESCRIPTION MIN MAX UNITS

t1

t2

BUSREQ pulse width

BUSGRNT delay

CMD WORD
TX DATA WORD
RX DATA

t3

Note: HSFAIL will go low following a BUSREQ to BUSGRNT timeout.

BUSGRNT to BUSACK delay

667 - ns

0
0
0

1.5

15.5

2.33

40 166 ns

Figure 14 – RTU Handshake Timing

t

BUSACK

OE

(59)

(18)

t

1

4

t

7

µs
µs
µs

(44)

WR

t

8

t

9

t

5

t

10

(17)

CS

ADRINC (49)

D0 - D15

t

2

t

4

t

5

t

t

3

VALID VALID

MEMORY WRITE MEMORY READ

6

CYCLE SYMBOL DESCRIPTION MIN TYP MAX UNITS

Read t1

t2

t3

t4

t5

t6

Write t7

t8

t9

t10

BUSACK to OE delay

OE to CS delay
Data setup time

CS, OE and BUSACK pulse width

CS to ADRINC delay
ADRINC pulse width

BUSACK to CS delay
WR to CS delay

CS and WR pulse width

Data valid setup prior to leading edge of WR

- - 25 ns

- - 25 ns

- - 250 ns

- 500 - ns

- - 25 ns

80 - 166 ns

- - 225 ns

- - 25 ns

150 166 180 ns

60 - 100 ns

Figure 15 – RTU Read/Write Timing

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Use of Status Word

The status word may be captured by the
subsystem as it is transmitted to the 1553 port by
pulsing BUFENA (pin 58) low during STATEN

(pin
3: 520ns low pulse). Data becomes valid
approximately 50ns after the falling edge of
BUFENA

. This corresponds with all
non-broadcast message transfers and the
TRANSMIT STATUS WORD mode command.
Note that the status word may be transmitted prior
to an error condition (See Transmit CMD). These
conditions will be indicated in the "next" status
word and may be monitored if the BC requests the
SW before it is altered (See Mode Commands).

Subsystem Control

The CT2565 allows the subsystem total control
over the status word flags using the inputs
indicated in Table 7.

BIT Word

The BIT Word (Built-In-Test) becomes available in
response to a TRANSMIT BIT WORD mode
command and provides additional status
information (See Figure 19) to that provided by the
status word. The subsystem may capture the BIT
word on the parallel data bus by pulsing BUFENA

(pin 58) low during BITEN (pin 43: approximately
520ns low pulse). Data Becomes valid
approximately 50ns after the falling edge of
BUFENA

. Like the status word, the BIT word

cannot be altered by the subsystem.

PIN

SYMBOL DESCRIPTION

#

6 DBACCEPT RT accepts BC operation

responsibility (See Table 2).

7 SSFLAG Transmitted data may be

invalid sets SSFLAG bit.

8 SVCREQ Service Request; see

Transmit Vector mode
command.

10 SSER RTU fault exists: sets

TERMINAL FLAG bit.

47 SSBUSY Subsystem cannot service

1553 request at this time.

48 ILLCMD Mode command subsystem

illegalization: Sets MSGERR
bit, doesn’t suppress status
word.

Table 7 – Subsystem Control of RT-Status

1553 BUS

NRGRNT

BCSTRCV

HANDSHAKE
(REQ, GRNT, ACK)

MEM-WRITE
(CS

, WR, ADRINC)

STATEN
BUFFENA

INCMD

SOM (78)

D0 - D15

NODT

(3)/

EOM (57)

(42)

(75)

(9)

(71)

(58)

CMD

RTARCV P

1.5µs

5.5±0.5µs

DATA (16 BITS)

3.4±0.5µs

0.5µs

3.2±0.5µs

CMD DATA STAT

667ns

P

10.75±0.75µs

7.5±0.5µs

3.9µs

REF

STAT RTAP

5.5±0.5µs

4µs

7.5±0.5µs

4.5±0.5µs

400ns

WC

0-4

/CHB (16)

CHA

T/R (15)

166ns

Note: All timing is typical unless otherwise noted.

Figure 16 – RT Receive Command Timing

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1553 BUS

NRGRNT

(42)

ILLEGALIZE

(9)

INCMD

HANDSHAKE
(REQ, GRNT, ACK)

SOM (78)

MEM-READ
(CS

, OE, ADRINC)

CMD

RTATXP

3.4±0.5µs

1.5µs

LMC

ILLCMD

10.75±0.75µs

7.5±0.5µs

STAT

5.5±0.5µs

RTAP

1.0±0.2µs

DATA (16 BITS)

P

7.5±0.5µs

4.5±0.5µs

STATEN
BITEN

WC

CHA

D0 - D15

NODT

(43)

EOM (57)

T/R (15)

0-4

/CHB (16)

CMD STAT DATA

5.5±0.5µs

(71)

(3)/

4µs

500±20ns 500±20ns

667ns

166ns

Notes:
(1) All timing is typical unless otherwise noted.
(2) BITEN only occurs when XMIT BIT WD mode code command is received
(Handshake and read/write signals are not generated in this case).

Figure 17 – RT Transmit Command Timing

165ns

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1553 BUS

NRGRNT

(42)

ILLEGALIZE

(9)

INCMD

HANDSHAKE
(REQ, GRNT, ACK)

SOM (78)

MEM-READ
(CS

, WE, ADRINC)

D0 - D15

NODT (71)

STATEN
BITEN

(3)/

(43)

EOM (57)

TIMEOUT (4)

RTARCV P RTBTXP

CMD CMD

3.4±0.5µs

LMC

ILLCMD

1.5µs

RCV

CMD STATDATA

5.5±0.5µs

10.75±0.75µs

7.5±0.5µs

(TIMEOUT ERROR)

19.5µs

STAT

RTBP

DATA

(16) BITS

5.5±0.5µs

400ns

330ns

P

10.75±0.5µs

7.5±0.5µs

2.3µs

450ns

500ns

Note: All timing is typical unless otherwise noted.

REF

STAT

RTAP

7.5±0.5µs

4.5±0.5µs

400ns

(NO TIMEOUT)

Figure 18 – RT-RT Transfer Timing

15 8 7 0

SET TO "0"

SET TO "0"

CHAN B XMITTER TIMEOUT

CHAN A XMITTER TIMEOUT

CHAN B LOOP TEST FAILURE

CHAN A LOOP TEST FAILURE

CHAN B XMITTER SHUTDOWN

CHAN A XMITTER SHUTDOWN

NON-MODE BROADCAST CMD TO XMIT

MESSAGE HIGH WORD COUNT

MESSAGE LOW WORD COUNT
ILLEGAL MODE CODE OR ILLEGAL

BROADCAST WITH MODE CODE
MODE CODE OR T/R ERROR

CHAN A/B LOOP TEST FAILURE

HANDSHAKE FAILURE

Notes:
(1) Bits 0-2 and 10-13 are latched and only cleared by a mode reset command or a master RESET
(2) Bits 3-7 are cleared at the start of each new message and updated at the end of the message. They reflect the present

command word.

(3) Bits 8-9 are set by the mode command for Transmitter Shutdown and are cleared by the mode command for Override

Transmitter Shutdown, Reset RT or a master RESET

CHAN A/B XMITTER TIMEOUT

.

.

Figure 19 – Bit Word

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MT Operation

In the MT mode, the CT2565 captures all valid
transmissions on both channels of the 1553 bus, allowing
the user to monitor bus activity. Each word is transferred to
the subsystem along with an identification for interpretation
of the 1553 data stream.

MT Initialization

Initialize the CT2565 for MT operation per Table 2. The
CT2565 will remain in an idle state until BCSTART

(pin 41)

is pulsed low. Figure 21 illustrates MT operation.
Valid words received by the CT2565 are transferred to the

subsystem along with an identification Word by a single
DMA handshake with two memory-write operations shown
in Figure 22, MT Transfer Timing. Since the decoder will
reject words based on sync field errors and/or errors in the
first 2 non-sync bits, these words will not be processed
further (i.e., the subsystem will receive no indication of the
receipt of this word).

START

INITIALIZATION

(START-UP ONLY)

START MT OPERATION

1553 BUS
ACTIVITY

DECODER CHECK

SYNC + 2 BITS

15 8 7 0

GAP TIME

WORD TRANSFER

LOGIC "1"

LOGIC "1"

VALID WORD

COMMAND SYNC

CH A/B

WORD GAP

SET TO "0"

NAME Definition

GAP TIME NODT low time. 2MHz Clock

WORD TRANSFER

WORD TRANSFERRED

VALID WORD

allows 500ns increments to
128µs (remains static at FF on
overflow).

Logic "1" indicates successful
transfer to subsystem.

Indicates successful transfer
(See bit 7)

Reset (1) indicates Manchester
error, Parity error, Low Bit Count
and/or Status sync field.

YES

ERROR

?

NO

NODT LOW

DMA

MEMORY WRITE

1553 INPUT

INCREMENT MEM ADDR

MEMORY WRITE

IDENTIFICATION WORD

INCREMENT MEM ADDR

Notes:
(1) Steps marked with " ___" indicates operation is

transparent to user.

(2) Steps marked with " ___" indicates user interaction

required.

YES

COMMAND SYNC Logic "1" indicates Command or

Status sync field. Logic"0"
indicates data sync.

CHAN A/B

WORD GAP

Logic "1" if word received on
1553 bus Channel B.

Set (0) if current word was
received at least 2µs after
receipt of previous word (parity
to mid-sync).

Note: Subsystem should clear entire memory prior to start of MT
operation.

Figure 20 – Identification Word

Figure 21 – MT Operation Flow Chart

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Simultaneous Transmission

Transmissions appearing simultaneously on
alternate 1553-bus channels will be captured by
CT2565 sequentially providing that each
BUSREQ is answered by the subsystem with a
BUSGRNT within the handshake timeout period.

RESET Signal

Pulsing RESET low will suspend MT operation by
(1) INCMD goes high (EOM goes low on the rising
edge) and (2) the CT2565 enters an idle state.
MT operation may be restored by pulsing
BCSTART low (above) or another mode of
operation may be selected (See Table 2).

BUSREQ (19)

t

1

t

BUSGRNT

(45)

2

t

3

Handshake Failure

Note that a handshake failure will abort the
current transfer. Monitoring will resume upon
receipt of a valid word on the 1553 bus.

MODE CODES

Nine of the 13 available, dual redundant mode
codes are handled by the CT2565 without user
intervention. Of the four remaining codes,
Dynamic Bus Control and Synchronize (no data)
require subsystem notification. The remaining
two mode codes, Transmit Vector Word and
Synchronize (with data) involve data transfer with
the subsystem. Mode command illegalization and
handling are detailed in the RTU Operation
section and listed in Table 8.

BUSACK

ADRINC

(59)

WR (44)

CS

(17)

(49)

D0 - D15

t

4

t

6

t

5

t

7

DATA VALID

t

8

t

10

ID-WORD VALID

t

6

t

6

t

8

t

9

CYCLE SYM DESCRIPTION MIN TYP MAX UNITS

Handshake t1

Write Only t4

t10

t2

t3

t5

t6

t7

t8

t9

BUSREQ to BUSGRNT delay

BUSGRNT pulse width

BUSGRNT to BUSACK delay

BUSACK to WR delay

WR to CS time
WR and CS pulse width

DATA VALID setup

CS to ADRINC delay

ARINC pulse width
ID WORD VALID setup

0 - 800 ns

166 - - ns

? - ? ns

320 330 370 ns

- - 25 ns

150 166 175 ns

- - 50 ns

- - 25 ns

80 - 166 ns

- - 100 ns

Figure 22 – MT Transfer Timing

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DYNAMIC BUS CONTROL (00000)

MESSAGE SEQUENCE = DBC * STATUS

The CT2565 responds with status. If the subsystem wants control of the bus, it must set DBACC within 2.5us after NBGRT.

ERROR CONDITIONS

1.

Invalid Command.
Command Followed by Data Word.

2.

T/R bit Set to Zero.

3.

Zero T/R bit and Broadcast Address.

4.

No response, command ignored.

No status response. Bits set: message error (SW), High word Count (BIT Word).

No status response. Bits set: message error (SW), T/R Error (Bit Word).

No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R

Error (BIT Word).

Broadcast Address.

5.

No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code (BIT Word).

SYNCHRONIZE WITHOUT DATA WORD (00001)

MESSAGE SEQUENCE = SYNC * STATUS

The CT2565 responds with status. If sent as a broadcast, the broadcast receive bit will be set and status response suppressed.

ERROR CONDITIONS

1.

Invalid Command.
Command Followed by Data Word.

2.

T/R bit Set to Zero.

3.

Zero T/R bit and Broadcast Address.

4.

No response, command ignored.

No status response. Bits set: message error (SW), High Word Count (BIT Word).

No status response. Bits set: message error (SW), T/R Error (BIT Word).

No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R

Error (BIT Word).

TRANSMIT STATUS WORD (00010)

MESSAGE SEQUENCE = TRANSMIT STATUS * STATUS

The status and BIT word registers are not altered by this command and contain the resulting status from the previous command.

ERROR CONDITIONS

1.

Invalid Command.
Command Followed by Data Word.

2.

T/R bit Set to Zero.

3.

Zero T/R bit and Broadcast Address.

4.

No response, command ignored.

No status response. Bits set: message error (SW), High Word Count (BIT Word).

No status response. Bits set: message error (SW), T/R Error (BIT Word).

No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R

Error (BIT Word).

Broadcast Address.

5.

No status response. Bits set: message error, broadcast received (S/W), Illegal Mode code, T/R Error (BIT Word).

INITIATE SELF-TEST (00011)

MESSAGE SEQUENCE = SELF TEST * STATUS

The CT2565 responds with a status word. If the command was broadcast, the broadcast received bit is set and status transmission
suppressed. Short-loop test is initiated on the status word transmitted. If the test fails, an RT fail flag is generated.

ERROR CONDITIONS

1.

Invalid Command.
Command Followed by Data Word.

2.

T/R bit Set to Zero.

3.

Zero T/R bit and Broadcast Address.

4.

Faulty Test.

5.

No response, command ignored.

No status response. Bits set: message error (SW), High Word Count (BIT Word).

No status response. Bits set: message error (SW), T/R Error (BIT Word).

No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word).

Bits set: terminal flag (SW), A/B Loop Test Fail, Current 1553 Bus (A or B) Loop Test Fail (BIT Word).

TRANSMITTER SHUTDOWN (00100)

MESSAGE SEQUENCE - SHUTDOWN * STATUS

This command is only used with dual redundant bus systems. The CT2565 responds
with status. At the end of the status transmission, the CT2565 inhibits any further transmission from the dual redundant channel. Once
shutdown, the transmitter can only be re-activated by Override Transmitter Shutdown or RESET RT commands.

ERROR CONDITIONS

1.

Invalid Command.
Command Followed by Data Word.

2.

T/R bit Set to Zero.

3.

Zero T/R bit and Broadcast Address.

4.

No response, command ignored.

No status response. Bits set: message error (SW), High Word Count (BIT Word).

No status response. Bits set: message error (SW), T/R Error BIT Word).

No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R

Error (BIT Word).

Table 8 – Mode Codes

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OVERRIDE TRANSMITTER SHUTDOWN (00101)

MESSAGE SEQUENCE - OVERRIDE SHUTDOWN - STATUS

This command is only used with dual redundant bus systems. The CT2565 responds with status. At the end of the status transmission, the
CT2565 re-enables the transmitter of the redundant bus. If the command was broadcast, the broadcast received bit is set and status
transmission is suppressed.

ERROR CONDITIONS

1.

Invalid Command.
Command Followed by Data Word.

2.

T/R bit Set to Zero.

3.

Zero T/R bit and Broadcast Address.

4.

No response, command ignored.

No status response. Bits set: message error (SW), High Word Count (BIT Word).

No status response. Bits set: message error (SW), T/R Error (BIT Word).

No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R

Error (BIT Word).

INHIBIT TERMINAL FLAG BIT (00110)

MESSAGE SEQUENCE - INHIBIT TERMINAL FLAG * STATUS

The CT2565 responds with status and inhibits further internal or external setting of the terminal flag bit in the status register. Once the
terminal flag has been inhibited, it can only be reactivated by an Override Inhibit Terminal Flag or Reset RT command. If the command was
broadcast, the broadcast received bit is set and status transmission is suppressed.

ERROR CONDITIONS

1.

Invalid Command.
Command Followed by Data Word.

2.

T/R bit Set to Zero.

3.

Zero T/R bit and Broadcast Address.

4.

No response, command ignored.

No status response. Bits set: message error (SW), High Word Count (BIT Word).

No status response. Bits set: message error (SW), T/R Error (BIT Word).

No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word).

OVERRIDE INHIBIT TERMINAL FLAG BIT (00111)

MESSAGE SEQUENCE - OVERRIDE INHIBIT TERMINAL FLAG * STATUS

The RTU responds with status and reactivates the terminal flag bit in the status register. If the command was broadcast, the broadcast
received bit is set and status transmission is suppressed.

ERROR CONDITIONS

1.

Invalid Command.
Command Followed by Data Word.

2.

T/R bit Set to Zero.

3.

Zero T/R bit and Broadcast Address.

4.

No response, command ignored.

No status response. Bits set: message error (SW), High Word Count (BIT Word).

No status response. Bits set: message error (SW), T/R Error (BIT Word).

No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word).

RESET REMOTE TERMINAL (01000)

MESSAGE SEQUENCE - RESET REMOTE TERMINAL * STATUS

The CT2565 responds with status and internally resets. Transmitter shutdown, mode commands, and inhibit terminal flag commands will
be reset. If the command was broadcast, the broadcast received bit is set and the status word is suppressed.

ERROR CONDITIONS

1.

Invalid Command.
Command Followed by Data Word.

2.

T/R bit Set to Zero.

3.

Zero T/R bit and Broadcast Address.

4.

No response, command ignored.

No status response. Bits set: message error (SW), High Word Count (BIT Word).

No status response. Bits set: message error (SW), T/R Error (BIT Word).

No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word).

RESERVED MODE CODES (01001-01111)

MESSAGE SEQUENCE = RESERVED MODE CODES * STATUS

The CT2565 responds with status. If the command is illegalized through an optional PROM, the message error bit is set and only the status
word is transmitted.

ERROR CONDITIONS

1.

Invalid Command.
Command Followed by Data Word.

2.

T/R bit Set to Zero.

3.

Zero T/R bit and Broadcast Address.

4.

No response, command ignored.

No status response. Bits set: message error (SW), High Word Count (BIT Word).

No status response. Bits set: message error (SW), Illegal Mode Code (BIT Word).

No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code (BIT

Word).

Table 8 – Mode Codes (continued)

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TRANSMIT VECTOR WORD (10000)

MESSAGE SEQUENCE - TRANSMIT VECTOR WORD * STATUS VECTOR WORD

The CT2565 transmits a status word followed by a vector word. The contents of the vector word (from the subsystem) are enabled onto
DBO-DB15 with BUSREQ after the command transfer (same as data word in a normal transmit command).

ERROR CONDITIONS

1.

Invalid Command.
Command Followed by Data Word.

2.

T/R bit Set to Zero.

3.

Zero T/R bit and Broadcast Address.

4.

No response, command ignored.

No status response. Bits set: message error (SW) High Word Count (BIT Word).

No status response. Bits set: message error (SW), T/R Error, Low Word Count (BIT Word).

No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R

Error, Low Word Count (BIT Word).

Broadcast Address.

5.

No status response. Bits set: message error, broadcast received (SW), Illegal Mode code, (BIT Word).

SYNCHRONIZE WITH DATA WORD (10001)

MESSAGE SEQUENCE - SYNCHRONIZE DATA WORD * STATUS

The data word received following the command word is transferred to the subsystem. The status register is then enabled and its contents
transferred onto the data bus and transmitted. If the command was broadcast, the broadcast received bit is set and status transmission is
suppressed.

ERROR CONDITIONS

1.

Invalid Command.
Command Not Followed by Data Word.

2.

Command followed by too many Data Words.

3.

Command T/R bit Set to One.

4.

Command, T/R bit Set to One and Broadcast Address.

5.

No response, command ignored.

No status response. Bits set: message error (SW), Low Word Count (BIT Word).

No status response. Bits set: message error (SW), High Word Count (BIT word).

No status response. Bits set: message error (SW), T/R Error, High Word Count (BIT Word).

No status response. Bits set: message error, broadcast received (SW), High

Word Count, T/R Error (BIT Word).

TRANSMIT LAST COMMAND (10010)

MESSAGE SEQUENCE = TRANSMIT LAST COMMAND * STATUS LAST COMMAND

The status and BIT word registers are not altered by this command. The SW contains the status from the previous command. The data
word transmitted contains the previous valid command (providing it was not another TRANSMIT LAST COMMAND).

ERROR CONDITIONS

1.

Invalid Command.
Command Followed by Data Word.

2.

T/R bit Set to Zero.

3.

Zero T/R bit and Broadcast Address.

4.

Broadcast Address.

5.

No response, command ignored.

No status response. Bits set: message error (SW).

No status response. Bits set: message error (SW), T/R Error, Low Word Count (BIT Word).

No status response. Bits set: message error, (SW), Illegal Mode Code T/R Error (BIT Word).

No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code (BIT Word).

TRANSMIT BIT WORD (10011)

MESSAGE SEQUENCE - TRANSMIT BIT WORD * STATUS BIT WORD

The CT2565 transmits a status word followed by the BIT word . When activated, BITEN allows the subsystem to latch the BIT word on the
parallel data bus. The BIT word is not altered by this command; however, the next SW will reflect errors in this transmission.

ERROR CONDITIONS

1.

Invalid Command.
Command Followed by Data Word.

2.

T/R bit Set to Zero.

3.

Zero T/R bit and Broadcast Address.

4.

No response, command ignored.

No status response. Bits set: message error (SW).

No status response. Bits set: message error (SW), T/R Error, Low Word Count (BIT Word).

No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R

Error, Low Word Count (BIT Word).

Broadcast Address.

5.

No status response. Bits set: message error, broadcast received (SW), Illegal Mode code, (BIT Word).

Table 8 – Mode Codes (continued)

23

Aeroflex Circuit Technology

SCDCT2565 REV B 8/10/99 Plainview NY [phone]

SELECTED TRANSMITTER SHUTDOWN (10100)

MESSAGE SEQUENCE - TRANSMITTER SHUTDOWN DATA * STATUS

The data word received is transferred to the subsystem and status is transmitted. If the
command was broadcast, the broadcast received bit is set and status transmission suppressed. Intended for use with RTs with more than
one dual redundant channel.

ERROR CONDITIONS

1.

Invalid Command.

Command Not Followed by Data Word.

2.

No response, command ignored.

No status response. Bits set: message error (SW), High Word Count, Illegal Mode Code (BIT

Word).

Command Followed by too many Data Words.

3.

No status response. Bits set: message error (SW), Low Word Count, Illegal Mode Code

(BIT Word).

Command T/R bit Set to One.

4.

Command T/R bit Set to One and Broadcast Address.

5.
Mode Code, High Word Count (BIT Word).

No status response. Bits set: message error (SW), Illegal Mode Code, High word count (BIT Word).

No status response. Bits set: message error, broadcast received (SW), Illegal

OVERRIDE SELECTED TRANSMITTER SHUTDOWN (10101)

MESSAGE SEQUENCE - TRANSMITTER SHUTDOWN DATA * STATUS

The data word received after the command word is transferred to the subsystem. If the
command was broadcast, the broadcast received bit is set and status transmission suppressed.

ERROR CONDITIONS

1.

Invalid Command.

Command Not Followed by Data Word.

2.

No response, command ignored.

No status response. Bits set: message error (SW), Low Word Count, Illegal Mode Code (BIT

Word).

Command Followed by too many Data Words.

3.

No status response. Bits set: message error (SW), High Word Count, Illegal Mode Code

(BIT Word).

Command T/R bit Set to One.

4.

Command T/R bit Set to One and Broadcast Address.

5.

No status response. Bits set: message error (SW), Illegal Mode Code, High Word Count (Bit Word).

No status response. Bits set: message error, broadcast received (SW), Illegal

Mode Code, High Word Count, T/R (BIT Word).

RESERVED MODE CODES

MESSAGE SEQUENCE = RESERVED MODE CODE (T/R = 1) * STATUS
RESERVED MODE CODE (T/R = 0) * STATUS

The CT2565 responds with status. If the command was broadcast, the broadcast received bit is set and status transmission suppressed.

ERROR CONDITIONS (T/R = 1)

1.

Invalid Command.

Command Followed by Data Word.

2.

No response, command ignored.

No status response. Bits set: message error (SW), High Word Count, Illegal Mode Code (BIT

Word).

ERROR CONDITIONS (T/R = 0)

1.

Invalid Command.

Command not Followed by Contiguous Data Word.

2.

No response, command ignored.

No status response. Bits set: message error (SW), High word Count, Illegal Mode

Code (BIT Word).

Command Followed by too many Data Words.

3.

No status response. Bits set: message error (SW), High Word Count, Illegal Mode

Code (BIT Word).

Table 8 – Mode Codes (continued)

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Aeroflex Circuit Technology

SCDCT2565 REV B 8/10/99 Plainview NY [phone]

Table 9A – Pin Function Table (78 Pin DDIP)

Pin # Symbol Description

1 RT/BC

2 MT

Mode Select input - logic "1" for RT mode, logic “0” for BC mode.

Monitor mode enable. When unit is operating as a BC, a logic “0” will select monitor
mode.

3 STATEN

Output signal in RT mode that indicates status word is being transferred on the
internal bus.

4 TIMEOUT

5 HSFAIL

Indicates No Response Timeout has occured during BC and RTU (RT to RT transfer).

Output in RT mode indicating the DMA transfer did not occur in time to allow proper
operation on the 1553 bus.

6 DBACCEPT

Input signal used to set DBACCEPT bit in status register for response to a valid mode
command on the 1553 bus.

7 SSFLAG

8 SVCREQ

9 INCMD

10 SSER

11 TESTOUT

Input which controls the SSFLAG bit in the status register.

Input which controls the service request bit in the status word.

Output signal indicating the RT is currently in a message transfer sequence.

Input which controls the subsystem error bit in the status register.

Factory test point. Do not connect.

12 WC1 WC bit 1 - latched output of command word.

13 WC3 WC bit 3 - latched output of command word.

14 TXINH B Transmitter inhibit output for channel B.

15 T/R

16 CHA

/CHB Output indicating current selected channel (0 = Channel A).

17 CS

18 OE

19 BUSREQ

Output indicating T/R bit of current command word in RT mode.

Chip Select output for subsystem memory control.

Output Enable output for subsystem memory control.

Output signal used to initiate transfer to/from subsystem.

20 +5V +5 Volt DC input.

21 DB0 Least significant bit - 16 bit parallel data bus.

22 DB2 Bit 2 of data bus.

23 DB4 Bit 4 of data bus.

24 DB6 Bit 6 of data bus.

25 DB8 Bit 8 of data bus.

26 DB10 Bit 10 of data bus.

27 DB12 Bit 12 of data bus.

28 DB14 Bit 14 of data bus.

29 LWORD Last word output during BC mode indicates last data word of the current message

transfer has been transferred on the parallel bus.

25

Aeroflex Circuit Technology

SCDCT2565 REV B 8/10/99 Plainview NY [phone]

Table 9A – Pin Function Table (78 Pin DDIP) (continued)

Pin # Symbol Description

30 MSGERR Output signal which indicates an error occurred during the current message

sequence.

31 TXDATA A Bipolar serial data output to positive input of bus transceiver.

32 RXDATA A

Bipolar serial input from negative output of bus transceiver.

33 RTADP Parity bit input for RT address.

34 RTAD1 Bit 1 of RT address input.

35 RTAD3 Bit 3 of RT address input.

36 RESET

37 TXDATA B

System reset input - resets all inputs in module.

Bipolar serial data output to negative input bus transceiver.

38 RXDATA B Bipolar serial data input from positive output of bus transceiver.

39 12MHz 12MHz TTL clock input.

40 GROUND Signal ground.

41 BCSTART

42 NBGRNT

43 BITEN

44 WR

45 BUSGRNT

Cycle enable input Logic "0" initiates bus controller message transfer operation.

New bus grant output from RT indicates beginning of message transfer sequence.

Built in Test enable output indicates RT is transferring BlT word on internal 16 bit bus.

Write enable output for control of subsystem memory.

Bus request input in response to DTREQ. Allows BC/RT to transfer data to
subsystem.

46 LOOPERR

47 SSBUSY

48 ILLCMD

49 ADRINC

Loop error output. Logic "0" indicates failure of loop back transmitted data.

Subsystem busy input for RT status word.

Illegal command input to RT, used to block RT response to an illegal command.

Increment output pulse. Goes LOW at the completion of each word transfer to/from
subsystem. Can increment external address counter.

50 CHASSIS Frame ground electricity isolated from signal ground

51 WC0 LSB of current command word count field.

52 WC2 Bit 2 of word count field.

53 WC4 Bit 4 of word count field.

54 TXINH A Transmitter inhibit output signal for Channel A.

55 LMC Latched Mode Command. Logic "1" indicates current word command is a mode code

word, WC0-WC4.

56 TESTIN

57 EOM

58 BUFENA

Factory test point. Do not connect.

End of message output. Logic "0" occurs when BC/RT message is completed.

Buffer enable input, may be driven LOW by STATEN or BITEN if subsystem must read
bit or Status words. Enables internal 16 bit bus onto subsystem bus.

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Aeroflex Circuit Technology

SCDCT2565 REV B 8/10/99 Plainview NY [phone]

Table 9A – Pin Function Table (78 Pin DDIP) (continued)

Pin # Symbol Description

59 BUSACK Bus acknowledge output. LOW during DMA Handshake, in response to BUSGRNT.

60 DB1 Bit 1 of 16 bit parallel bus.

61 DB3 Bit 3 of 16 bit parallel bus.

62 DB5 Bit 5 of 16 bit parallel bus.

63 DB7 Bit 7 of 16 bit parallel bus.

64 DB9 Bit 9 of 16 bit parallel bus.

65 DB11 Bit 11 of 16 bit parallel bus.

66 DB13 Bit 13 of 16 bit parallel bus.

67 DB15 Bit 15 of 16 bit parallel bus.

68 STATERR

BC output indicates one or more bits set or address mismatch in a received status
word.

69 TXDATA A

Bipolar serial data output to negative input of bus transceiver.

70 RXDATA A Bipolar serial data input from positive output of bus transceiver.

71 NODT

No data input. Logic "0" indicates the 1553 bus is idle; HIGH means device front end is
active.

72 RTAD0 LSB of 5 bit RT address.

73 RTAD2 Bit 2 of RT address.

74 RTAD4 Bit 4 of RT address.

75 BCSTRCV

Broadcast receive. Logic "0" means the current command was a broadcast command.

76 TXDATA B Bipolar serial output to positive input of bus transceiver.

77 RXDATAB

78 SOM

Bipolar serial input from negative output of bus transceiver.

Start of message output indicates beginning of RT/BC message transfer sequence.

27

Aeroflex Circuit Technology

SCDCT2565 REV B 8/10/99 Plainview NY [phone]

Table 9B – CT2565 Pin Out Description

(DDIP)

1

41

2

42

3

43

4

44

5

45

6

46

7

47

8

48

9
49
10
50
11
51
12
52
13
53
14
54
15
55
16
56
17
57
18
58
19
59
20

RT/BC

BCSTART
MT
NBGRNT
STATEN
BITEN
TIMEOUT
WR
HSFAIL
BUSGRNT
DBACCEPT
LOOPERR
SSFLAG
SSBUSY
SVCREQ
ILLCMD
INCMD
ADRINC
SSER
CASE GND
TESTOUT
WC0
WC1
WC2
WC3
WC4
TXINH B
TXINH A
T/R
LMC
CHB/CHA
TESTIN
CS
EOM

OE

BUFENA
BUSREQ
BUSACK
+5 Volt

CT2565

MIL-STD-1553

BUS Controller,

Remote Terminal and

BUS MONITOR

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8

DB9
DB10
DB11
DB12
DB13
DB14

DB15 (MSB)

LWORD

STATERR

MSGERR
TXDATA A
TXDATA A

RXDATA A
RXDATA A

NODT

RTADP

RTAD0
RTAD1
RTAD2
RTAD3
RTAD4

RESET

BCSTRCV

TXDATA B
TXDATA B

RXDATA B
RXDATA B

12MHz

SOM

GND

21
60
22
61
23
62
24
63
25
64
26
65
27
66
28
67
29
68
30
69
31
70
32
71
33
72
34
73
35
74
36
75
37
76
38
77
39
78
40

Pin

Function

#

1

RT/BC

2 MT

3 STATEN 42 NBGRNT

4 TIMEOUT 43 BITEN

5 HSFAIL 44 WR

6 DBACCEPT 45 BUSGRNT

7 SSFLAG 46 LOOPERR

8 SVCREQ 47 SSBUSY

9 INCMD 48 ILLCMD

10 SSER 49 ADRINC

11 TESTOUT 50 CASE GND

12 WC1 51 WC0

13 WC3 52 WC2

14 TXINH B 53 WC4

15 T/R

16 CHB/CHA

17 CS

18

OE

19 BUSREQ 58 BUFENA

20 + 5 Volt 59 BUSACK

21 DB0 (LSB) 60 DB1

22 DB2 61 DB3

23 DB4 62 DB5

24 DB6 63 DB7

25 DB8 64 DB9

26 DB10 65 DB11

27 DB12 66 DB13

28 DB14 67 DB15 (MSB)

29 LWORD 68 STATERR

30 MSGERR 69 TXDATA A

31 TXDATA A 70 RXDATA A

32 RXDATA A

33 RTADP 72 RTAD0

34 RTAD1 73 RTAD2

35 RTAD3 74 RTAD4

36 RESET

37 TXDATA B 76 TXDATA B

38 RXDATA B 77 RXDATA B

39 12MHz 78 SOM

Pin

#

40 GND

41 BCSTART

54 TXINH A

55 LMC

56 TESTIN

57 EOM

71 NODT

75 BCSTRCV

Function

DDIP Pin Connection Diagram, CT2565 and Pinout

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Aeroflex Circuit Technology

SCDCT2565 REV B 8/10/99 Plainview NY [phone]

Table 10 – CT2565 Pin Out Description

(FP)

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41

N/C

RT/BC
BCSTART
MT
NBGRNT
STATEN
BITEN
TIMEOUT
WR
HSFAIL
BUSGRNT
DBACCEPT
LOOPERR
SSFLAG
SSBUSY
SVCREQ
ILLCMD
INCMD
ADRINC
SSER
CASE GND
TESTOUT
WC0
WC1
WC2
WC3
WC4
TXINH B
TXINH A
T/R
LMC
CHB/CHA
TESTIN
CS
EOM
OE
BUFENA
BUSREQ
BUSACK
+5V
N/C

CT2565FP

MIL-STD-1553

BUS Controller,

Remote Terminal and

BUS MONITOR

N/C

DB0 (LSB)

DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8

DB9
DB10
DB11
DB12
DB13
DB14

DB15 (MSB)

LWORD

STATERR

MSGERR
TXDATA A
TXDATA A

RXDATA A
RXDATA A

NODT

RTADP

RTAD0
RTAD1
RTAD2
RTAD3
RTAD4

RESET

BCSTRCV

TXDATA B
TXDATA B

RXDATA B
RXDATA B

12MHz

SOM

GROUND

N/C

82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42

Pin

Function

#

1 N/C 42 N/C

2 RT/BC

3 BCSTART

4 MT 45 12MHz

5 NBGRNT

6 STATEN 47 RXDATA B

7 BITEN

8 TIMEOUT

9 WR 50 BCSTRCV

10 HSFAIL 51 RESET

11 BUSGRNT 52 RTAD4

12 DBACCEPT

13 LOOPERR

14 SSFLAG 55 RTAD1

15 SSBUSY

16 SVCREQ

17 ILLCMD

18 INCMD 59 RXDATA A

19 ADRINC 60 RXDATA A

20 SSER

21 CASE GND 62 TXDATA A

22 TESTOUT 63 MSGERR

23 WC0 64 STATERR

24 WC1 65 LWORD

25 WC2 66 DB15 (MSB)

26 WC2 67 DB14

27 WC4 68 DB13

28 TXINH B 69 DB12

29 TXINH A 70 DB11

30 T/R

31 LMC 72 DB9

32 CHB/CHA

33 TESTIN

34 CS

35 EOM

36 OE

37 BUFENA

38 BUSREQ

39 BUSACK

40 +5V 81 DB0 (LSB)

41 N/C 82 N/C

Pin

43 GROUND

44 SOM

46 RXDATA B

48 TXDATA B

49 TXDATA B

53 RTAD3

54 RTAD2

56 RTAD0

57 RTADP

58 NODT

61 TXDATA A

71 DB10

73 DB8

74 DB7

75 DB6

76 DB5

77 DB4

78 DB3

79 DB2

80 DB1

Function

#

Flat Package Pin Connection Diagram, CT2566 and Pinout

29

Aeroflex Circuit Technology

SCDCT2565 REV B 8/10/99 Plainview NY [phone]

Lead 1 & ESD
Designator

2.100

1.870

.110

1.650

Pin 82

.100

Pin 1

1.500

Pin 21

1.900

Pin 2

Pin 41

Pin 60

Pin 22

.050

.100

TYP

TYP

Pin 19

Pin 39

Pin 20

Pin 59

.018 DIA

TYP

Pin 78

Pin 40

1.800

Figure 23 – Plug In Package Outline

2.200
MAX

.050

.015

Pin 42

.250

MAX

.250

.010

±.002

.180

MAX

Lead 1 & ESD
Designator

Designator

.400

MIN

.095

(4 Places)

1.610
MAX

MAX

Pin 41

2.000

.050 Lead Centers

41 Leads/Side

Figure 24 – Flat Package Outline

30

.080

Aeroflex Circuit Technology

SCDCT2565 REV B 8/10/99 Plainview NY [phone]

CIRCUIT TECHNOLOGY

Ordering Information

Model Number Screening DESC SMD # Package

CT2565 Military Temperature, -55°C to +125°C,

CT2565-FP - Flat Package

CT2565-001-1 Per SMD 5962-8858501XA Plug in

CT2565-001-2 5962-8858501XC Plug in

CT2565-201-1 5962-8858501YA Flat Package

CT2565-201-2 5962-8858501YC Flat Package

Screened to the individual test methods

of MIL-STD-883

- Plug in

Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11803
www.aeroflex.com/act1.htm

Specifications subject to change without notice

Telephone: [phone]
FAX: [phone]

Toll Free Inquiries: (800) THE-1553

E-Mail: [e-mail]

31