Datasheet CT1820 Datasheet (ACT)

CT1820

F

E

I

D

C

E

R

T

A

E

R

O

F

L

E

X

L

A

B

S

I

N

C

.

43

7

4546474850

444241

234565456

56

43

43

43

53

D1

(LSB) D0

D2D3D4D5D6D7D8

D9

D10

D11

D12

D13

D14

(MSB) D 15

(OPTION AL)

SERIA L

INPUT

LATCH

DATA

2

LATCH DATA 1

LOAD

DATA 2

LOAD DATA 1

DATA SELECT 1

DATA

SELECT 2

Data Terminal Bit Processor

for MIL-STD-1553 A & B

Features

• Performs Encoder, Decoder, Logic and Control functions of a Data Bus Terminal to
MIL-STD-1553 specifications, including Address, Mode Code and Broadcast Decoding and
Terminal Fail Safe

• Flexibility - all control lines accessible

• Parallel tri-state subsystem l/O bus compatible with both 16 bit and 8 bit systems

• Dual rank l/O registers for versatile subsystem tlmlng

• Operates from +5VDC @ 40mA typical (25mA CT1820)

• Self-contained oscillator and clock driver

• Look-ahead serial receive data output

• Self-test, on-line wraparound, plus off-line capability

1

General Description

The CT1555-3/CT1820 Bit Processor Unit (BPU) is an advanced Hybrid Microcircuit that provides the interface between a
MIL-STD-1553 Transceiver such as CT3231M or CT3232M, and the subsystem internal parallel data bus. The unit can be
employed as the mux bus interface for Remote Subsystems or Master Terminal Bus Controllers, thus providing a common
interface for all systems communicating over the bus.
The unit places no restrictions on Command, Response or polling operations as it transfers all Command, Status and Data
words from the bus to parallel output lines, together with error information, bus status and handshaking signals. It also
contains 5 Bit Address Recognition, Broadcast and Mode Code Decode, Terminal Fail Safe Signal and Self Test.
In the transmit mode, it accepts parallel data from the user and transmits Command, Status and Data words, under
subsystem control, to the data bus. Positive handshaking signals provide logic control synchronisation between the unit
and the subsystem for direct data flow.
The hybrid is completely compatible with all the electrical and functional spec requirements of MIL-STD-1553 A & B.

ISO

9001

I

5 BIT

ADDRESS

36

32

12

8

9

10

{

13

39

40

14

16

33

37

31

SERIAL DATA OUT

RT ENABLE

(MSB) A4

A3

A2

A1

(LSB) A0

BROADCAST

MODE CODE

VALID WORD

COMM/DATA SYNC

DEC RST

TAKE DATA

DSC OUT

FIRST
RANK
REC’V

REG

DO - D7

FIRST
RANK
REC’V

REG

D8 - D15

ADDRESS

DECODE

BROAD-

CAST

DECODE

MODE

CODE

DECODE

SECOND

DO - D7

SECOND

D8 - D15

RANK
REC’V

REG

RANK
REC’V

REG

MANCHESTER

DECODER

&

CONTROL LOGIC

MANCHESTER

ENCODER

&

CONTROL LOGIC

OSC

&
CLOCK
DRIVER

FIRST
RANK

XMT
REG

DO - D7

FIRST
RANK

XMT
REG

D8 - D15

FAIL SAFE

TIMER

&

CONTROL

SECOND

RANK

XMT
REG

DO - D7

SECOND

RANK

XMT
REG

D8 - D15

BUILT IN

TEST

SELECT

+5V OSC / CLOCK POWER

DATA IN

DATA IN

BIT SELECT

DATA OUT

DATA OUT

FAIL SAFE

SEND DATA

ESCOUT

SYNC SEL

ENC ENA

OUTPUT INH

MRST

XTAL

CLOCK OUT

CLOCK IN

Vcc

+5V

GND

GND

CASE

1

11

34

20

21

22

19

25

26

15

27

28

24

23

35

38

30

29

18

17

Figure 1 – Functional Diagram

eroflex Circuit Technology – Data Bus Modules For The Future © SCDCT1820 REV D 6/25/99

Aeroflex Circuit Technology SCDCT1820 REV D 6/25/99 Plainview NY [phone]

DATA

Figure 2 – Typical MIL-STD-1553 Data Terminal

BUS

RX

DATA

IN

TX

DATA

OUT

TX

DATA

OUT

RX

DATA

IN

25

1

CT3231

HYBRID

2

26

T/R

31

TX

INHIBIT

TX

DATA

32

IN

TX

33

DATA

IN

RX

DATA

OUT

7

RX

DATA

10

OUT

DATA

OUT

DATA

OUT

DATA

IN

DATA

IN

25

26

CT1820

CT1553

PROCESSOR

21

22

Absolute Maximum Ratings

OR

BIT

29

DATA

XTAL

CONTROL

12

MHz

16 BIT

OR
8 BIT
SUB-

SYSYEM

Parameter Units

Supply Voltage

Logic Input Voltage

Logic Input Current

Clock Output Current (Pin 18)

Clock In (Pin 17)

Storage Temperature Range

Operating Case Temperature Range

-0.3 to VCC +0.3V V

+7.0 V

-0.3 to +5.5 V

-20 to +4 mA

15 mA

-65 to +150 °C

-55 to +125 °C

Electrical Characteristics

(VCC = 5.0V ±5%)

Sym Parameter / Conditions Min Typ Max Units

IH

V

V

V

V

V

V

Logic "1" Input Voltage

IL

Logic "0" Input Voltage

OH

Logic "1" Output Voltage

OL

Logic "0" Output Voltage

IHC

Logic "1" Input Voltage (CLOCK)

ILC

Logic "0" Input Voltage (CLOCK)

2.0 - - V

- - 0.7 V

See Pin assignments and Loading

See Pin assignments and Loading

CC-0.5 - V

V

- GND+0.5 V

OHC

V

OLC

V

OC

l

OSC

l

Logic "1" Output Voltage (CLOCK)

Logic "0" Output Voltage (CLOCK)

Logic Supply Current

Oscillator / Clock Supply Current

2

CC-0.3 - V

V

- GND+0.3 V

- 40 - mA

8 13 mA

Aeroflex Circuit Technology SCDCT1820 REV D 6/25/99 Plainview NY [phone]

PIN ASSIGNMENTS AND LOADING

In the following table, the symbols are defined as follows:

IH= maximum input HIGH current with VIN = 2.5 volts

I

IL = maximum input LOW current with VIN = 0.4 volts

I

OH = maximum output HIGH current for VOUT = 2.5 volts minimum

I

OL = maximum output LOW current for VOUT = 0.4 volts maximum

I

* Indicates use of an internal pull-up resistor

Pin

No

1 VCC +5V Power Input

2 D8 40 -0.4 -1000 2.4 20 -0.4 -1000 6.0 10.0 Part of 16 Bit TRI-STATE l/O

3 D9

4 D10

5 D11

6 D12

7 DATA SELECT 1 20 -0.4 20 -0.4 A LOW on this input applies the contents of the SECOND

8 A3* -1500 -3.2 20 -0.4 Part of 5 Bit ADDRESS INPUT

9 A2*

10 A1*

11 GROUND Logic and power return

12 A4* -1500 -3.2 20 -0.4 MSB of 5 Bit ADDRESS INPUT

13 A0* LSB of 5 Bit ADDRESS INPUT

14 VALID WORD -400 2.4 -400 4.0 4.0 A LOW on this output indicates receipt of avalid word

15 FAIL SAFE -400 2.4 -400 4.0 4.0 A HIGH on this output indicates termination of a

16 COMM / DATA

17 CLOCK IN ±30 ±0.003 +100-3+100

18 CLOCK OUT -1000 1.0 -1000 1.0 1.0 Output of OSCILLATOR AND CLOCK DRIVER.

19 S / T SELECT 40 -0.8 20 -0.4 A HIGH on this input sets the unit in the self test mode.

20 CASE CASE CONNECTION

21 DATA IN 20 -0.4 20 -0.4 A HIGH on this input represents a positive state on the

22 DATA IN 20 -0.4 20 -0.4 A HIGH on this input represents a negative state on the

23 ENC ENA 20 -0.4 20 -0.4 A LOW on this input initiates a transmit cycle.

24 SYNC SEL 20 -0.4 20 -0.4 Actuates COMMAND (or STATUS) sync for an input LOW

25 DATA OUT 360 2.4 -400 4.0 4.0 A HIGH on this output produces a positive state on the

26 DATA OUT 360 2.4 -400 4.0 4.0 A HIGH on this output produces a negative state on the

27 SEND DATA 380 2.4 -400 4.0 4.0 A HlGH on this output indicates data shifting during the

28 ESC OUT 1000 1.2 -1000 1.2 1.2 LOW to HIGH transitions on thls output during HIGH

29 XTAL A 12MHz (parallel resonant) crystal is connected between

30 +5V OSC / CLOCK

31 DSC OUT -1000 1.2 -1000 1.2 1.2 LOW to HIGH transitions on this output during LOW TAKE

32 RT ENABLE -400 2.4 -400 4.0 4.0 A HIGH on this output indicates reception of a valid

Name CT1555-3 CT1820 CT1820-2 Description

I

IH

IL

OH

OL

IH

IL

OH

OL

OL

I

I

(mA)

RANK REC’V REG to the D8-D15 I/O pins

transmitted message that exceeds 768µs.

word reception. A LOW indicates DATA word reception.

Input for 12MHz clock (20pf load).

bus.

bus. (Pins 21 and 22 must both be high when the bus is
inactive.)

and DATA sync for an input HIGH.

bus.

bus.

transmit cycle.

SEND DATA cause the transmit cycle data shifting to
occur.

this pin and ground.

+5V power for OSCILLATOR AND CLOCK POWER
DRIVER.

DATA cause receive cycle data shifting to occur.

COMMAND (or STATUS) word containing the terminalís
address. It also resets the FAIL SAFE.

POWER

I

I

I

I

I

(µA)

(µA)

(µA)

(mA

(µA)

SYNC - 380 2.4 -400 4.0 4.0 A HIGH on this output indicates COMMAND (or STATUS)

(µA)

-3

I

(µA)

(mA

3

Aeroflex Circuit Technology SCDCT1820 REV D 6/25/99 Plainview NY [phone]

Pin

No

Name CT1555-3 CT1820 CT1820-2 Description

IH

IL

OH

OL

IH

IL

OH

OL

I

(µA)

I

(µA)

I

(µA)

I

(mA

I

(µA)

I

(µA)

I

(µA)

(mA

OL

I

I

(mA)

33 DEC RST 20 -0.4 20 -0.4 A LOW on this input (for 1µs minimum) resets the decoder

to a condition ready for a new word, resets the COMM /
DATA

SYNC output LOW, and resets the VALID WORD

output HIGH.

34 GROUND Logic and Power Return.

35 OUTPUT INH 20 -0.4 20 -0.4 A LOW on this input holds output pins 25 and 26 LOW.

36 SERIAL DATA OUT -400 1.6 -400 4.0 4.0 The received serial data in NRZ format is available at this

pin during LOW TAKE DATA

.

37 TAKE DATA -360 2.4 -400 4.0 4.0 A LOW on this output indicates data shifting during the

receive cycle.

38 MRST 60 -1.2 20 -0.4 A LOW on this input (for 1µs minimum) interrupts and

clears the transmit cycle, resets the FAIL SAFE, and also
performs the same functions as DEC RST

.

39 BROADCAST* -300 1.6 -400 4.0 4.0 A HIGH on this output indicates reception of a valid

COMMAND (or STATUS) word containing all ONES in the
address field.

40 MODE CODE* -600 2.4 -600 6.0 6.0 A LOW on this output indicates reception of a valid

COMMAND (or STATUS) word containing all ONES or all
ZEROS in the sub-address field.

41 D6 40 -0.4 -1000 2.4 20 -0.4 -1000 6.0 10.0 Part of 16 Bit TRI-STATE l/O

42 D7

43 DATA SELECT 2 20 -0.4 20 -0.4 A LOW on this input applies the contents of the SECOND

RANK REC’V REG to the D0-D7 I/O pins.

44 D5 40 -0.4 -1000 2.4 20 -0.4 -1000 6.0 10.0 Part of 16 Bit TRI-STATE l/O

45 D0 LSB of 16BIT TRI-STATE I/O

46 D1 Part of 16 Bit TRI-STATE l/O

47 D2 Part of 16 Bit TRI-STATE l/O

48 D3 Part of 16 Bit TRI-STATE l/O

49 LATCH DATA 2 20 -0.4 A HIGH on this input allows the l/O data on D0-D7 to

appear at the output of the FIRST RANK XMT REG. A
LOW on this input holds the register outputs in their last
state.

50 D4 40 -0.4 -1000 2.4 -1000 6.0 Part of 16 Bit TRl-STATE l/O

51 LOAD DATA 2 60 -1.2 A LOW on this input loads the D0-D7 data into the

SECOND RANK XMT REG. A HIGH on this input then
locks out the data inputs to permit serial shifting.

52 LATCH DATA 1 20 -0.4 A HIGH on this input allows the l/O data on D8-D15 to

appear at the output of the FIRST RANK XMT REG. A
LOW on this input holds the register outputs in their last
state.

53 LOAD DATA 1 60 -1.2 20 -0.4 A LOW on this input loads the D8-D15 data into the

SECOND RANK XMT REG. A HIGH on this input then
locks out the data inputs to permit serial shifting.

54 D13 40 -0.4 -1000 2.4 -1000 6.0 10.0 Part of 16 Bit TRl-STATE l/O.

55 D14

OPTIONAL SERIAL INPUT.

56 D15

4

Aeroflex Circuit Technology SCDCT1820 REV D 6/25/99 Plainview NY [phone]

TRANSMIT CYCLE OPERATION

Figure 3 – Transmit Cycle Timing

ENCODER SHIFT CLOCK (ESC) (see Figure 3)
operates at the data rate (1MHz). A low at
ENCODER ENABLE (ENC ENA) during a falling

edge of ESC
lasts for twenty ESC clock periods. The SYNC

SELECT (SYNC SEL) input is valid at the next
low-to-high transition of ESC

SEL will produce a data sync, or a low will produce
a command sync for that word.

Parallel data must be stable at the second rank
transmit register before SEND DATA goes high
Since ENC ENA
minimum time to
edge.

The first-rank transmit register may be operated
transparently (LATCH DATA always high), or may be
used to hold data ready for transmission,
independent of the activity on the 16-line subsystem
l/O bus. As long as LATCH DATA is held high, data
present on the subsystem l/O bus appears at the
output of the first rank transmit register. Stable data
may be latched and held at the first rank register
output by bringing LATCH DATA low. Data to be
transmitted may be latched any time before the
low-to high transition of SEND DATA (SEND DATA,
when appled to the LOAD DATA inputs, locks out
the data inputs to the second rank transmit
register.) For multiple word transmissions, the next

word may be inputted and latched any time after
but before the next low to-high transition of SEND
DATA.

① starts the Transmit cycle, which

②. A high at SYNC

③.

is not synchronous with ESC, the

③ is 3µsec from ENC ENA leading

③,

SEND DATA remains high for 16 ESC periods,
during which the parallel transmit data is clocked to

the MANCHESTER ENCODER

③ to ④. After the

sync and Manchester coded data are transmitted
through the DATA OUT and DATA OUT

ENCODER adds on the parity bit for that word

outputs, the

⑤.

If the transmitted word is to be the last word of the
transmission, ENC ENA

must go high by ⑤ to

prevent initiation of another transmit cycle.

At any time, a low applied to OUTPUT INHIBIT will
force both DATA OUT and DATA OUT

to a low state

without affecting any other operations.

The entire transmit cycle may be interrupted and
cleared by applying a minimum of 1µsec negative
pulse to the MASTER RESET

(MRST) input.

For 8-BlT I/O subsystems, D0 is tied to D8, D1 to
D9, etc., through D7 tied to D15, and data is
inputted in 8-BlT bytes by using LATCH DATA 1 and
LATCH DATA 2 and / or LOAD DATA 1

and LOAD

DATA 2 independently.

For serial data applications, D15 input serves as the
serial transmit input. With LOAD DATA 1

held low
and LATCH DATA 1 held high, D15 input is applied
to the ENCODERís serial data input. Inputted data
must be at the ESC rate with the MSB starting at
the low-to-high transition of SEND DATA.

If a message length ever exceeds 768µsec, the
768µsec TIME OUT (FAIL SAFE) flag goes high,
and DATA OUT and DATA OUT

are both forced to a
low state. This condition will remain until a valid
command word (containing the terminalís address)
is received or until MRST

goes low.

0 1 2 3 4 5 16 17 18 19 0 1 2 3

ESC

ENC ENA

SYNC

SEL

DATA SELECT

LATCH DATA

SEND DATA
& LOAD DATA

DATA OUT

DATA OUT

IF USED

VALID

DON’T CARE

½ SYNC ½ SYNC 15 14 13 2 1 0 P ½ SYNC ½ SYNC 15 14 13 2 1 0 P

½ SYNC ½ SYNC 15 14 13 2 1 0 P ½ SYNC ½ SYNC 15 14 13 2 1 0 P

1

2

DON’T CARE

DON’T CARE

SEE

TEXT

3

DEPENDS ON "LATCH" TIMING

OPTIONAL NEXT-WORD LATCH

VALID

4 5

5

DON’T CARE

DON’T CARE

SEE

TEXT

4 5

DEPENDS ON "LATCH" TIMING

OPTIONAL NEXT-WORD LATCH

16 17 18 19

Aeroflex Circuit Technology SCDCT1820 REV D 6/25/99 Plainview NY [phone]

ENCODER

SHIFT CLOCK

ENCODER

ENABLE

SYNC

SELECT

SEND DATA

& LOAD DATA

LATCH DATA

(IF USED)

PARALLEL

DATA IN

DATA

SELECT

TE2

TE1

VALID

TE4

TE3

0

1

TE10

TE7

2

TE5

TE6

TE8

TE9

TE11

Symbol Description Min Max Units

E1 ENCODER ENABLE SET-UP TIME 100 - ns

T

T

T

T

T

T

T

T

T

T

T

E2

E3

E4

E5

E6

E7

E8

E9

E10

E11

ENCODER ENABLE PULSE WIDTH

SYNC SELECT SET-UP TIME

SYNC SELECT 'VALID' PULSE WIDTH

SEND DATA DELAY

LATCH DATA HOLD TIME

LATCH DATA SET UP TIME

LATCH DATA PULSE WIDTH LOW

PARALLEL DATA 'VALID' WIDTH

DATA SELECT DISABLE TIME

DATA SELECT PULSE WIDTH HIGH

180 - ns

190 - ns

150 - ns

- 70 ns

25 - ns

50 - ns

50 - ns

75 - ns

25 - ns

100 - ns

Figure 4 – Encoder Timing Detail

6

Aeroflex Circuit Technology SCDCT1820 REV D 6/25/99 Plainview NY [phone]

RECEIVE CYCLE OPERATION

DECODER SHIFT CLOCK (DSC) (see Figure 5)
operates at the data rate (1MHz). When the
DECODER recognises a valid sync and two valid

Manchester data bits
The new sync is indicated at the COMMAND/DATA
SYNC (C/D SYNC) output and the TAKE DATA
output goes low
in its valid state until a new sync is detected on a
subsequent word or until DECODER RESET
RST) or MRST goes low. A low at DEC RST or
MRST causes C/D SYNC to go low.

TAKE DATA

remains low for 16 DSC periods during
which time the 16 serial data bits appear at the
SERIAL DATA OUTPUT (SDO). This data is
simultaneously loaded into the first-rank receive

register. The low-to-high transition of TAKE DATA
makes the new data available at the output of the
second-rank receive register. This data remains
available until the next low-to-high transitions of
TAKE DATA

. It is not reset or cleared by any other

signals. This data is applied to the D0 to D15 I/O

①, a receive cycle is initiated.

②. The C/D sync output will remain

(DEC

③

bus by setting DATA SELECT

lines low.

After all data has been loaded into the receive
registers, the data is checked for odd parity. A low

on VALID WORD

(VW) output ③, indicates

successful reception of a word without any
Manchester or parity errors. For consecutive word
receptions, VW

will go high again in 3 to 3.5µs. In
the absence of succeeding valid syncs, VW will
return high in 20µs. A DEC RST

(low) at any time

will reset VW high.

All decoded commands, including RT ENABLE
(address recognition), BROADCAST and MODE
CODE are enabled internally by VW and remain
valid only as long as VW is low.

For 8-BIT l/O subsystems (D0 tied to D8, through
D7 tied to D15), data may be extracted in 8 BIT
bytes by selectively activating DATA SELECT 1

and

DATA SEL.ECT 2.

For serial data systems, SERIAL DATA OUTPUT is
available at the DSC rate from

② to ③.

OSC

DATA IN

DATA IN

TAKE DATA

C/D SYNC

SDO

VW

DECODE COMMANDS

(see text)

SECOND-RANK REC’V

REGISTER CONTENT

DATA SELECT

0 1 2 3 4 5 16 17 18 19 0 1 2 3 4 5 16 17 18 19

½ SYNC ½ SYNC 15 14 13 2 1 0 P ½ SYNC ½ SYNC 15 14 13 2 1 0 P

½ SYNC ½ SYNC 15 14 13 2 1 0 P ½ SYNC ½ SYNC 15 14 13 2 1 0 P

FROM PREVIOUS WORD

UNDEFINED

FROM PREVIOUS WORD

15 4 3 2 1 0 15 4 3 2 1 0

NOT VALID

FROM PREVIOUS WORD

OPTIONAL–HIGH = TRISTATE HI-Z AT D0 TO D15 OPTIONAL–HIGH = TRISTATE HI-Z AT D0 TO D15

1

2

VALID FOR CURRENT WORD VALID FOR CURRENT WORD

UNDEFINED

NEW DATA

4

3

VALID

NOT VALID VALID

Figure 5 – Receive Cycle Timing

NEW DATA

7

Aeroflex Circuit Technology SCDCT1820 REV D 6/25/99 Plainview NY [phone]

DECODER

SHIFT CLOCK

TAKE
DATA

SYNC

C/D

VALID
WORD

BROADCAST

RT ENABLE

MODE
CODE

DATA

SELECT

PARALLEL
DATA OUT

LAST STATE

5 194

TD1

TD3

LAST STATE NEW SYNC

TD2

TD4

TD5

TD6

TD7

TD8

TD9

NEW DATA

Symbol Description Min Max Units

D1

T

D2

T

D3

T

D4

T

D5

T

D6

T

D7

T

D8

T

D9

T

TAKE DATA RELAY ON

TAKE DATA DELAY OFF

SYNC DELAY

VALID WORD DELAY

BROADCAST DELAY

RT ENABLE DELAY

MODE CODE DELAY

DATA SELECT INPUT DELAY

PARALLEL DATA OUTPUT DELAY

Notes: 1. DATA SELECT may be applied at any tlme that the 16 line I/O is otherwise free.

The parallel DATA OUT, however, is not ’NEWDATA’ until 50ns after TAKE DATA

2. 180ns max for CT1555-3.

- 125 ns

- 125 ns

- 50 ns

- 125 ns

- 70 ns

- 100 ns

- 100 ns

0 (Note 1) - ns

- 50 (Note 2) ns

goes high.

Figure 6 – Decoding Timing Detail

8

Aeroflex Circuit Technology SCDCT1820 REV D 6/25/99 Plainview NY [phone]

SELF TEST FUNCTION

A high on the S/T SELECT input sets the hybrid in
the SELF TEST mode. In this mode, the DATA and
DATA output lines are connected to the Decoder
inputs so that the unit may operate in the
"wraparound" mode without actually going through
the data bus transceiver. Note that the DATA and
DATA

output lines are active in this mode and the
S/T SELECT command must also be used to inhibit
the data bus transmitter to prevent arbitrary
transmission on the data bus.

TERMINAL FAIL SAFE

In order to satisfy the Terminal Fail Safe
requirements of MIL-STD-1553B, the DATA and
DATA output lines are continuously monitored for
length of message. A transmitted message in
excess of 768µs sets the FAIL SAFE output high
and terminates the transmission by setting both
DATA and DATA

output lines low. As a redundant
safety factor, the FAlLSAFE output may be applied
to the lNHlBlT input of the data bus transmitter (if so
equipped). Further transmissions are prevented
until the FAIL SAFE flag is reset either by reception
of a valid command word containing the terminal
address or by a negative pulse on the MRST

input.
Note: Transmissions containing gaps of 3µs or less
are considered continuous, even if the gap is
caused by a MRST

pulse.

TERMINAL ADDRESS LINES

The five-bit terminal address is set by hard wiring
the 5-BlT ADDRESS lines. The hybrid contains
internal pull-up resistors so that logic "1" lines may
be left open circuited. Logic "0" lines must be
grounded.

In operation, RT ENABLE goes high when a valid
command word containing the hard-wired address
is received. See "RECEIVE CYCLE OPERATION"
for timing.

clock or an external clock source.

For internal clock operation, a 12MHz
parallel-resonant fundamental-mode crystal must
be connected from XTAL to ground. Power (+5V)
must be applied to +5V OSC/CLOCK POWER and
CLOCK OUT must be connected to CLOCK IN.

For external clock operation, no power is applied to
+5V OSC/CLOCK POWER and the external clock is
applied to CLOCK IN (CLOCK OUT not connected).
The external clock must be capable of driving a 20
picofarad load to within 0.5 volts of VCC and within

0.5 volts of ground with rise and fall times of less
than 10 nanoseconds. Standard TTL levels are not
satisfactory. For a normal 1MHz data rate, the clock
frequency must be 12MHz.

FALSE RT ENABLE

Terminals that continuously monitor their own
transmissions are subject to "END-AROUND"
operation due to a false RT ENABLE. The terminal
can erroneously interpret its own status word as a
new command word. If no measures are taken to
prevent or re-set RT ENABLE, it will remain high for
20µs or until the DECODER recognises a new valid
sync (whichever time is shorter).

RT ENABLE may be inhibited by interrupting the
RECEIVE CYCLE during a status word
transmission. Inverted SEND DATA applied to DEC
RST will prevent reception of the status word.

If continuous monitoring is required, RT ENABLE
may be reset immediately after it goes high by a 1µs
(minimum) low at DEC RST
then be available at the second-rank receive
register.

. The status word will

OSCILLATOR AND CLOCK DRIVER

The hybrid may be operated with either the internal

9

Aeroflex Circuit Technology SCDCT1820 REV D 6/25/99 Plainview NY [phone]

CIRCUIT TECHNOLOGY

Ordering Information

Model Number Package

CT1820

2.155" x 1.14" Metal Plug In

Plug-In Package Outline

2.155 MAX

1.900

48

49

TOP VIEW

1.155 .900

56

29

28

.450 REF

21

201

.100 TYP

.200 MAX

.175 MIN

.018 DIA TYP

±.002

Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11830

Specifications subject to change without notice.

10

Toll Free Inquiries: 1-(800)THE-1553

Telephone: [phone]
FAX: [phone]