Datasheet CS8129YTVA5, CS8129YTHA5, CS8129YT5, CS8129YDWR16, CS8129YDW16 Datasheet (Cherry Semiconductor)
Page 1
1
5V, 750mA Low Dropout Linear
Regulator with Lower RESET Threshold
Features
■ 5V +/- 3% Regulated
Output
■ Low Dropout Voltage
(0.6V @ 0.5A)
■ 750mA Output Current
Capability
■ Reduced Threshold
for use with 4V Microprocessors
■ Externally Programmed
Delay
■ Fault Protection
Reverse Battery
60V, -50V Peak Transient
Voltage
Short Circuit
Thermal Shutdown
RESET
RESET
Package Options
5 Lead TO-220
CS8129
V
IN
NC
NC
Gnd
Gnd
NC
Delay
RESET
V
OUT
NC
V
OUT(SENSE)
Gnd
Gnd
Gnd
NC
NC
Description
The CS8129 is a precision 5V linear regulator capable of sourcing 750mA.
The threshold voltage has been
lowered to 4.2V so that the regulator
can be used with 4V microprocessors.
The lower threshold also permits operation under low battery conditions (5.5V plus a diode). The Õs
delay time is externally programmed
using a discrete RC network. During
power up, or when the output goes out
of regulation, remains in the
low state for the duration of the delay.
This function is independent of the
input voltage and will function correctly as long as the output voltage remains
at or above 1V. Hysteresis is included in
the Delay and the comparators
to improve noise immunity. A latching
discharge circuit is used to discharge
the delay capacitor when it is triggered
by a brief fault condition.
The regulator is protected against a
variety of fault conditions: i.e. reverse
battery, overvoltage, short circuit and
thermal runaway conditions. The regulator is protected against voltage transients ranging from -50V to +40V. Short
circuit current is limited to 1.2A (typ).
The CS8129 is packaged in a 5 lead
TOÐ220 and a 16 lead surface mount
package.
RESET
RESET
RESET
RESET
RESET
Block Diagram
CS8129
1V
IN
2
3 Gnd
4 Delay
5V
OUT
RESET
1
16 Lead SOIC Wide
A Company
¨
Rev. 3/31/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
Pre-
Regulator
Charge
Current
Generator
Regulated Supply
for Circuit Bias
Bandgap
Reference
Thermal
Shutdown
Over Voltage
Shutdown
Error
Amplifier
-
+
Anti-Saturation
and
Current Limit
V
V
V
IN
OUT
OUT
SENSE
1
Delay
Gnd
Latching Discharge
QRS
-
+
VDISCHARGE
-
+
Delay Comparator
+
-
RESET
Page 2
* To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable.
Delay Time = = C
Delay
x 3.5 x 105(typ)
Note 1: assuming ideal capacitor
C
Delay
x V
Delay Threshold Charge
I
Charge
Electrical Characteristics: -40ûC ² T
A
² + 125ûC, -40ûC ² TJ ² +150ûC, 6V ² V
IN
² 26V, 5mA ² I
OUT
² 500mA, R = 4.7k½ to V
OUT
unless otherwise noted*
RESET
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Absolute Maximum Ratings
Input Operating Range..................................................................................................................................................-0.5 to 26V
Power Dissipation.............................................................................................................................................Internally Limited
Peak Transient Voltage (46V Load Dump @ 14V VIN) ...............................................................................................-50V, 60V
Output Current .................................................................................................................................................Internally Limited
ESD Susceptibility (Human Body Model)..............................................................................................................................4kV
Junction Temperature.............................................................................................................................................-55¡C to 150¡C
Storage Temperature...............................................................................................................................................-55¡C to 150¡C
Lead Temperature Soldering
Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260¡C peak
Reflow (SMD styles only) ......................................................................................60 sec. max above 183¡C, 230¡C peak
CS8129
2
■ Output Stage (V
OUT
)
Output Voltage 4.85 5.00 5.15 V
Dropout Voltage I
OUT
= 500mA 0.35 0.60 V
Supply Current I
OUT
² 10mA 2 7 mA
I
OUT
² 100mA 6 12
I
OUT
² 500mA 55 100
Line Regulation 6V ² V
IN
² 26V, I
OUT
= 50mA 5 50 mV
Load Regulation 50mA ² I
OUT
² 500mA, VIN= 14V 10 50 mV
Ripple Rejection f = 120Hz, VIN= 7 to 17V, 54 75 dB
I
OUT
= 250mA
Current Limit 0.75 1.20 A
Overvoltage Shutdown 32 40 V
Reverse Polarity Input V
OUT
³ -0.6V, 10½ Load -15 -30 V
Voltage DC
Thermal Shutdown Guaranteed by Design 150 180 210 ¡C
■ and Delay Functions
Delay Charge Current V
DELAY
= 2V 5 10 15 µA
Threshold V
OUT
Increasing, V
RT(ON)
4.05 4.35 4.50 V
V
OUT
Decreasing, V
RT(OFF)
4.00 4.20 4.45 V
Hysteresis VRH=V
RT(ON)
- V
RT(OFF)
50 150 250 mV
Delay Threshold Charge, V
DC(HI)
3.25 3.50 3.75 V
Discharge, V
DC(LO)
2.85 3.10 3.35 V
Delay Hysteresis 200 400 800 mV
Output Voltage Low1V < V
OUT
< V
RT(L)
, 3k½ to V
OUT
0.1 0.4 V
Output Leakage V
OUT
> V
RT(H)
010µA
Current
Delay Capacitor Discharge Latched ÒONÓ, 0.2 0.5 V
Discharge Voltage V
OUT
> V
RT
Delay Time C
DELAY
= 0.1µF (Note 1) 16 32 48 ms
RESET
RESET
RESET
RESET
RESET
Page 3
3
Typical Performance Characteristics
0.0
0.0
I
CQ
(mA)
VIN (V)
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
20.0
40.0
60.0
80.0
100.0
120.0
R
load
= 6.67W
R
load
= 10W
R
load
= 25W
R
load
= NO LOAD
Room Temp.
0.0
0.0
V
OUT
(V)
VIN (V)
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
R
load
= 25W
125ûC
25ûC
-40ûC
Output Voltage vs Input Voltage over Temperature
Quiescent Current vs Input Voltage over Load Resistance
Quiescent Current vs Input Voltage over Temperature
V
OUT
vs. VINover R
LOAD
Package Lead Description
PACKAGE LEAD # LEAD SYMBOL FUNCTION
CS8129
-100
0
LINE REGULATION (mV)
OUTPUT CURRENT (mA)
-80
-60
-40
-20
0
20
40
60
80
100
100 200 300 400 500 600 700 800
VIN 6-26V
TEMP = 25ûC
TEMP = -40ûC
TEMP = 125ûC
Load Regulation vs. Output Current
Line Regulation vs. Output Current
R
load
=25½
16L SOIC Wide 5L TO-220
11VINUnregulated supply voltage to IC.
16 5 V
OUT
Regulated 5V output.
4, 5, 11, 12, 13 3 Gnd Ground connection.
8 4 Delay Timing capacitor for function.
6 2 CMOS/TTL compatible output lead. goes low whenev-
er V
OUT
drops below 6% of it's regulated value.
14 N/A V
OUT(SENSE)
Remote sensing of output voltage.
RESETRESET
RESET
55.0
R
= 25W
50.0
45.0
40.0
35.0
30.0
(mA)
25.0
CQ
I
20.0
15.0
10.0
5.0
0.0
load
25ûC
125ûC
-40ûC
0.0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
VIN (V)
5.5
Room Temp.
5.0
4.5
(V)
OUT
V
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Rload =
NO LOAD
Rload = 10W
Rload = 6.67W
0.0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
0.0
VIN (V)
6
4
2
0
-2
-4
-6
-8
LOAD REGULATION (mV)
-10
-12
-14
100 200 300 400 500 600 700 800
0
TEMP = -40ûC
TEMP = 25ûC
VIN = 14V
TEMP = 125ûC
OUTPUT CURRENT (mA)
Page 4
4
CS8129
Test & Application Circuit
CIN*
100nF
V
IN
Delay
Gnd
RESET
V
OUT
CS8129
C
OUT
**
10mF to 100mF
R
RST
4.7kW
Delay
0.1mF
Ripple Rejection
Quiescent Current vs. Output Current
Dropout Voltage vs. Output Current
Typical Performance Characteristics Continued
10
0
ESR (ohms)
Output Current (mA)
10
1
10
2
10
3
10
1
10
2
10
3
10
-4
10
0
10
-1
10
-2
10
-3
C
OUT
= 68mF
C
OUT
= 47mF
C
OUT
= 47/68mF
Stable Region
Output Capacitor ESR
*CINrequired if regulator is far from the power source filter.
**C
OUT
required for stability.
900
800
700
600
500
400
300
200
DROPOUT VOLTAGE (mV)
100
0
0
100 200 300 400 500 600 700 800
OUTPUT CURRENT (mA)
I
90
OUT
80
70
60
50
40
30
REJECTION (dB)
20
10
0
0
10
C
= 10mF, ESR = 1W
OUT
C
10110210310410510610710
FREQUENCY (Hz)
125ûC
-40ûC
= 250mA
C
= 10mF, ESR = 1 & 0.1mF,
OUT
ESR = 0
= 10mF, ESR = 10W
OUT
25ûC
100
90
80
70
60
50
40
VIN = 14V
125ûC
25ûC
-40ûC
30
20
QUIESCENT CURRENT (mA)
10
0
100 200 300 400 500 600 700 800
0
OUTPUT CURRENT (mA)
8
Page 5
The CS8129 function has hysteresis on both the
reset and delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1V.
The circuit output is an open collector type with
ON and OFF parameters as specified. The output
NPN transistor is controlled by the two circuits described
(see Block Diagram).
This circuit monitors output voltage, and when output
voltage is below the specified minimum causes the
output transistor to be in the ON (saturation)
state. When the output voltage is above the specified level,
this circuit permits the output transistor to go into
the OFF state if allowed by the Delay circuit.
This circuit provides a programmable (by external capacitor) delay on the output lead. The Delay lead provides source current to the external delay capacitor only
when the "Low Voltage Inhibit" circuit indicates that out-
put voltage is above V
RT(ON)
. Otherwise, the Delay lead
sinks current to ground (used to discharge the delay
capacitor). The discharge current is latched ON when the
output voltage is below V
RT(OFF)
. The Delay capacitor is
fully discharged anytime the output voltage falls out of
regulation, even for a short period of time. This feature
ensures a controlled pulse is generated following
detection of an error condition. The circuit allows
the output transistor to go to the OFF (open) state
only when the voltage on the Delay lead is higher than
V
DC(HI)
.
The Delay time for the function is calculated from
the formula:
Delay time =
Delay time = C
Delay(µF)
x 3.2 x 10
5
If C
Delay
=0.1µF, Delay time (ms)=32ms ± 50%: i.e. 16ms to
48ms. The tolerance of the capacitor must be taken into
account to calculate the total variation in the delay time.
C
Delay
x V
Delay Threshold
I
Charge
RESET
RESET
RESET
RESET
Reset Delay Circuit
RESET
RESET
RESET
Low Voltage Inhibit Circuit
RESET
RESET
RESET
5
(1)
(2)
(3)
(2)
Delay
V
OUT
V
RT(ON)
V
RT(OFF)
V
RH
V
DC(HI)
V
DC(LO)
V
DH
t
Delay
V
DIS
V
RL
RESET
(1) = No Delay Capacitor
(2) = With Delay Capacitor
(3) = Max: Voltage (1.0V)
RESET
Circuit Waveform
RESET
Circuit Functional Description
RESET
CS8129
Page 6
6
CS8129
Application Notes
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start-up
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum
or aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25¡C to -40¡C), both the value and ESR of the least
expensive will vary considerably. The capacitor manufacturers data sheet usually provides this information.
The value for the output capacitor C
OUT
shown in the test
and applications circuit should work for most applications, however it is not necessarily the optimized solution.
To determine an acceptable value for C
OUT
for a particular
application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part.
Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade
box outside the chamber, the small resistance added by
the longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load
while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to
ensure a stable design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that
cause the greatest oscillation. This represents the worst
case load conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If
the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger
standard capacitor value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Remove the unit from the environmental chamber
and heat the IC with a heat gun. Vary the load current as
instructed in step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for
the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic
capacitors have a tolerance of +/- 20% so the minimum
value found should be increased by at least 50% to allow
for this tolerance plus the variation which will occur at
low temperatures. The ESR of the capacitor should be less
than 50% of the maximum allowable ESR found in step 3
above.
The maximum power dissipation for a single output regulator (Figure 1) is:
P
D(max)
={V
IN(max)ÐVOUT(min)
}
I
OUT(max)+VIN(max)IQ
(1)
where
V
IN(max)
is the maximum input voltage,
V
OUT(min)
is the minimum output voltage,
I
OUT(max)
is the maximum output current for the applica-
tion, and
IQis the quiescent current the regulator consumes at
I
OUT(max)
.
Once the value of P
D(max)
is known, the maximum permis-
sible value of R
QJA
can be calculated:
R
QJA
=
(2)
The value of R
QJA
can then be compared with those in
the package section of the data sheet. Those packages
with R
QJA
's less than the calculated value in equation 2
will keep the die temperature below 150¡C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
150¡C - T
A
P
D
Figure 1: Single output regulator with key performance parameters
labeled.
Stability Considerations
Calculating Power Dissipation
in a Single Output Linear Regulator
I
V
IN
IN
Regulator
Control
Features
}
Smart
I
Q
I
OUT
V
OUT
Page 7
7
Application Notes: continued
CS8129
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed
to determine the value of R
QJA
.
R
QJA
= R
QJC
+ R
QCS
+ R
QSA
(3)
where
R
QJC
= the junctionÐtoÐcase thermal resistance,
R
QCS
= the caseÐtoÐheatsink thermal resistance, and
R
QSA
= the heatsinkÐtoÐambient thermal resistance.
R
QJC
appears in the package section of the data sheet. Like
R
QJA
, it too is a function of package type. R
QCS
and R
QSA
are functions of the package type, heatsink and the interface between them. These values appear in heat sink data
sheets of heat sink manufacturers.
Heat Sinks
Page 8
8
Part Number Description
CS8129YDW16 16 Lead SOIC Wide
CS8129YDWR16 16 Lead SOIC Wide
(tape & reel)
CS8129YT5 5 Lead TO-220 Straight
CS8129YTHA5 5 Lead TO-220 Horizontal
CS8129YTVA5 5 Lead TO-220 Vertical
Rev. 3/31/99
Ordering Information
CS8129
D
Lead Count Metric English
Max Min Max Min
16 L SOIC Wide 10.50 10.10 .413 .398
Thermal Data 16 Lead 5 Lead
SOIC Wide TO-220
R
QJC
typ 23 2.1 ûC/W
R
QJA
typ 105 50 ûC/W
Package Specification
PACKAGE THERMAL DATA
PACKAGE DIMENSIONS IN mm (INCHES)
© 1999 Cherry Semiconductor Corporation
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
Surface Mount Wide Body (DW); 300 mil wide
1.27 (.050) BSC
7.60 (.299)
7.40 (.291)
10.65 (.419)
10.00 (.394)
D
0.32 (.013)
0.23 (.009)
1.27 (.050)
0.40 (.016)
REF: JEDEC MS-013
2.49 (.098)
2.24 (.088)
0.51 (.020)
0.33 (.013)
2.65 (.104)
2.35 (.093)
0.30 (.012)
0.10 (.004)
5 Lead TO-220 (T) Straight
2.87 (.113)
2.62 (.103)
6.93(.273)
6.68(.263)
9.78 (.385)
10.54 (.415)
1.02(.040)
0.63(.025)
1.83(.072)
1.57(.062)
0.56 (.022)
0.36 (.014)
2.92 (.115)
2.29 (.090)
1.40 (.055)
1.14 (.045)
4.83 (.190)
4.06 (.160)
6.55 (.258)
5.94 (.234)
14.22 (.560)
13.72 (.540)
1.02 (.040)
0.76 (.030)
3.71 (.146)
3.96 (.156)
14.99 (.590)
14.22 (.560)
5 Lead TO-220 (TVA) Vertical
1.68
(.066) typ
1.70 (.067)
7.51 (.296)
1.78 (.070)
4.34 (.171)
0.56 (.022)
0.36 (.014)
1.40 (.055)
1.14 (.045)
4.83 (.190)
4.06 (.160)
14.99 (.590)
14.22 (.560)
2.92 (.115)
2.29 (.090)
.94 (.037)
.69 (.027)
8.64 (.340)
7.87 (.310)
6.80 (.268)
10.54 (.415)
9.78 (.385)
2.87 (.113)
2.62 (.103)
6.55 (.258)
5.94 (.234)
3.96 (.156)
3.71 (.146)
5 Lead TO-220 (THA) Horizontal
0.81(.032)
1.70 (.067)
6.81(.268)
1.40 (.055)
1.14 (.045)
5.84 (.230)
6.60 (.260)
6.83 (.269)
0.56 (.022)
0.36 (.014)
10.54 (.415)
9.78 (.385)
6.55 (.258)
5.94 (.234)
3.96 (.156)
3.71 (.146)
1.68
(.066)
TYP
14.99 (.590)
14.22 (.560)
2.77 (.109)
2.29 (.090)
2.92 (.115)
4.83 (.190)
4.06 (.160)
2.87 (.113)
2.62 (.103)
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