Datasheet CS8120YTVA5, CS8120YTHA5, CS8120YT5, CS8120YN8, CS8120YDR14 Datasheet (Cherry Semiconductor)
...Page 1
1
Features
■
5V ± 4% Output Voltage
300mA
■ Low Dropout Voltage
(1V @ 150mA)
■ Low Quiescent Current
(2.5mA @ I
OUT
= 150mA)
■ µP Compatible Control
Functions
■ Low Current Sleep Mode
IQ=250µA
■ Fault Protection
Thermal Shutdown
Short Circuit
60V Load Dump
ENABLE
RESET
Package Options
5 Lead TO-220
Tab (Gnd)
14 Lead SOIC
Narrow
8 Lead PDIP
CS8120
5V, 300mA Linear Regulator with
and
ENABLE
RESET
1
CS8120
Description
The CS8120 is a 5V, 300mA precision
linear regulator with two microprocessor compatible control functions and
protection circuitry included on chip.
The composite NPN-PNP output pass
transistor assures a lower dropout voltage (1V @ 200mA) without requiring
excessive supply current (2.5mA).
The CS8120Õs two logic control functions make this regulator well suited to
applications requiring microprocessorbased control at the board or module
level. controls the output
stage. A high voltage (>2.9V) on the
lead turns off the regulatorÕs pass transistor and sends the IC
into Sleep mode where it draws only
250µA. The function sends a
signal when the IC is powering up or whenever the output voltage
moves out of regulation. The
signal is valid down to V
OUT
= 1V.
The CS8120 design optimizes supply
rejection by switching the internal
bandgap reference from the supply
input to the regulator output as soon as
the nominal output voltage is achieved.
Additional on chip filtering enhances
rejection of high frequency transients
on all external leads.
The CS8120 is fault protected against
short circuit, over voltage and thermal
runaway conditions.
RESET
RESET
RESET
ENABLE
ENABLE
Block Diagram *
V
IN
SENSE
NC
V
OUT
Gnd
NC
NC
NC
NC
NC
NC
NC
RESET
ENABLE
V
IN
ENABLE
Gnd
RESET
V
OUT
SENSE
NC
NC
1V
IN
2
3 Gnd
4
5V
OUT
RESET
ENABLE
* TO-220 Block Diagram
1
5 Lead D2 PAK
Rev. 2/3/98
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
A Company
¨
ENABLE
V
IN
ENABLE
-
Comparator
+
V
REF
TO V
Bandgap
Supply
OUT
Over
Voltage
Shutdown
Thermal
Shutdown
Bandgap
Reference
+
-
Error
Amplifier
Output
Current
Limit
V
OUT
1
1
RESET
RESET
Comparator
+
-
Gnd
Page 2
2
Electrical Characteristics: V
IN
= 14V, I
OUT
=5 mA, -40ûC ² TJ ² 150ûC, -40ûC ² TC ² 125ûC unless otherwise specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CS8120
Absolute Maximum Ratings
DC Input Voltage ...........................................................................................................................................................-0.7 to 26V
Load Dump .................................................................................................................................................................................60V
Output Current .................................................................................................................................................Internally Limited
Electrostatic Discharge (Human Body Model)......................................................................................................................2kV
Operating Temperature .......................................................................................................................................-40¡C to +125¡C
Junction Temperature...........................................................................................................................................-40¡C to +150¡C
Storage Temperature ............................................................................................................................................-55¡C to +150¡C
Lead Temperature Soldering
Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260¡C peak
Reflow (SMD styles only) ......................................................................................60 sec. max above 183¡C, 230¡C peak
* To have safe operating junction temperatures, low duty cycle pulse testing is used on tests where applicable.
■ Output Stage
Output Voltage, V
OUT
7V ² V
IN
² 26V, 1mA ² I
OUT
² 300mA 4.8 5.0 5.2 V
Line Regulation 7V ² V
IN
² 26V, I
OUT
= 200mA 50 mV
Load Regulation 1mA ² I
OUT
² 300mA 50 mV
Supply Voltage Rejection V
IN
= 14VDC + 1
VRMS
40 70 dB
@120Hz, I
LOAD
= 25½
Dropout Voltage I
OUT
= 200mA 1.0 1.5 V
Quiescent Current = High, V
IN
= 12V 0.25 0.65 mA
= Low, I
OUT
= 200mA 2.5 15.0 mA
■ Protection Circuits
Short Circuit Current 300 600 mA
Thermal Shutdown 150 190 ûC
Overvoltage Shutdown 26 40 V
■
Saturation Voltage 1V < V
OUT
< V
RT(OFF)
, 3.1k½ pull-up 0.1 0.4 V
to V
OUT
Output Leakage = Low 0 25 µA
Current V
OUT
> V
RT(ON)
, V = V
OUT
Power ON/OFF 3.1k½ pull-up to V
OUT
0.7 1.0 V
Peak Output Voltage
Threshold ON V
OUT
- 0.10 V
OUT
- 0.04 V
(V
OUT
Increasing)
Threshold OFF 4.75 V
OUT
- 0.14 V
(V
OUT
Decreasing)
Threshold Hysteresis 10 40 mV
■
Input High Voltage 7V < V
IN
< 26V 2.9 3.9 V
Input Low Voltage 7V < V
IN
< 26V 1.1 2.1 V
Input Hysteresis 7V < V
IN
< 26V 0.4 0.8 2.8 V
Input Current Gnd < V
IN(HI)
< V
OUT
-10 0 +10 µA
ENABLE
RESET
RESET
RESET
RESET
RESET
ENABLERESET
RESET
RESET
ENABLE
ENABLE
Page 3
Load Regulation vs. Output Current Over Temperature
5.02
5.01
5
4.99
4.98
4.97
4.96
4.95
-40 -20 0 20 40 60 80 100 120 140 150
Junction Temperature (°C)
V
OUT
(V)
5.00V @25°C
I
OUT
= 100mA
Output Voltage vs. Temperature
0
-10
0 50 100 150 200 250 300 350 400 450 500
10
20
30
40
50
-40° C
125° C
I
OUT
(mA)
Line Reg. (mV)
25°C
V
IN
= 7 to 25V
Line Regulation vs. Output Current Over Temperature
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
Output Current (mA)
Dropout Voltage (V)
-40°C
25°C
125°C
50 100
350
150
200 250 300
Dropout Voltage vs. Output Current Over Temperature
3
CS8120
Typical Performance Characteristics
Package Lead Description
PACKAGE LEAD # LEAD SYMBOL FUNCTION
5 Lead 8 Lead 14 Lead SO 5 Lead D
2
TO-220 PDIP Narrow PAK
12 1 1 VINSupply voltage to IC, usually direct from the battery.
2 4 5 2 CMOS compatible logical input. V
OUT
is disabled i.e.
placed in a high impedance state when is high.
3 8 13 3 Gnd Ground connection.
4 6 10 4 CMOS compatible output lead. goes low when-
ever V
OUT
falls out of regulation. The delay is
externally programmed.
51 14 5 V
OUT
Regulated output voltage, 5V (typ).
N/A 7 12 SENSE Kelvin Connection which allows remote sensing of out-
put voltage for improved regulation. If remote sensing is
not desired, connect to V
OUT
.
3, 5 2,3,4, NC No connection
6,7,8,9,11
RESET
RESET
RESET
ENABLE
ENABLE
0
-40° C
25° C
-10
-15
-5
VIN =14V
125° C
-20
-25
-30
Load Reg. (mV)
-35
-40
-45
-50
0 100 200 300 400 500
I
(mA)
OUT
Page 4
Precision Voltage Reference
The regulated output voltage depends on the precision
band gap voltage reference in the IC. By adding an error
amplifier into the feedback loop , the output voltage is
maintained within ±4% over temperature and supply
variation.
Output Stage
The composite PNPNPN output structure
(Figure 1) provides
300mA (typ) of output
current while maintaining a low drop out voltage (1.00V, typ) and
drawing little quiescent
current (2.5mA).
The NPN pass device prevents deep saturation of the output stage which in turn improves the ICÕs efficiency by
preventing excess current from being used and dissipated
by the IC.
Output Stage Protection
The output stage is protected against overvoltage, short
circuit and thermal runaway conditions (Figure 2).
4
CS8120
Circuit Description
Typical Performance Characteristics: continued
Voltage Reference and Output Circuitry
Figure 1: Composite Output Stage of the CS8120
5.5
10.0
0.0
Supply Voltage (V)
Supply Current (mA)
V
OUT
(V)
V
OUT
IQ
5.0
4.0
3.0
2.0
1.0
0.0
22.0
20.0
16.0
12.0
8.0
4.0
0.0
2.0 4.0 6.0 8.0
Output Voltage and Supply Current vs. Input Voltage
2000
1800
1600
1400
1200
1000
800
600
400
200
0
1 5 10 15 20 25 30 35 40
VIN = 5V
Reset Output Current (mA)
Reset Output Voltage (mV)
RESET Output Voltage vs. Output Current
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
050
-40°C
25°C
125°C
Output Current (mA)
Quiescent Current (mA)
VIN = 14V
100 150 200 250 300 350
Quiescent Current vs. Output Current Over Temperature
Figure 2: Typical Circuit Waveforms for Output Stage Protection.
V
IN
V
OUT
V
IN
V
OUT
I
OUT
> 30V
Load
Dump
Short
Circuit
Thermal
Shutdown
Page 5
If the input voltage rises above 26V (e.g. load dump), the
output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage
transients.
Using an emitter sense scheme, the amount of current
through the NPN pass transistor is monitored. Feedback
circuitry insures that the output current never exceeds a
preset limit.
Should the junction temperature of the power device
exceed 180ûC (typ) the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
The CS8120 contains two microprocessor compatible control functions: and (Figure 3).
Function
switches the output transistor. When the voltage
on the lead exceeds 2.9V typ, the output pass
transistor turns off, leaving a high impedance facing the
load. The IC will remain in Sleep mode, drawing only
250µA, until the voltage on the lead drops below 2.1V typ.
Hysteresis (800mV) is built into the function to
Figure 3: Circuit Waveforms for CS8120
provide good noise immunity.
Function
A signal (low voltage) is generated as the IC powers up (V
OUT
> V
OUT
- 100mV) or when V
OUT
drops out of
regulation (V
OUT
< V
OUT
- 140mV, typ). 40mV of hysteresis
is included in the function to minimize oscillations.
The output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
Figure 4: RC Network for Delay circuitry
guaranteeing that the signal is valid for V
OUT
as low
as 1V.
An external RC network on the lead (Figure 4) pro-
vides a sufficiently long delay for most microprocessor
based applications. RC values can be chosen using the following formula:
R
TOT
´ C
RST
where:
R
TOT
= R
RST
in parallel with R
IN,
RIN= µP port impedance,
C
RST
= delay capacitor,
t
Delay
= desired delay time,
V
RST
= V
SAT
of lead
(0.7V @ turn - on), and
V
T
= µP logic threshold voltage.
RESET
RESET
][
RESET
RESET
RESET
RESET
RESET
RESET
ENABLE
ENABLE
ENABLE
ENABLE
RESETENABLE
Regulator Control Functions
5
Ðt
Delay
ln
)
VTÐ V
OUT
V
RST
Ð V
OUT
(
Applications Notes
CS8120
The circuit depicted in Figure 5 lets the microprocessor
control its power source, the CS8120 regulator. An I/O
port on the µP and the SWITCH port are used to drive the
base of Q1. When Q1 is driven into saturation, the voltage
on the lead falls below its lower threshold. The
regulatorÕs output is switched out. When the drive current is removed, the voltage on the lead rises,
the output is switched off and the IC moves into Sleep
mode where it draws 250µA.
By coupling these two controls with , the system
has added flexibility. Once the system is running, the
state of the SWITCH is irrelevant as long as the I/O port
continues to drive Q1. The µP can turn off its own power
by withdrawing drive current, once the SWITCH is open.
This software control at the I/O port allows the µP to finish key housekeeping functions before power is removed.
The logic options are summarized in Table 1 below
ENABLE
ENABLE
ENABLE
Circuit Description: continued
Table 1: Logic Control of CS8120 Output
µP I/O drive SWITCH Output
ON Closed LOW ON
Open LOW ON
OFF Closed LOW ON
Open HIGH OFF
ENABLE
V
IN
ENABLE
V
OUT
RESET
HI
V
IN(HI)
LO
V
RT(ON)
V
RT(OFF)
VR
PEAK
H
FOR 7V < V
(1)
VR
(1) = NO RESET DELAY CAPACITOR
(2) = WITH RESET DELAY CAPACITOR
SAT
(2)
< 26V
IN
VR
PEAK
CS–8120
V
OUT
RESET
5V to mP
and
System
Power
C
R
RST
C
RST
2
22mF
to mP
RESET
Port
Page 6
6
Application Notes
The I/O port of the microprocessor typically provides
50µA to Q1. In automotive applications the SWITCH is
connected to the ignition switch.
The output or compensation capacitor, C
2
, helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum
or aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25¡C to -40¡C), both the value and ESR of the
capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information.
The value for the output capacitor C2shown in Figure 6
should work for most applications, however it is not necessarily the optimized solution.
To determine an acceptable value for C2for a particular
application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part.
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature
and monitor the outputs with an oscilloscope. A decade
box connected in series with the capacitor will simulate
the higher ESR of an aluminum capacitor. Leave the
decade box outside the chamber, the small resistance
added by the longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load
while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to
ensure a stable design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that
cause the greatest oscillation. This represents the worst
case load conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in
step 3 and vary the input voltage until the oscillations
increase. This point represents the worst case input voltage conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If
the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger
standard capacitor value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Remove the unit from the environmental chamber
and heat the IC with a heat gun. Vary the load current as
instructed in step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for
the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic
capacitors have a tolerance of ± 20% so the minimum
value found should be increased by at least 50% to allow
for this tolerance plus the variation which will occur at
low temperatures. The ESR of the capacitor should be less
than 50% of the maximum allowable ESR found in step 3
above.
Stability Considerations
CS8120
C
1
0.1mF
V
IN
Gnd
RESET
CS–8120
V
OUT
ENABLE
500kW
Q
1
500kW
100kW
100kW
C
RST
R
RST
C
2
22mF
V
CC
I/O Port
mP
SWITCH
V
BAT
RESET
Figure 5: Microprocessor Control of CS8120 using an external switching transistor (Q1).
Page 7
7
The maximum power dissipation for a single output regulator (Figure 7) is:
P
D(max)
={V
IN(max)
Ð V
OUT(min)
}
I
OUT(max)
+ V
IN(max)IQ
(1)
where:
V
IN(max)
is the maximum input voltage,
V
OUT(min)
is the minimum output voltage,
I
OUT(max)
is the maximum output current for the applica-
tion, and
IQis the quiescent current the regulator consumes at
I
OUT(max)
.
Once the value of P
D(max)
is known, the maximum permis-
sible value of R
QJA
can be calculated:
R
QJA
=
(2)
The value of R
QJA
can then be compared with those in
the package section of the data sheet. Those packages
with R
QJA
's less than the calculated value in equation 2
will keep the die temperature below 150¡C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed
to determine the value of R
QJA
:
R
QJA
= R
QJC
+ R
QCS
+ R
QSA
(3)
where:
R
QJC
= the junctionÐtoÐcase thermal resistance,
R
QCS
= the caseÐtoÐheatsink thermal resistance, and
R
QSA
= the heatsinkÐtoÐambient thermal resistance.
R
QJC
appears in the package section of the data sheet. Like
R
QJA
, it too is a function of package type. R
QCS
and R
QSA
are functions of the package type, heatsink and the interface between them. These values appear in heat sink data
sheets of heat sink manufacturers.
150¡C - T
A
P
D
Calculating Power Dissipation
in a Single Output Linear Regulator
Application Notes: continued
Heat Sinks
Figure 7. Single output regulator with key performance parameters
labeled.
CS8120
V
Figure 6. Circuit showing output compensation capacitor.
*C1is required if regulator is far from power source filter.
**C
2
is required for stability.
IN
C1*
0.1mF
V
OUT
CS-8120
R
RST
C2**
10mF
5V to mP and
System
Power
ENABLE
I
V
IN
IN
Smart
Regulator
I
OUT
V
OUT
RESET
to mP
RESET
Port
C
RST
Control
Features
}
I
Q
Page 8
Part Number Description
CS8120YT5 5 Lead TO-220 Straight
CS8120YTVA5 5 Lead TO-220 Vertical
CS8120YTHA5 5 Lead TO-220 Horizontal
CS8120YN8 8 Lead PDIP
CS8120YDP5 5 Lead D2PAK
CS8120YDPR5 5 Lead D
2
PAK
(tape & reel)
CS8120YD14 14 Lead SOIC Narrow
CS8120YDR14 14 Lead SOIC Narrow
(tape & reel)
D
Lead Count Metric English
8
Ordering Information
Rev. 2/3/98
CS8120
Package Specification
PACKAGE THERMAL DATA
PACKAGE DIMENSIONS IN mm (INCHES)
Max Min Max Min
14 Lead SOIC Narrow 8.75 8.55 .344 .337
8 Lead PDIP 10.16 9.02 .400 .355
© 1999 Cherry Semiconductor Corporation
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
Thermal Data 5 Lead 5 Lead 8 Lead 14 Lead SOIC
TO-220 D2Pak PDIP Narrow
R
QJC
typ 3.1 3.1 52 30 ûC/W
R
QJA
typ 50 10-50* 100 125 ûC/W
*Depending on thermal properties of substrate. R
Q
JA = RQJC +
R
Q
CA
Plastic DIP (N); 300 mil wide
0.39 (.015)
MIN.
2.54 (.100) BSC
1.77 (.070)
1.14 (.045)
D
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.
.203 (.008)
.356 (.014)
REF: JEDEC MS-001
3.68 (.145)
2.92 (.115)
8.26 (.325)
7.62 (.300)
7.11 (.280)
6.10 (.240)
.356 (.014)
.558 (.022)
5 Lead TO-220 (T) Straight
2.87 (.113)
2.62 (.103)
6.93(.273)
6.68(.263)
9.78 (.385)
10.54 (.415)
1.02(.040)
0.63(.025)
1.83(.072)
1.57(.062)
0.56 (.022)
0.36 (.014)
2.92 (.115)
2.29 (.090)
1.40 (.055)
1.14 (.045)
4.83 (.190)
4.06 (.160)
6.55 (.258)
5.94 (.234)
14.22 (.560)
13.72 (.540)
1.02 (.040)
0.76 (.030)
3.71 (.146)
3.96 (.156)
14.99 (.590)
14.22 (.560)
5 Lead D2PAK (DP)
1.70 (.067) REF
0.10 (.004)
0.00 (.000)
10.31 (.406)
10.05 (.396)
0.91 (.036)
0.66 (.026)
1.40 (.055)
1.14 (.045)
4.57 (.180)
4.31 (.170)
1.68 (.066)
1.40 (.055)
2.74(.108)
2.49(.098)
.254 (.010) REF
2.79 (.110)
2.29 (.090)
15.75 (.620)
14.73 (.580)
8.53 (.336)
8.28 (.326)
Surface Mount Narrow Body (D); 150 mil wide
1.27 (.050) BSC
0.51 (.020)
0.33 (.013)
6.20 (.244)
5.80 (.228)
4.00 (.157)
3.80 (.150)
1.57 (.062)
1.37 (.054)
D
0.25 (0.10)
0.10 (.004)
1.75 (.069) MAX
1.27 (.050)
0.40 (.016)
REF: JEDEC MS-012
0.25 (.010)
0.19 (.008)
Loading...