Datasheet CS8101YTVA5, CS8101YTHA5, CS8101YT5, CS8101YDWFR20, CS8101YDWF20 Datasheet (Cherry Semiconductor)
...Page 1
The CS8101 is a precision 5V
micropower voltage regulator with
very low quiescent current (70µA
typ at 100µA load). The 5V output is
accurate within ±2% and supplies
100mA of load current with a typical dropout voltage of only 400mV.
Microprocessor control logic
includes an input and an
active . This combination of
low quiescent current, outstanding
regulator performance and control
logic makes the CS8101 ideal for
any battery operated, microprocessor controlled equipment.
The active circuit includes
hysteresis, and operates correctly at
an output voltage as low as 1V. The
function is activated during
the power up sequence or during
normal operation if the output
voltage drops outside the regulation
limits by more than 200mV typ. The
logic level compatible
input allows the user to put the regulator into a shutdown mode where
it draws only 20µA typical of quiescent current.
The regulator is protected against
reverse battery, short circuit, over
voltage, and thermal overload conditions. The device can withstand
load dump transients making it
suitable for use in automotive environments.
The CS8101 is functionally equivalent to the National Semiconductor
LP2951 series low current regulators.
ENABLE
RESET
RESET
RESET
ENABLE
1
Features
■ 5V ±2% Output
■ Low 70µA Quiescent
Current
■ Active
■ Input for
ON/OFF and Active/Sleep
Mode Control
■ 100mA Output Current
Capability
■ Fault Protection
+60V Peak Transient
Voltage
-15V Reverse Voltage
Short Circuit
Thermal Overload
■ Low Reverse Current
(Output to Input)
ENABLE
RESET
Package Options
CS8101
Micropower 5V, 100mA Low Dropout
Linear Regulator with RESET and ENABLE
CS8101
Description
Block Diagram
1
V
OUT
V
OUT
Sense
ENABLE
Gnd
V
IN
NC
NC
RESET
5L TO-220
Tab (Gnd)
1. V
OUT
2.
3. Gnd
4.
5. V
IN
RESET
ENABLE
Other Packages: D2PAK (consult factory)
8L SOIC
V
OUT
V
IN
NC
NC
RESET
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
ENABLE
NC
NC
NC
NC
NC
NC
NC
20L SOIC Wide
(Internally Fused Leads)
Rev. 4/9/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
A Company
¨
V
ENABLE
IN
Current Source
(Circuit Bias)
Shutdown
Over
Voltage
Current Limit
Sense
V
OUT
Internally connected
on 5 lead TO-220
V
Sense
OUT
1
RESET
+ -
Error
Thermal
Protection
Amplifier
Bandgap
Reference
+
-
Reset
Comparator
Gnd
Page 2
2
Power Dissipation.............................................................................................................................................Internally Limited
Transient Peak Voltage (46V Load Dump) ..................................................................................................................-15V, 60V
Output Current .................................................................................................................................................Internally Limited
ESD Susceptibility (Human Body Model) ..............................................................................................................................2kV
Operating Temperature..........................................................................................................................................-40¡C to 125¡C
Junction Temperature .............................................................................................................................................-40¡C to 150¡C
Storage Temperature ................................................................................................................................................-55C to 150¡C
Lead Temperature Soldering Wave Solder (through hole styles only) ..........................................10 sec. max, 260¡C peak
Reflow (SMD styles only) ..........................................60 sec. max above 183¡C, 230¡C peak
Electrical Characteristics: 6V ² V
IN
² 26V, I
OUT
= 1mA, -40 ² TA² 125, -40 ² TJ² 150¡C unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CS8101
Absolute Maximum Ratings
■ Output Stage
Output Voltage, V
OUT
9V < VIN< 16V, 100µA ² I
OUT
² 100mA 4.90 5.00 5.10 V
6V ² VIN² 26V, 100µA ² I
OUT
² 100mA 4.85 5.00 5.15 V
Dropout Voltage (VIN-V
OUT
)I
OUT
= 100mA 400 600 mV
I
OUT
= 100µA 100 150 mV
Load Regulation VIN= 14V, 100µA ² I
OUT
² 100mA 5 50 mV
Line Regulation 6V < V < 26V, I
OUT
= 1mA 5 50 mV
Quiescent Current, (IQ)
Active Mode I
OUT
= 100µA, VIN= 6V 70 140 µA
I
OUT
= 50mA 4 6 mA
I
OUT
² 100mA 12 20 mA
Sleep Mode V
OUT
= OFF, VIN= 6V, V = 2V 20 50 µA
Ripple Rejection 7 ² VIN² 17V, I
OUT
= 100mA, f = 120Hz 60 75 dB
Current Limit 105 200 mA
Short Circuit Output Current V
OUT
= 0V 25 125 mA
Thermal Shutdown 150 180 ¡C
Overvoltage Shutdown V
OUT
²1V 303438V
Reverse Current V
OUT
= 5V, VIN= 0V 100 200 µA
■ Enable Input ( )
Threshold
HIGH (V
OUT
OFF) 1.4 2.0 V
LOW (V
OUT
ON) 0.6 1.4 V
Input Current V = 2.4V 30 100 µA
■ Reset Function ( )
Threshold
HIGH (VRH)V
OUT
Increasing 4.525 4.75 V
OUT
- 0.05 V
LOW (VRL)V
OUT
Decreasing 4.500 4.700 V
OUT
- 0.075 V
Hysteresis (HIGH - LOW) 25 50 100 mV
Reset Output Leakage V
OUT³VRH
25 µA
= HIGH
Output Voltage
Low (V
RLO
) 1V ² V
OUT²VRL
0.1 0.4 V
R = 10K
Low (VRpeak) V
OUT
, Power up, Power down 0.6 1.0 V
RESET
RESET
RESET
RESET
RESET
ENABLE
ENABLE
ENABLE
Page 3
Output Stage Protection
The output stage is protected against overvoltage, short
circuit and thermal runaway conditions (Figure 1).
Figure 1. Typical Circuit Waveforms for Output Stage Protection.
If the input voltage rises above 30V (e.g. load dump), the output shuts down. This response protects the internal circuitry
and enables the IC to survive unexpected voltage transients.
Should the junction temperature of the power device exceed
180ûC (typ) the load current capability is reduced thereby
preventing thermal overload. This thermal management
function is an effective means to prevent die overheating
since the load current is the principle heat source in the IC.
The CS8101 contains two microprocessor compatible control functions: and (Figure 2).
Figure 2. Circuit Waveform
Function
The function switches the output transistor ON
and OFF. When the voltage on the lead exceeds
1.4V typ, the output pass transistor turns off, leaving a
high impedance facing the load. The IC will remain in
Sleep mode, drawing only 50µA, until the voltage on this
input drops below the threshold.
Function
A signal (low voltage) is generated as the IC powers up until V
OUT
is within 250mV of the regulated output
voltage, or when V
OUT
drops out of regulation,and is
lower than 300mV below the regulated output voltage. A
hysteresis of 50mV is included in the function to minimize
oscillations.
The output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC thereby
guaranteeing that the signal is valid for V
OUT
as low
as 1V.
RESET
RESET
RESET
RESET
ENABLE
ENABLE
ENABLE
ENABLE
RESETENABLE
Regulator Control Functions
Voltage Reference and Output Circuitry
3
CS8101
Package Lead Description
PACKAGE LEAD # LEAD SYMBOL FUNCTION
Circuit Description
8 Lead 20 Lead SOIC 5 Lead
SOIC (Internally Fused Leads) TO-220
819 5VINInput voltage.
120 1V
OUT
5V, ±2%, 100mA output.
3 1 2 Logic level switches output off when toggled HIGH.
4 4,5,6,7 3 Gnd Ground. All Gnd leads must be connected to Ground.
14,15,16,17
5 10 4 Active reset (accurate to V
OUT
³ 1V).
2V
OUT
Sense Kelvin connection which allows remote sensing of out-
put voltage for improved regulation. If remote sensing
is not required, connect to V
OUT
.
6,7 2,3,8,9,11,12,13,18 NC No Connection.
RESET
ENABLE
> 30V
V
IN
V
OUT
I
OUT
Load
Dump
Current
Limit
Short
Circuit
FOR 7V < V
V
IN
ENABLE
V
IN
H
V
RH
V
V
OUT
RESET
RL
VR
(1)
PEAK
VR
LO
(1) = NO RESET DELAY CAPACITOR
(2) = WITH RESET DELAY CAPACITOR
IN
(2)
< 26V
VR
PEAK
Page 4
Figure 3. RC Network for Delay
An external RC network on the lead (Figure 3) provides a sufficiently long delay for most microprocessor
based applications. RC values can be chosen using the
following formula:
Ðt
Delay
R
TOTCRST
=
[
ln
]
where: R
RST
= Delay resistor
R
IN
= µP port impedance
R
TOT
= R
RST
in parallel with R
IN
C
RST
= Delay capacitor
t
Delay
= desired delay time
V
RST
= V
SAT
of lead (0.7V @ turn - ON)
VT= threshold
RESET
RESET
RESET
RESET
)
VTÐ V
OUT
V
RST
Ð V
OUT
(
RESET
RESET
The circuit depicted in Figure 4 lets the microprocessor
control its power source, the CS8101 regulator. An I/O
port on the µP and the SWITCH port are used to drive the
base of Q1. When Q1 is driven into saturation, the voltage
on the lead falls below its lower threshold. The
regulatorÕs output is
enabled
. When the drive current is
removed, the voltage on the lead rises, the output is switched off and the IC moves into Sleep mode
where it draws 50µA (max).
By coupling these two controls with the lead, the
system has added flexibility. Once the system is running,
the state of the SWITCH is irrelevant as long as the I/O
port continues to drive Q1. The microprocessor can turn
off its own power by withdrawing drive current, once the
SWITCH is open. This software control at the I/O port
allows the microprocessor to finish key housekeeping
functions before power is removed.
The logic options are summarized in Table 1.
ENABLE
ENABLE
ENABLE
4
CS8101
Applications Notes
Circuit Description: continued
Figure 4. Microprocessor Control of CS8101 using external switching transistor Q1.
CS8101
V
RESET
OUT
R
RST
C
RST
5V to mP
and
System
Power
C
OUT
to mP
RESET
Port
V
BAT
0.1mF
500kW
V
IN
CS8101
V
OUT
R
RST
V
CC
C
OUT
mP
ENABLE
Q
1
500kW 100kW
SWITCH
Gnd
RESET
RESET
C
RST
100kW
I/O Port
Page 5
The I/O port of the microprocessor typically provides
50µA to Q1. In automotive applications the SWITCH is
connected to the ignition switch.
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start-up
delay, load transient response and loop stability.
Figure 5. Test and application circuit showing output compensation.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum
or aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25¡C to -40¡C), both the value and ESR of the
capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information.
The value for the output capacitor C
OUT
shown in Figure 5
should work for most applications, however it is not necessarily the optimized solution.
To determine an acceptable value for C
OUT
for a particular
application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part.
Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade
box outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load
while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to
ensure a stable design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that
cause the greatest oscillation. This represents the worst
case load conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger standard capacitor value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Remove the unit from the environmental chamber
and heat the IC with a heat gun. Vary the load current as
instructed in step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for
the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic
capacitors have a tolerance of ±20% so the minimum value
found should be increased by at least 50% to allow for this
tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than
50% of the maximum allowable ESR found in step 3 above.
The maximum power dissipation for a single output regulator (Figure 6) is:
P
D(max)
= {V
IN(max)
- V
OUT(min)
}
I
OUT(max)
+ V
IN(max)IQ
(1)
where:
V
IN(max)
is the maximum input voltage,
V
OUT(min)
is the minimum output voltage,
I
OUT(max)
is the maximum output current for the applica-
tion, and
IQis the quiescent current the regulator consumes at
I
OUT(max)
.
Once the value of P
D(max)
is known, the maximum permis-
sible value of R
QJA
can be calculated:
R
QJA
=
(2)
The value of R
QJA
can then be compared with those in
the package section of the data sheet. Those packages with
R
QJA
's less than the calculated value in equation 2 will keep
the die temperature below 150¡C.
150¡C - T
A
P
D
Calculating Power Dissipation
in a Single Output Linear Regulator
Stability Considerations
Table 1. Logic Control of CS8101 Output
Microprocessor
I/O drive Switch ENABLE Output
ON Closed LOW ON
Open LOW ON
OFF Closed LOW ON
Open HIGH OFF
5
CS8101
Application Notes: continued
V
IN
CIN*
0.1mF
*CIN required if regulator is located far from the power supply filter.
** C
required for stability. Capacitor must operate at minimum
OUT
temperature expected.
CS8101
ENABLE
V
RESET
OUT
R
RST
C
OUT
10mF
**
Page 6
Application Notes: continued
6
CS8101
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
Figure 6: Single output regulator with key performance parameters
labeled.
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed
to determine the value of R
QJA
:
R
QJA
= R
QJC
+ R
QCS
+ R
QSA
(3)
where:
R
QJC
= the junctionÐtoÐcase thermal resistance,
R
QCS
= the caseÐtoÐheatsink thermal resistance, and
R
QSA
= the heatsinkÐtoÐambient thermal resistance.
R
QJC
appears in the package section of the data sheet. Like
R
QJA
, it too is a function of package type. R
QCS
and R
QSA
are functions of the package type, heatsink and the interface between them. These values appear in heatsink data
sheets of heatsink manufacturers.
Heatsinks
I
V
IN
IN
Regulator
Control
Features
}
Smart
I
Q
I
OUT
V
OUT
Page 7
CS8101
7
8 Lead 20 Lead 5 Lead
Thermal Data SOIC SOIC Wide TO-220
R
QJC
typ 45 9 3.3 ûC/W
R
QJA
typ 165 55 50 ûC/W
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES)
PACKAGE THERMAL DATA
D
Lead Count Metric English
Max Min Max Min
8L SOIC 5.00 4.80 .197 .189
20L SOIC 13.00 12.60 .512 .496
1.27 (.050) BSC
0.51 (.020)
0.33 (.013)
6.20 (.244)
5.80 (.228)
4.00 (.157)
3.80 (.150)
1.57 (.062)
1.37 (.054)
D
0.25 (0.10)
0.10 (.004)
1.75 (.069) MAX
1.27 (.050)
0.40 (.016)
REF: JEDEC MS-012
0.25 (.010)
0.19 (.008)
Surface Mount Narrow Body (D); 150 mil wide
1.27 (.050) BSC
7.60 (.299)
7.40 (.291)
10.65 (.419)
10.00 (.394)
D
0.32 (.013)
0.23 (.009)
1.27 (.050)
0.40 (.016)
REF: JEDEC MS-013
2.49 (.098)
2.24 (.088)
0.51 (.020)
0.33 (.013)
2.65 (.104)
2.35 (.093)
0.30 (.012)
0.10 (.004)
Surface Mount Wide Body (DW); 300 mil wide
Page 8
CS8101
8
Rev. 4/9/99
Part Number Description
CS8101YD8 8L SOIC
CS8101YDR8 8L SOIC (tape & reel)
CS8101YDWF20 20L SOIC (internally fused leads)
CS8101YDWFR20 20L SOIC (internally fused leads)
(tape & reel)
CS8101YT5 5L TO-220
CS8101YTVA5 5L TO-220 Vertical
CS8101YTHA5 5L TO-220 Horizontal
Ordering Information
© 1999 Cherry Semiconductor Corporation
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
Package Specification
5 Lead TO-220 (T) Straight
2.87 (.113)
2.62 (.103)
6.93(.273)
6.68(.263)
9.78 (.385)
10.54 (.415)
1.02(.040)
0.63(.025)
1.83(.072)
1.57(.062)
0.56 (.022)
0.36 (.014)
2.92 (.115)
2.29 (.090)
1.40 (.055)
1.14 (.045)
4.83 (.190)
4.06 (.160)
6.55 (.258)
5.94 (.234)
14.22 (.560)
13.72 (.540)
1.02 (.040)
0.76 (.030)
3.71 (.146)
3.96 (.156)
14.99 (.590)
14.22 (.560)
5 Lead TO-220 (THA) Horizontal
0.81(.032)
1.70 (.067)
6.81(.268)
1.40 (.055)
1.14 (.045)
5.84 (.230)
6.60 (.260)
6.83 (.269)
0.56 (.022)
0.36 (.014)
10.54 (.415)
9.78 (.385)
6.55 (.258)
5.94 (.234)
3.96 (.156)
3.71 (.146)
1.68
(.066)
TYP
14.99 (.590)
14.22 (.560)
2.77 (.109)
2.29 (.090)
2.92 (.115)
4.83 (.190)
4.06 (.160)
2.87 (.113)
2.62 (.103)
5 Lead TO-220 (TVA) Vertical
1.68
(.066) typ
1.70 (.067)
7.51 (.296)
1.78 (.070)
4.34 (.171)
0.56 (.022)
0.36 (.014)
1.40 (.055)
1.14 (.045)
4.83 (.190)
4.06 (.160)
14.99 (.590)
14.22 (.560)
2.92 (.115)
2.29 (.090)
.94 (.037)
.69 (.027)
8.64 (.340)
7.87 (.310)
6.80 (.268)
10.54 (.415)
9.78 (.385)
2.87 (.113)
2.62 (.103)
6.55 (.258)
5.94 (.234)
3.96 (.156)
3.71 (.146)
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