Datasheet CS52845EDR8, CS52845EDR14, CS52845ED8, CS52845ED14 Datasheet (Cherry Semiconductor)

The CS52845 provides all the nec­essary features to implement off­line fixed frequency current-mode
control with a minimum number
of external components.

The CS52845 incorporates a new
precision temperature-controlled
oscillator to minimize variations in
frequency. An internal toggle flip­flop, which blanks the output
every other clock cycle, limits the
duty-cycle range to less than 50%.

An undervoltage lockout ensures
that V

REF

is stabilized before the
output stage is enabled. In the
CS52845 turn on is at 8.4V and
turn off at 7.6V.

Other features include low start-up
current, pulse-by-pulse current lim­iting, and a high-current totem pole
output for driving capacitive loads,
such as gate of a power MOSFET.
The output is low in the off state,
consistent with N-channel devices.

1

Features

■

Optimized for Off-line
Control

■

Temperature
Compensated Oscillator

■

50% Maximum Duty-cycle
Clamp

■ V

REF

Stabilized before

Output Stage is Enabled

■ Low Start-up Current

■ Pulse-by-pulse Current

Limiting

■ Improved Undervoltage

Lockout

■ Double Pulse Suppression

■ 1% Trimmed Bandgap

Reference

■ High Current Totem Pole

Output

Package Options

CS52845

Current Mode PWM

Control Circuit

with 50% Max Duty Cycle

CS52845

Description

Block Diagram

Absolute Maximum Ratings

Supply Voltage (I

CC

<30mA) ..........................................................Self Limiting

Supply Voltage (Low Impedance Source)...................................................30V

Output Current ...............................................................................................±1A

Output Energy (Capacitive Load) .................................................................5µJ

Analog Inputs (V

FB

, V

SENSE

)...........................................................-0.3V to 5.5V

Error Amp Output Sink Current...............................................................10mA

Lead Temperature Soldering

Reflow (SMD styles only)...........60 sec. max above 183°C, 230°C peak

10

7

14

13

12

8

1

2

3

4

5

6

11

9

COMP

NC

V

FB

NC

Sense

NC

OSC

V

REF

NC
V

CC

VCC Pwr
V

OUT

Pwr Gnd

Gnd

14L SO Narrow

7

8

2

3

4

5

6

COMP

V

FB

Sense

OSC

V

REF

V

CC

V

OUT

Gnd

8L SO Narrow

Rev. 3/4/99

Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: [phone] Fax: [phone]

Email: [e-mail]

Web Site: www.cherry-semi.com

A Company

®

V

Undervoltage Lock-out

V

CC

CC

V

Pwr

CC

1

34V

Gnd

8.4V/7.6V

V

FB

COMP

OSC

Sense

Error

Amplifier

2 R

­+

2.50V

Oscillator

R

1V

Undervoltage

R

R

Current

Sensing

Comparator

Set/

Reset

V

REF

Lockout

Toggle

Flip-Flop

S

R
PWM

Latch

5.0 Volt

Reference

NOR

Internal

Bias

V

REF

V

OUT

Pwr Gnd

2

Electrical Characteristics: -40 ≤ TA ≤ 85˚C; V

CC

= 15V (Note 1); RT = 10kΩ; CT = 3.3nF for sawtooth mode.unless otherwise stated.

CS52845

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

■ Reference Section

Output Voltage TJ=25˚C, I

REF

=1mA 4.95 5.00 5.05 V

Line Regulation 12≤V

CC

≤25V 6 20 mV

Load Regulation 1≤I

REF

≤20mA 6 25 mV

Temperature Stability (Note 2) 0.2 0.4 mV/˚C

Total Output Variation Line, Load, Temp. (Note 2) 4.90 5.10 V

Output Noise Voltage 10Hz≤f≤10kHz, T

J

=25˚C (Note 2) 50 µV

Long Term Stability T

A

=125˚C, 1000 Hrs. (Note 2) 5 25 mV

Output Short Circuit TA=25˚C -30 -100 -180 mA

■ Oscillator Section

Initial Accuracy Sawtooth Mode, T

J

=25˚C475257kHz

Voltage Stability 12≤V

CC

≤25V 0.2 1.0 %

Temperature Stability Sawtooth Mode T

MIN≤TA≤TMAX

(Note 2) 5 %

Amplitude V

OSC

(peak to peak) 1.7 V

■ Error Amp Section

Input Voltage V

COMP

=2.5V 2.45 2.50 2.55 V

Input Bias Current VFB=0V -0.3 -1.0 µA

A

VOL

2≤V

OUT

≤4V 65 90 dB

Unity Gain Bandwidth (Note 2) 0.7 1.0 MHz

PSRR 12≤VCC≤25V 60 70 dB

Output Sink Current VFB=2.7V, V

COMP

=1.1V 2 6 mA

Output Source Current VFB=2.3V, V

COMP

=5V -0.5 -0.8 mA

V

OUT

HIGH VFB=2.3V, RL=15kΩ to Gnd 5 6 V

V

OUT

LOW VFB=2.7V, RL=15kΩ to V

REF

0.7 1.1 V

■ Current Sense Section

Gain (Notes 3 & 4) 2.85 3.00 3.15 V/V

Maximum Input Signal V

COMP

=5V (Note 3) 0.9 1.0 1.1 V

PSRR 12≤V

CC

≤25V (Note 3) 70 dB

Input Bias Current V

Sense

=0V -2 -10 µA

Delay to Output TJ=25˚C (Note 2) 150 300 ns

■ Output Section

Output Low Level I

SINK

=20mA 0.1 0.4 V

I

SINK

=200mA 1.5 2.2 V

Output High Level I

SOURCE

=20mA 13.0 13.5 V

I

SOURCE

=200mA 12.0 13.5 V

Rise Time TJ=25˚C, CL=1nF (Note 2) 50 150 ns

Fall Time TJ=25˚C, CL=1nF (Note 2) 50 150 ns

3

Package Pin Description

PACKAGE PIN # PIN SYMBOL FUNCTION

Electrical Characteristics: Unless otherwise stated, specifications apply for -40 ≤ TA ≤ 85˚C; V

CC

= 15V (Note 1); RT = 10kΩ;

C

T

= 3.3nF for sawtooth mode.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

■ Total Standby Current

Start-Up Current 0.5 1.0 mA

Operating Supply Current VFB=V

Sense

=0V RT=10kΩ, CT=3.3nF 11 17 mA

VCCZener Voltage ICC=25mA 34 V

■ PWM Section

Maximum Duty Cycle 46 48 50 %

Minimum Duty Cycle 0 %

■ Undervoltage Lockout Section

Start Threshold 7.8 8.4 9.0 V

Min. Operating Voltage After Turn On 7.0 7.6 8.2 V

Notes: 1. Adjust VCCabove the start threshold before setting at 15V. 3. Parameter measured at trip point of latch with VFB=0.

2.These parameters, although guaranteed, are not 100% tested in production. 4. Gain defined as:
A = ; 0 ≤ V

Sense

≤ 0.8V.

∆V

COMP

∆V

Sense

8L 14L

SO Narrow SO Narrow

1 1 COMP Error amp output, used to compensate error amplifier.

23 VFBError amp inverting input.

3 5 Sense Noninverting input to Current Sense Comparator.

4 7 OSC Oscillator timing network with Capacitor to Ground, resistor to V

REF

.

5 9 Gnd Ground.

5 8 Pwr Gnd Output driver Ground.

610V

OUT

Output drive pin.

711V

CC

Pwr Output driver positive supply.

712VCCPositive power supply.

814V

REF

Output of 5V internal reference.

2,4,6,13 NC No Connection.

Undervoltage Lockout

During Undervoltage Lockout (Figure 1), the output driv­er is biased to sink minor amounts of current. The output
should be shunted to ground with a resistor to prevent
activating the power switch with extraneous leakage cur­rents.

PWM Waveform

To generate the PWM waveform, the control voltage from
the error amplifier is compared to a current sense signal
which represents the peak output inductor current (Figure

2). An increase in VCCcauses the inductor current slope to
increase, thus reducing the duty cycle. This is an inherent
feed-forward characteristic of current mode control, since
the control voltage does not have to change during
changes of input supply voltage.

When the power supply sees a sudden large output cur­rent increase, the control voltage will increase allowing
the duty cycle to momentarily increase. Since the duty
cycle tends to exceed the maximum allowed to prevent
transformer saturation in some power supplies, the inter­nal oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of OSC compo­nents.

4

Figure 1: Startup voltage for the CS52845.

Circuit Description

Test Circuit Open Loop Laboratory Test Fixture

V

REF

V

CC

V

OUT

1kΩ
1W

0.1µF

0.1µF

V

REF

V

CC

V

OUT

Gnd

V

FB

Sense

OSC

COMP

5kΩ

100kΩ

4.7kΩ

1kΩ

Error Amp

Adjust

4.7kΩ

Sense

Adjust

R

T

2N2222

C

T

Gnd

A

V

CC

<15mA

I

CC

<1mA

V

= 8.4V

ON

V

OFF

V

ONVOFF

= 7.6V

ON/OFF Command

to reset of IC

V

CC

Setting the Oscillator

The times Tcand Tdcan be determined as follows:

Grounding

High peak currents associated with capacitive loads neces­sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Gnd in a single
point ground.

The transistor and 5kΩ potentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.

5

CS52845

Circuit Description:: continued

Substituting in typical values for the parameters in the
above formulas:

V

REF

= 5.0V, V

upper

= 2.7V, V

lower

= 1.0V, Id= 8.3mA,

then

tc≈ 0.5534RTC

T

td= RTCTln

For better accuracy RTshould be ≥10kΩ.

)

2.3 - 0.0083 R

T

4.0 - 0.0083 R

T

(

V

Figure 2: Timing Diagram

Figure 3: Duty Cycle parameters.

tc= RTCTln

t

d

= RTCTln

)

V

REF

- IdRT- V

lower

V

REF

- IdRT- V

upper

(

)

V

REF

- V

lower

V

REF

- V

upper

(

OSC

OSC

RESET

Toggle

F/F Output

EA Output

Switch

Current

V

CC

I

O

V

O

V

V

upper

lower

ton=t
t

off=tc

t

on

t

t

c

c

+2t

d

t

off

d

6

Rev. 3/4/99

CS52845

D

Lead Count Metric English

Max Min Max Min
8L SO Narrow 5.00 4.80 .197 .189
14L SO Narrow 8.75 8.55 .344 .337

Thermal Data 8L 14L

SO Narrow SO Narrow

R

ΘJC

typ 45 30 ˚C/W

R

ΘJA

typ 165 125 ˚C/W

Package Specification

PACKAGE DIMENSIONS IN mm (INCHES)

PACKAGE THERMAL DATA

Ordering Information

Part Number Description

CS52845ED8 8L SO Narrow
CS52845EDR8 8L SO Narrow (tape & reel)
CS52845ED14 14L SO Narrow
CS52845EDR14 14L SO Narrow (tape & reel)

© 1999 Cherry Semiconductor Corporation

Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.

1.27 (.050) BSC

0.51 (.020)

0.33 (.013)

6.20 (.244)

5.80 (.228)

4.00 (.157)

3.80 (.150)

1.57 (.062)

1.37 (.054)

D

0.25 (0.10)

0.10 (.004)

1.75 (.069) MAX

1.27 (.050)

0.40 (.016)

REF: JEDEC MS-012

0.25 (.010)

0.19 (.008)

Surface Mount Narrow Body (D); 150 mil wide