Datasheet CS52843ED8, CS52843ED14, CS52843EDR8, CS52843EDR14 Datasheet (Cherry Semiconductor)

Page 1
The CS52843 provides all the nec­essary features to implement off­line fixed frequency current-mode control with a minimum number of external components.
The CS52843 incorporates a new precision temperature-controlled oscillator to minimize variations in frequency. An undervoltage lock­out ensures that V
REF
is stabilized
before the output stage is enabled. In the CS52843 turn on is at 8.4V and turn off at 7.6V.
Other features include low start-up current, pulse-by-pulse current lim­iting, and a high-current totem pole output for driving capacitive loads, such as gate of a power MOSFET. The output is low in the off state, consistent with N-channel devices.
1
Features
Optimized for Off-line Control
Internally
Temperature
Compensated Oscillator
V
REF
Stabilized before
Output Stage is Enabled
Very Low Start-up Current
300 µA (typ)
Pulse-by-pulse Current
Limiting
Improved Undervoltage
Lockout
Double Pulse Suppression
2% 5 Volt Reference
High Current Totem Pole
Output
Package Options
CS52843
Current Mode PWM
Control Circuit
CS52843
Description
Block Diagram
Absolute Maximum Ratings
Supply Voltage (I
CC
<30mA) ..........................................................Self Limiting
Supply Voltage (Low Impedance Source)...................................................30V
Output Current ...............................................................................................±1A
Output Energy (Capacitive Load) .................................................................5µJ
Analog Inputs (V
FB
, V
SENSE
)...........................................................-0.3V to 5.5V
Error Amp Output Sink Current...............................................................10mA
Lead Temperature Soldering
Reflow (SMD styles only)...........60 sec. max above 183°C, 230°C peak
7
8
2
3
4
5
6
COMP
V
FB
Sense
OSC
V
REF
V
CC
V
OUT
Gnd
8L SO Narrow
A Company
®
10
7
14
13
12
8
1
2
3
4
5
6
11
9
COMP
NC
V
FB
NC
Sense
NC
OSC
V
REF
NC V
CC
VCC Pwr V
OUT
Pwr Gnd Gnd
14L SO Narrow
Rev. 12/23/97
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
V
CC
34V
Gnd
V
FB
COMP
OSC
Sense
Undervoltage Lock-out
V
CC
8.4V/7.6V
Error
Amplifier
2 R
Oscillator
R
­+
R
2.50V
1V
Current
Sensing
Comparator
5.0 Volt
Set/
Reference
Reset
OUTPUT ENABLE
R
NOR
S
R PWM
Latch
Internal
Bias
V
Pwr
CC
V
REF
V
OUT
Pwr Gnd
1
Page 2
2
Electrical Characteristics: -40 ≤ TA ≤ 85˚C; V
CC
= 15V (Note 1); RT = 680; CT = .022µF for triangle mode,
R
T
= 10k; CT = 3.3nF sawtooth mode unless otherwise stated.
CS52843
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference Section
Output Voltage TJ = 25˚C, I
REF
= 1mA 4.90 5.00 5.10 V
Line Regulation 12 ≤ V
CC
25V 6 20 mV
Load Regulation 1 ≤ I
RE F
20mA 6 25 mV
Temperature Stability (Note 1) 0.2 0.4 mV/˚C
Total Output Variation Line, Load, Temp. (Note 1) 4.82 5.18 V
Output Noise Voltage 10Hz f 10kHz, T
J
= 25˚C (Note 1) 50 µV
Long Term Stability TA = 125˚C, 1000 Hrs. (Note 1) 5 25 mV
Output Short Circuit T
A
= 25˚C -30 -100 -180 mA
Oscillator Section
Initial Accuracy Sawtooth Mode, T
J
= 25˚C (Note 1) 47 52 57 kHz
Triangle Mode, T
J
= 25˚C 44 52 60 kHz
Voltage Stability 12 ≤ V
CC
25V 0.2 1.0 %
Temperature Stability Sawtooth Mode T
MIN
TA ≤ T
MAX
5%
Triangle Mode T
MIN
TA ≤ T
MAX
(Note 1) 8 %
Amplitude V
OSC
(peak to peak) 1.7 V
Discharge Current T
J
= 25˚C 7.3 8.3 9.3 mA
T
MIN
TA ≤ T
MAX
6.8 9.8 mA
Error Amp Section
Input Voltage V
COMP
= 2.5V 2.42 2.50 2.58 V
Input Bias Current V
FB
= 0V -0.3 -2.0 µA
A
VOL
2 V
OUT
4V 65 90 dB
Unity Gain Bandwidth (Note 1) 0.7 1.0 MHz
PSRR 12 ≤ V
CC
25V 60 70 dB
Output Sink Current V
FB
= 2.7V, V
COMP
= 1.1V 2 6 mA
Output Source Current V
FB
= 2.3V, V
COMP
= 5V -0.5 -0.8 mA
V
OUT
HIGH V
FB
= 2.3V, RL = 15kto Gnd 5 6 V
V
OUT
LOW V
FB
= 2.7V, RL = 15kto V
REF
0.7 1.1 V
Current Sense Section
Gain (Notes 2 & 3) 2.85 3.00 3.15 V/V
Maximum Input Signal V
COMP
= 5V (Note 2) 0.9 1.0 1.1 V
PSRR 12 ≤ V
CC
25V (Note 2) 70 dB
Input Bias Current V
Sense
=0V -2 -10 µA
Delay to Output TJ=25˚C (Note 1) 150 300 ns
Output Section
Output Low Level I
SINK
= 20mA 0.1 0.4 V
I
SINK
= 200mA 1.5 2.2 V
Output High Level I
SOURCE
= 20mA 13.0 13.5 V
I
SOURCE
= 200mA 12.0 13.5 V
Page 3
3
CS52843
Package Pin Description
PACKAGE PIN # PIN SYMBOL FUNCTION
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
8L 14L
SO Narrow SO Narrow
1 1 COMP Error amp output, used to compensate error amplifier.
23 V
FB
Error amp inverting input.
3 5 Sense Noninverting input to Current Sense Comparator.
4 7 OSC Oscillator timing network with Capacitor to Ground, resistor to V
REF
.
5 8 Gnd Ground.
5 9 Pwr Gnd Output driver Ground.
610V
OUT
Output drive pin.
711V
CC
Pwr Output driver positive supply.
712V
CC
Positive power supply.
814V
REF
Output of 5V internal reference.
2,4,6,13 NC No Connection.
Electrical Characteristics: -40 ≤ TA ≤ 85˚C; V
CC
= 15V (Note 1); RT = 680; CT = .022µF for triangle mode,
R
T
= 10k; CT = 3.3nF sawtooth mode unless otherwise stated.
Rise Time TJ = 25˚C, CL = 1nF (Note 1) 50 150 ns
Fall Time TJ=25˚C, CL=1nF (Note 1) 50 150 ns
Output Leakage UVLO Active V
OUT
= 0 -.01 -10.0 µA
Total Standby Current
Start-Up Current 300 500 µA
Operating Supply Current VFB=V
Sense
=0V RT=10kΩ, CT=3.3nF 11 17 mA
VCCZener Voltage ICC=25mA 34 V
Undervoltage Lockout Section
Start Threshold 7.8 8.4 9.0 V
Min. Operating Voltage After Turn On 7.0 7.6 8.2 V
Notes: 1.These parameters, although guaranteed, are not 100% tested in production.
2. Parameter measured at trip point of latch with VFB=0.
3. Gain defined as: A = ; 0 V
Sense
0.8V.
V
COMP
V
Sense
Page 4
Figure 1: Startup voltage for the CS52843.
Undervoltage Lockout
During Undervoltage Lockout (Figure 1), the output driv­er is biased to sink minor amounts of current. The output should be shunted to ground with a resistor to prevent activating the power switch with extraneous leakage cur­rents.
PWM Waveform
To generate the PWM waveform, the control voltage from the error amplifier is compared to a current sense signal which represents the peak output inductor current (Figure
2). An increase in V
CC
causes the inductor current slope to increase, thus reducing the duty cycle. This is an inherent feed-forward characteristic of current mode control, since the control voltage does not have to change during changes of input supply voltage.
4
CS52843
Test Circuit Open Loop Laboratory Test Fixture
V
REF
V
CC
V
OUT
1k 1W
0.1µF
0.1µF
V
REF
V
CC
V
OUT
Gnd
V
FB
Sense
OSC
COMP
5k
100k
4.7k
1k
Error Amp
Adjust
4.7k
Sense Adjust
R
T
2N2222
C
T
Gnd
A
Typical Performance Characteristics
FREQ. (kHz)
Oscillator Frequency vs C
T
Oscillator Duty Cycle vs R
T
Circuit Description
900 800
700
600
500
400
300
200
100
.0005 .001 .002 .003 .005 .01 .02 .03 .04
RT =1.5k
R
=680
T
RT =10k
CT (µF)
100
90 80
70 60 50 40
DUTY CYCLE (%)
30 20 10
.05
100 200 700 1k 2k 5k 7k 10k
RT ()
4k3k500400300
V
CC
V
ON
V
OFF
I
CC
<15mA
<500µA
ON/OFF Command
to reset of IC
=8.4V
= 7.6V
V
V
ONVOFF
CC
Page 5
When the power supply sees a sudden large output cur­rent increase, the control voltage will increase allowing the duty cycle to momentarily increase. Since the duty cycle tends to exceed the maximum allowed to prevent trans­former saturation in some power supplies, the internal oscillator waveform provides the maximum duty cycle clamp as programmed by the selection of oscillator timing components.
Figure 2: Timing Diagram
Figure 3: Oscillator Timing Network and Parameters
Setting the Oscillator
The times T
c
and Tdcan be determined as follows:
t
c
= RTCTln
t
d
= RTCTln
Substituting in typical values for the parameters in the above formulas:
V
REF
= 5.0V, V
UPPER
= 2.7V, V
LOWER
= 1.0V, Id= 8.3mA,
then
t
c
0.5534RTC
T
td= RTCTln
For better accuracy RTshould be 10kΩ.
Grounding
High peak currents associated with capacitive loads neces­sitate careful grounding techniques. Timing and bypass capacitors should be connected close to Gnd in a single point ground.
The transistor and 5kpotentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Sense.
)
2.3 - 0.0083 R
T
4.0 - 0.0083 R
T
(
)
V
REF
- IdRT- V
LOWER
V
REF
- IdRT- V
UPPER
(
)
V
REF
- V
LOWER
V
REF
- V
UPPER
(
V
5
CS52843
Circuit Description
Triangular Mode
Sawtooth Mode
OSC
OSC
RESET
Toggle
F/F Output
EA Output
Switch
Current
V
CC
I
O
V
O
V
V
LARGE R
SMALL R
upper
lower
V
REF
OSC
Gnd
(10k)
T
(700k)
T
t
c
R
T
C
T
t
d
V
OSC
Internal Clock
V
REF
Internal Clock
Page 6
6
Part Number Description
CS52843ED8 8L SO Narrow CS52843EDR8 8L SO Narrow (tape & reel) CS52843ED14 14L SO Narrow CS52843EDR14 14L SO Narrow (tape & reel)
Rev. 12/23/97
CS52843
D
Lead Count Metric English
Max Min Max Min
8L SO Narrow 5.00 4.80 .197 .189
14L SO Narrow 8.75 8.55 .344 .337
Thermal Data 8L SO Narrow 14L SO Narrow
R
ΘJC
typ 45 30 ˚C/W
R
ΘJA
typ 165 125 ˚C/W
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES)
PACKAGE THERMAL DATA
Ordering Information
© 1999 Cherry Semiconductor Corporation
Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information.
Surface Mount Narrow Body (D); 150 mil wide
1.27 (.050) BSC
0.51 (.020)
0.33 (.013)
6.20 (.244)
5.80 (.228)
4.00 (.157)
3.80 (.150)
1.57 (.062)
1.37 (.054)
D
0.25 (0.10)
0.10 (.004)
1.75 (.069) MAX
1.27 (.050)
0.40 (.016)
REF: JEDEC MS-012
0.25 (.010)
0.19 (.008)
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