Datasheet CS5166H Datasheet (CHERRY Semiconductor)

Features

■

V

2

TM

Control Topology

■

Dual N-Channel Design

■

125ns Controller Transient Response

■

Excess of 1Mhz Operation

■

5-bit DAC with 1% Tolerance

■

Power-Good Output with Internal

Delay

■

Adjustable Hiccup Mode Over

Current Protection

■

Complete Pentium

®

II System

Requires just 21 Components

■

5V and 12V Operation using either

Dual or Single Supplies

■

Adaptive Voltage Positioning

■

Remote Sense Capability

■

Current Sharing Capability

■

V

CC

Monitor

■

Overvoltage Protection (OVP)

■

Programmable Soft Start

■

200ns PWM Blanking

■

65ns FET Non-Overlap

■

40ns Gate Rise and Fall Times

(3.3nF load)

Package Options

CS5166H

5-Bit Synchronous CPU Controller

with Power-Good and Current Limit

CS5166H

Description

The CS5166H is a synchronous
dual NFET Buck Regulator
Controller. It is designed to pow­er the core logic of the latest high
performance CPUs. It uses the
V

2

TM

control method to achieve
the fastest possible transient
response and best overall regula­tion. It incorporates many addi­tional features required to ensure
the proper operation and protec­tion of the CPU and power sys­tem. The CS5166H provides the
industry’s most highly integrat­ed solution, minimizing external
component count, total solution
size, and cost.

The CS5166H is specifically
designed to power Intel’s
Pentium

®

II processor and
includes the following features:
5-bit DAC with 1% tolerance,
Power-Good output, adjustable
hiccup mode over-current pro­tection, V

CC

monitor, Soft Start,
adaptive voltage positioning,
over-voltage protection, remote
sense and current sharing capa­bility.

The CS5166H will operate over a

4.15 to 20V range using either
single or dual input voltage and
is available in a 16 lead wide
body surface mount package.

Application Diagram

16 Lead SO WIDE

V

ID0

V

ID1

V

ID2

V

ID3

I

SENSE

C

OFF

SS

V

ID4

V

FB

COMP

LGnd

PWRGD

GATE(L)

PGnd

GATE(H)

V

CC

Pentium is a registered trademark of Intel Corporation.

5V to 2.8V @ 14.2A for 300MHz Pentium® II

1

V2is a trademark of Switch Power, Inc.

Rev. 6/28/99

Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: [phone] Fax: [phone]

Email: [e-mail]

Web Site: www.cherry-semi.com

A Company

®

查询CS5166H供应商

12V

1µF

C

OFF

330pF

0.1µF

0.1µF

SS

COMP

V

ID0

V

ID1

V

ID2

V

ID3

V

ID4

V

CS5166H

PWRGD

CC

GATE(H)

I

SENSE

GATE(L)

PGnd

LGnd

V

FB

5V

1200µF/10V x 3

1.2µH

3.0mΩ

1200µF

510

10V x 5

V

V
V

V

V

ID4

ID3

ID2

ID1

ID0

Pentium® II
System

0.1µF

PWRGD

3.3K

1000pF

1

Absolute Maximum Ratings

Pin Symbol Pin Name

V

MAX

V

MIN

I

SOURCE

I

SINK

2

PACKAGE PIN # PIN SYMBOL FUNCTION

Package Pin Description

CS5166H

V

CC

IC Power Input 20V -0.3V N/A 1.5A Peak 200mA DC
SS Soft Start Capacitor 6V -0.3V 200µA 10µA
COMP Compensation Capacitor 6V -0.3V 10mA 1mA
V

FB

Voltage Feedback and Current 6V -0.3V 1mA 1mA

Sense Comparator Input
C

OFF

Off-Time Capacitor 6V -0.3V 1mA 50mA
V

ID0-4

Voltage ID DAC Inputs 6V -0.3V 1mA 10µA
GATE(H) High-Side FET Driver 20V -0.3V 1.5A Peak 1.5A Peak

200mA DC 200mA DC

GATE(L) Low-Side FET Driver 20V -0.3V 1.5A Peak 1.5A Peak

200mA DC 200mA DC

I

SENSE

Current Sense Comparator Input 6V -0.3V 1mA 1mA
PWRGD Power-Good Output 6V -0.3V 10µA 30mA
PGnd Power Ground 0V 0V 1.5A Peak N/A

200mA DC

LGnd Logic Ground 0V 0V 100mA N/A

1,2,3,4,6 V

IDO

– V

ID4

Voltage ID DAC inputs. These pins are internally pulled up to 5V if left
open. V

ID4

selects the DAC range. When V

ID4

is high (logic one), the
Error Amp reference range is 2.125V to 3.525V with 100mV increments.
When V

ID4

is low (logic zero), the Error amp reference voltage is 1.325V

to 2.075V with 50mV increments.

5 SS Soft Start Pin. A capacitor from this pin to LGnd sets the Soft Start and

fault timing.

7C

OFF

Off-Time Capacitor Pin. A capacitor from this pin to LGnd sets both the
normal and extended off time.

8I

SENSE

Current Sense Comparator Inverting Input

9VCCInput Power Supply Pin.

10 GATE(H) High Side Switch FET driver pin.

11 PGnd High Current ground for the GATE(H) and GATE(L) pins.

12 GATE(L) Low Side Synchronous FET driver pin.

13 PWRGD Power-Good Output. Open collector output drives low when VFBis out

of regulation.

14 LGnd Reference ground. All control circuits are referenced to this pin.

15 COMP Error Amp output. PWM Comparator reference input. A capacitor to

LGnd provides Error Amp compensation.

16 V

FB

Error Amp, PWM Comparator feedback input, Current Sense
Comparator Non-Inverting input, and PWRGD comparator input.

Operating Junction Temperature, T

J

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to 150°C

Lead Temperature Soldering:

Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Sec max. above 183˚C, 230˚C Peak

Storage Temperature Range, TS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150˚C

CS5166H

3

Electrical Characteristics: 0˚C < TA< 70˚C; 0˚C < TJ< 125˚C; 8V < VCC< 20V; 2.0V DAC Code (V

ID4

= V

ID3

= V

ID2

=

V

ID1

=0, V

ID0

= 1), C

GATE(H

) = C

GATE(L)

= 3.3nF, C

OFF

= 330pF, CSS= 0.1µF; Unless otherwise stated.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

■ VCCSupply Current

Operating 1V<V

FB<VDAC

(Max On-Time),

No Loads on GATE(H) and GATE(L) 12 20 mA

■ V

CC

Monitor

Start Threshold GATE(H) Switching 3.75 3.95 4.15 V
Stop Threshold GATE(H) not switching 3.65 3.87 4.05 V
Hysteresis Start – Stop 80 mV

■ Error Amplifier

V

FB

Bias Current VFB= 0V 0.1 1.0 µA

COMP Source Current COMP = 1.2V to 3.6V; V

FB

= 1.9V 15 30 60 µA

COMP CLAMP Voltage V

FB

= 1.9V, Adjust COMP voltage 0.85 1.0 1.15 V

for Comp current = 60µA
COMP Clamp Current COMP = 0V 0.4 1.0 1.6 mA
COMP Sink Current V

COMP

=1.2V; VFB=2.2V; VSS> 2.5V 180 400 800 µA

Open Loop Gain Note 1 50 60 dB
Unity Gain Bandwidth Note 1 0.5 2 MHz
PSRR @ 1kHZ Note 1 60 85 dB

■ GATE(H) and GATE(L)

High Voltage at 100mA Measure V

CC

–GATE 1.2 2.0 V

Low Voltage at 100mA Measure GATE 1.0 1.5 V
Rise Time 1.6V < GATE < (V

CC

– 2.5V), 40 80 ns

8V < V

CC

< 14V

Fall Time (V

CC

– 2.5V) >GATE > 1.6V, 40 80 ns

8V < V

CC

< 14V

GATE(H) to GATE(L) Delay GATE(H)<2V, GATE(L)>2V

8V < V

CC

< 14V 30 65 100 ns

GATE(L) to GATE(H) Delay GATE(L)<2V, GATE(H)>2V

8V < V

CC

< 14V 30 65 100 ns

GATE pull-down Resistance to PGnd (Note 1) 20 50 115 kΩ

■ Over Current Detection

Current limit voltage V

FB

= 0V to 3.5V 55 76 130 mV

8V < V

CC

< 12V + 10%

I

SENSE

Bias Current I

SENSE

= 2.8V 13 30 50 µA

■ Fault Protection

SS Charge Time V

FB

= 3V, V

ISENSE

= 2.8V 1.6 3.3 5.0 ms

SS Pulse Period V

FB

= 3V, V

ISENSE

= 2.8V 25 100 200 ms

SS Duty Cycle (Charge Time/Period) × 100 1.0 3.3 6.0 %

CS5166H

4

Electrical Characteristics: 0˚C < TA< 70˚C; 0˚C < TJ< 125˚C; 8V < VCC< 20V; 2.0V DAC Code (V

ID4

= V

ID3

= V

ID2

=

V

ID1

=0, V

ID0

= 1), C

GATE(H

) = C

GATE(L)

= 3.3nF, C

OFF

= 330pF, CSS= 0.1µF; Unless otherwise stated.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

■ Fault Protection continued

SS Comp Clamp Voltage VFB= 2.7V, VSS= 0V 0.50 0.95 1.10 V

V

FB

Low Comparator Increase VFBtill normal off-time 0.9 1.0 1.1 V

■ PWM Comparator

Transient Response V

FB

= 1.2V to 5V 500ns after GATE(H) 115 175 ns

(after Blanking time) to
GATE(H) = (V

CC

– 1V)

to 1V, 8V < V

CC

< 14V

Minimum Pulse Width Drive V

FB

1.2V to 5V upon GATE(H) 100 200 300 ns

(Blanking Time) rising edge (> V

CC

– 1V), measure

GATE(H) pulse width,

8V < V

CC

< 14V

■ C

OFF

Normal Off-Time VFB= 2.7V 1.0 1.6 2.3 µs

Extended Off-Time V

SS

= VFB= 0V 5.0 8.0 12.0 µs

■ Time-Out Timer

Time-Out Time V

FB

= 2.7V, Measure GATE(H) 10 30 50 µs

Pulse Width

Fault Duty Cycle V

FB

= 0V 30 50 70 %

■ Voltage Identification DAC

Accuracy

(all codes except 11111) Measure V

FB

= COMP, (C

OFF

= Gnd) -1.0 1.0 %

V

ID4VID3VID2VID1VID0

25˚C ≤ TJ ≤ 125˚C, VCC= 12V

1 0 0 0 0 3.489 3.525 3.560 V
1 0 0 0 1 3.390 3.425 3.459 V
1 0 0 1 0 3.291 3.325 3.358 V
1 0 0 1 1 3.192 3.225 3.257 V
1 0 1 0 0 3.093 3.125 3.156 V
1 0 1 0 1 2.994 3.025 3.055 V
1 0 1 1 0 2.895 2.925 2.954 V
1 0 1 1 1 2.796 2.825 2.853 V
1 1 0 0 0 2.697 2.725 2.752 V
1 1 0 0 1 2.598 2.625 2.651 V
1 1 0 1 0 2.499 2.525 2.550 V
1 1 0 1 1 2.400 2.425 2.449 V
1 1 1 0 0 2.301 2.325 2.348 V
1 1 1 0 1 2.202 2.225 2.247 V
1 1 1 1 0 2.103 2.125 2.146 V
0 0 0 0 0 2.054 2.075 2.095 V
0 0 0 0 1 2.004 2.025 2.045 V
0 0 0 1 0 1.955 1.975 1.994 V
0 0 0 1 1 1.905 1.925 1.944 V

CS5166H

5

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

THRESHOLD ACCURACY

LOWER THRESHOLD UPPER THRESHOLD

MIN TYP MAX MIN TYP MAX UNITS

% of Nominal VIDCode -12 -8.5 -5 5 8.5 12 %

■ DAC CODE
V

ID4VID3VID2VID1VID0

1 0 0 0 0 3.102 3.225 3.348 3.701 3.824 3.948 V
1 0 0 0 1 3.014 3.133 3.253 3.596 3.716 3.836 V
1 0 0 1 0 2.926 3.042 3.158 3.491 3.607 3.724 V
1 0 0 1 1 2.838 2.950 3.063 3.386 3.499 3.612 V
1 0 1 0 0 2.750 2.859 2.968 3.281 3.390 3.500 V
1 0 1 0 1 2.662 2.767 2.873 3.176 3.282 3.388 V
1 0 1 1 0 2.574 2.676 2.778 3.071 3.173 3.276 V
1 0 1 1 1 2.486 2.584 2.683 2.966 3.065 3.164 V
1 1 0 0 0 2.398 2.493 2.588 2.861 2.956 3.052 V
1 1 0 0 1 2.310 2.401 2.493 2.756 2.848 2.940 V
1 1 0 1 0 2.222 2.310 2.398 2.651 2.739 2.828 V

Electrical Characteristics: 0˚C < TA< 70˚C; 0˚C < TJ< 125˚C; 8V < VCC< 20V; 2.0V DAC Code (V

ID4

= V

ID3

= V

ID2

=

V

ID1

=0, V

ID0

= 1), C

GATE(H

) = C

GATE(L)

= 3.3nF, C

OFF

= 330pF, CSS= 0.1µF; Unless otherwise stated.

Accuracy (all codes except 11111) Measure VFB= COMP, (C

OFF

= Gnd) -1.0 1.0 %

V

ID4VID3VID2VID1VID0

0 0 1 0 0 1.856 1.875 1.893 V
0 0 1 0 1 1.806 1.825 1.843 V
0 0 1 1 0 1.757 1.775 1.792 V
0 0 1 1 1 1.707 1.725 1.742 V
0 1 0 0 0 1.658 1.675 1.691 V
0 1 0 0 1 1.608 1.625 1.641 V
0 1 0 1 0 1.559 1.575 1.590 V
0 1 0 1 1 1.509 1.525 1.540 V
0 1 1 0 0 1.460 1.475 1.489 V
0 1 1 0 1 1.410 1.425 1.439 V
0 1 1 1 0 1.361 1.375 1.388 V
0 1 1 1 1 1.311 1.325 1.338 V
1 1 1 1 1 1.219 1.247 1.269 V

Input Threshold V

ID4

, V

ID3

, V

ID2

, V

ID1

, V

ID0

1.0 1.25 2.4 V

Input Pull-up Resistance V

ID4

, V

ID3

, V

ID2

, V

ID1

, V

ID0

25 50 100 kΩ

Input Pull-up Voltage 4.85 5.00 5.15 V

■ Power-Good Output
Low to High Delay V

FB

= (0.8 × V

DAC

) to V

DAC

30 65 110 µs

High to Low Delay V

FB

= V

DAC

to (0.8 × V

DAC

) 30 75 120 µs

Output Low Voltage V

FB

= 2.4V, I

PWRGD

= 500µA 0.2 0.3 V

Sink Current Limit V

FB

= 2.4V, PWRGD = 1V 0.5 4.0 15.0 mA

THRESHOLD ACCURACY

LOWER THRESHOLD UPPER THRESHOLD

MIN TYP MAX MIN TYP MAX UNITS

Block Diagram

6

CS5166H

Electrical Characteristics: 0˚C < TA< 70˚C; 0˚C < TJ< 125˚C; 8V < VCC< 20V; 2.0V DAC Code (V

ID4

= V

ID3

= V

ID2

=

V

ID1

=0, V

ID0

= 1), C

GATE(H

) = C

GATE(L)

= 3.3nF, C

OFF

= 330pF, CSS= 0.1µF; Unless otherwise stated.

% of Nominal V

ID

Code -12 -8.5 -5 5 8.5 12 %

■ DAC CODE
V

ID4VID3VID2VID1VID0

1 1 0 1 1 2.134 2.218 2.303 2.546 2.631 2.716 V
1 1 1 0 0 2.046 2.127 2.208 2.441 2.522 2.604 V
1 1 1 0 1 1.958 2.035 2.113 2.336 2.414 2.492 V
1 1 1 1 0 1.870 1.944 2.018 2.231 2.305 2.380 V
0 0 0 0 0 1.826 1.898 1.971 2.178 2.251 2.324 V
0 0 0 0 1 1.782 1.8520 1.923 2.126 2.197 2.268 V

0 0 0 1 0 1.738 1.807 1.876 2.073 2.142 2.212 V
0 0 0 1 1 1.694 1.761 1.828 2.021 2.088 2.156 V
0 0 1 0 0 1.650 1.715 1.781 1.968 2.034 2.100 V
0 0 1 0 1 1.606 1.669 1.733 1.916 1.980 2.044 V
0 0 1 1 0 1.562 1.624 1.686 1.863 1.925 1.988 V
0 0 1 1 1 1.518 1.578 1.638 1.811 1.871 1.932 V
0 1 0 0 0 1.474 1.532 1.591 1.758 1.817 1.876 V
0 1 0 0 1 1.430 1.486 1.543 1.706 1.763 1.820 V
0 1 0 1 0 1.386 1.441 1.496 1.653 1.708 1.764 V
0 1 0 1 1 1.342 1.395 1.448 1.601 1.654 1.708 V
0 1 1 0 0 1.298 1.349 1.401 1.548 1.600 1.652 V
0 1 1 0 1 1.254 1.303 1.353 1.496 1.546 1.596 V
0 1 1 1 0 1.210 1.258 1.306 1.443 1.491 1.540 V
0 1 1 1 1 1.166 1.212 1.258 1.391 1.437 1.484 V
1 1 1 1 1 1.094 1.138 1.181 1.306 1.349 1.393 V

Note 1: Guaranteed by design, not 100% tested in production

5V

60µA

COMP

V

V

V

V

V

PWRGD

V

I

SENSE

LGnd

SS

5 BIT
DAC

+8.5%

-+-

65µS
Delay

ERROR AMPLIFIER

+

-

+

76mV

ID0

ID1

ID2

ID3

ID4

-8.5%

FB

2µA

PWM
COMPARATOR

-

+

V

CC

30µA

-

+

I

SENSE

COMPARATOR

-

+

VFB LOW COMPARATOR

1V

2.5V

VCC Monitor

PWM Comp

Blanking

0.7V

Extended

-

+

+

-

Maximum

On-Time
Timeout

Normal

Off-Time

Off-Time
Timeout

-

+

SS Low
Comparator

SS High
Comparator

Time Out

Timer

3.95V

3.87V

R

S

FAULT

Latch

Off-Time
Timeout

FAULT

Q

FAULT

Q

Q

R

S

Q

PWM
Latch

Edge Triggered

GATE(H) = ON

GATE(H) = OFF

C

OFF

One Shot

R

S

Q

V

CC

V

GATE(H)

PGnd

V

CC

V

GATE(L)

PGnd

C

OFF

CS5166H

7

V

2

TM

Control Method

The V

2

TM

method of control uses a ramp signal that is gen­erated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is gen­erated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.

Figure 1: V

2

TM

Control Diagram.

The V

2

TM

control method is illustrated in Figure 1. The out­put voltage is used to generate both the error signal and
the ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regard­less of the origin of that change. The ramp signal also con­tains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.

A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V

2

TM

control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V

2

TM

control scheme has the same

advantages in line transient response.
A change in load current will have an affect on the output

voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.

The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal
loop. The main purpose of this ‘slow’ feedback loop is to
provide DC accuracy. Noise immunity is significantly
improved, since the error amplifier bandwidth can be
rolled off at a low frequency. Enhanced noise immunity
improves remote sensing of the output voltage, since the
noise associated with long feedback traces can be effective­ly filtered.

The Bode plot in Figure 2 shows the gain and phase margin

of the CS5166H single pole feedback loop and demon­strates the overall stability of the CS5166H-based regulator.

Figure 2: Feedback loop Bode Plot.

Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to compen­sate for a deviation in either line or load voltage. This
change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation.

A current mode controller maintains fixed error signal
under deviation in the line voltage, since the slope of the
ramp signal changes, but still relies on a change in the error
signal for a deviation in load. The V

2

TM

method of control
maintains a fixed error signal for both line and load varia­tion, since the ramp signal is affected by both line and load.

Constant Off-Time

To maximize transient response, the CS5166H uses a
Constant Off-Time method to control the rate of output
pulses. During normal operation, the Off-Time of the high
side switch is terminated after a fixed period, set by the
C

OFF

capacitor. To maintain regulation, the V

2

TM

Control
Loop varies switch On-Time. The PWM comparator moni­tors the output voltage ramp, and terminates the switch
On-Time.

Constant Off-Time provides a number of advantages.
Switch duty Cycle can be adjusted from 0 to 100% on a
pulse-by pulse basis when responding to transient condi­tions. Both 0% and 100% Duty Cycle operation can be
maintained for extended periods of time in response to
Load or Line transients. PWM Slope Compensation to
avoid sub-harmonic oscillations at high duty cycles is
avoided.

Switch On-Time is limited by an internal 30µs (typical)
timer, minimizing stress to the Power Components

Programmable Output

The CS-5166H is designed to provide two methods for pro­gramming the output voltage of the power supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage within two different ranges.

Theory Of Operation

Application Information

COMP

PWM
Comparator

+

C

–

Ramp Signal

Error

Signal

Error

Amplifier

GATE(H)

GATE(L)

E

V

FB

–

+

Reference

Voltage

.1µF
10K

Open Loop

49.63

BW

62.3 KHz

Phase margin

81.9

The first range is 2.125V to 3.525V in 100mV steps, the sec­ond is 1.325V to 2.075V in 50mV steps, depending on the
digital input code. If all five bits are left open, the CS5166H
enters adjust mode. In adjust mode, the designer can
choose any output voltage by using resistor divider feed­back to the VFBpin, as in traditional controllers. The
CS5166H is specifically designed to meet or exceed Intel’s
Pentium®II specifications.

Start-up

Until the voltage on the VCCSupply pin exceeds the 3.95V
monitor threshold, the Soft Start and Gate pins are held
low. The Fault latch is Reset (no Fault condition). The out­put of the Error Amp (COMP) is pulled up to 1V by the
Comp Clamp. When the V

CC

pin exceeds the monitor
threshold, the GATE(H) output is activated, and the Soft
Start Capacitor begins charging. The GATE(H) output will
remain on, enabling the NFET switch, until terminated by
either the PWM Comparator, or the Maximum On-Time
Timer.

If the Maximum On-Time is exceeded before the regulator
output voltage achieves the 1V level, the pulse is terminat­ed. The GATE(H) pin drives low, and the GATE(L) pin
drives high for the duration of the Extended Off-Time. This
time is set by the Time-out Timer and is approximately
equal to the Maximum On-Time, resulting in a 50% Duty
Cycle. The GATE(L) Pin will then drive low, the GATE(H)
pin will drive high, and the cycle repeats.

When regulator output voltage achieves the 1V level pre­sent at the Comp pin, regulation has been achieved and
normal Off-Time will ensue. The PWM comparator termi­nates the switch On-Time, with Off-Time set by the C

OFF

Capacitor. The V

2

TM

control loop will adjust switch Duty
Cycle as required to ensure the regulator output voltage
tracks the output of the Error Amp.

The Soft Start and Comp capacitors will charge to their
final levels, providing a controlled turn-on of the regulator
output. Regulator turn-on time is determined by the Comp
capacitor charging to its final value. Its voltage is limited
by the Soft Start Comp clamp and the voltage on the Soft
Start pin.

Figure 3: Demonstration board startup in response to increasing 12V
and 5V input voltages. Extended off time is followed by normal off
time operation when output voltage achieves regulation to the error
amplifier output.

Figure 4: Demonstration board startup waveforms.

Figure 5: Demonstration board enable startup waveforms.

Normal Operation

During Normal operation, Switch Off-Time is constant and
set by the C

OFF

capacitor. Switch On-Time is adjusted by

the V

2

TM

Control loop to maintain regulation. This results in
changes in regulator switching frequency, duty cycle, and
output ripple in response to changes in load and line.
Output voltage ripple will be determined by inductor rip­ple current and the ESR of the output capacitors (see
Figures 6 and 7).

CS5166H

8

Application Information: continued

Trace 1 - Regulator Output Voltage (1V/div.)
Trace 3 - COMP Pin (error amplifier output) (1V/div.)
Trace 4 - Soft Start Pin (2V/div.)

Trace 1 - Regulator Output Voltage (5V/div.)
Trace 2 - Inductor Switching Node (5V/div.)

Trace 1 - Regulator Output Voltage (1V/div.)
Trace 2 - Inductor Switching Node (2V/div.)
Trace 3 - 12V input (V
Trace 4 - 5V Input (1V/div.)

) (5V/div.)

CC

Figure 6: Normal Operation showing Output Inductor Ripple Current
and Output Voltage Ripple, 0.5A Load, V

OUT

= +2.825V (DAC = 10111).

Figure 7: Normal Operation showing Output Inductor Ripple Current
and Output Voltage Ripple, I

LOAD

= 14A, V

OUT

= +2.825V (DAC =

10111).

Transient Response

The CS5166H V

2

TM

Control Loop’s 150ns reaction time pro­vides unprecedented transient response to changes in
input voltage or output current. Pulse-by-pulse adjustment
of duty cycle is provided to quickly ramp the inductor cur­rent to the required level. Since the inductor current cannot
be changed instantaneously, regulation is maintained by
the output capacitor(s) during the time required to slew
the inductor current.

Overall load transient response is further improved
through a feature called “Adaptive Voltage Positioning”.
This technique pre-positions the output capacitors voltage
to reduce total output voltage excursions during changes
in load.

Holding tolerance to 1% allows the error amplifiers refer­ence voltage to be targeted +25mV high without compro­mising DC accuracy. A “Droop Resistor”, implemented
through a PC board trace, connects the Error Amps feed-

back pin (V

FB

) to the output capacitors and load and car­ries the output current. With no load, there is no DC drop
across this resistor, producing an output voltage tracking
the Error amps, including the +25mV offset. When the full
load current is delivered, a 50mV drop is developed across
this resistor. This results in output voltage being offset ­25mV low.

The result of Adaptive Voltage Positioning is that addition­al margin is provided for a load transient before reaching
the output voltage specification limits. When load current
suddenly increases from its minimum level, the output
capacitor is pre-positioned +25mV. Conversely, when load
current suddenly decreases from its maximum level, the
output capacitor is pre-positioned -25mV (see Figures 8, 9,
and 10). For best Transient Response, a combination of a
number of high frequency and bulk output capacitors are
usually used.

If the Maximum On-Time is exceeded while responding to
a sudden increase in Load current, a normal off-time
occurs to prevent saturation of the output inductor.

Figure 8: Output Voltage Transient Response to a 14A load pulse,
V

OUT

= 2.825V (DAC = 10111).

Figure 9: Output Voltage Transient Response to a 14A load step, V

OUT

=

2.825V (DAC = 10111).

CS5166H

9

Application Information: continued

Trace 1 GATE (H) (10V/div)
Trace 2 Inductor Switching Node (5V/div)
Trace 3 Output Inductor Ripple Current (2A/div)
Trace 4 V

ripple (20mV/div)

OUT

Trace 1 - GATE(H) (10/div)
Trace 2 - Inductor Switching Node (5V/div)
Trace 3 - Output Inductor Ripple Current (2A/div)
Trace 4 - V

ripple (20mV/div)

OUT

Trace 3 -Load Current (5A/10mV/div)
Trace 4 - V

Trace 1 - GATE(H) (10V/div)
Trace 2 - Inductor Switching Node (5V/div)
Trace 3 -Load Current (5A/div)
Trace 4 - V

OUT

OUT

(100mV/div)

(100mV/div)

Figure 10: Output Voltage Transient Response to a 14A load turn-off,
V

OUT

= +2.825V (DAC = 10111).

Power Supply Sequencing

The CS5166H offers inherent protection from undefined
start-up conditions, regardless of the 12V and 5V supply
power-up sequencing. The turn-on slew rates of the 12V
and 5V power supplies can be varied over wide ranges
without affecting the output voltage or causing detrimental
effects to the buck regulator.

Over-Current Protection

A loss-less hiccup mode current limit protection feature is
provided, requiring only the Soft Start capacitor to imple­ment. The CS5166H provides overcurrent protection by
sensing the current through a “Droop” resistor, using an
internal current sense comparator. The comparator com­pares this voltage drop to an internal reference voltage of
76mV (typical).

If the voltage drop across the “Droop” resistor exceeds this
threshold, the current sense comparator allows the fault
latch to be set. This causes the regulator to stop switching.
During this over current condition, the CS5166H stays off
for the time it takes the Soft Start capacitor to slowly dis­charge by a 2µA current source until it reaches its lower

0.7V threshold.
At that time the regulator attempts to restart normally by

delivering short gate pulses to both FETs. The CS5166H
will operate initially in its extended off time mode with a
50% duty cycle, while the Soft Start capacitor is charged
with a 60µA charge current. The gates will switch on while
the Soft Start capacitor is charged to its upper 2.7V thresh­old. During an overload condition the Soft Start charge
/discharge current ratio sets the duty cycle for the pulses
(2µA/60µA = 3.3%), while actual duty cycle is half that due
to the extended off time mode (1.65%) when V

FB

is less
than 1V. The Soft Start hiccup pulses last for a 3ms period
at the end of which the duty cycle repeats if a fault is
detected, otherwise normal operation resumes.

This protection scheme minimizes thermal stress to the reg­ulator components, input power supply, and PC board

traces, as the over current condition persists. Upon
removal of the overload, the fault latch is cleared, allowing
normal operation to resume. The current limit trip point
can be adjusted through an external resistor, providing the
user with the current limit set-point flexibility.

Figure 11: Demonstration board hiccup mode short circuit protection.
Gate pulses are delivered while the Soft Start capacitor charges, and
cease during discharge.

Figure 12: Demonstration board Start up with regulator output shorted
to ground.

Overvoltage Protection

Overvoltage protection (OVP) is provided as result of the
normal operation of the V

2

TM

control topology and requires
no additional external components. The control loop
responds to an overvoltage condition within 100ns, causing
the top MOSFET to shut off, disconnecting the regulator
from its input voltage. The bottom MOSFET is then activat­ed, resulting in a “crowbar” action to clamp the output
voltage and prevent damage to the load (see Figures 13
and 14). The regulator will remain in this state until the
overvoltage condition ceases or the input voltage is pulled
low. The bottom FET and board trace must be properly
designed to implement the OVP function. If a dedicated
OVP output is required, it can be implemented using the
circuit in Figure 15. In this figure the OVP signal will go
high (overvoltage condition), if the output voltage (V

CORE

)

exceeds 20% of the voltage set by the particular DAC code

Protection and Monitoring Features

CS5166H

10

Application Information: continued

Trace 1 - GATE(H) (10V/div)
Trace 2 - Inductor Switching Node (5V/div)
Trace 3 -Load Current (5A/div)
Trace 4 - V

(100mV/div)

OUT

Trace 4 - 5V Supply Voltage (2V/div.)
Trace 3 - Soft Start Timing Capacitor (1V/div.)
Trace 2 - Inductor Switching Node (2V/div.)

Trace 4 = 5V from PC Power Supply (2V/div.)
Trace 2 = Inductor Switching Node (2V/div.)

and provided that PWRGD is low. It is also required that
the overvoltage condition be present for at least the
PWRGD delay time for the OVP signal to be activated. The
resistor values shown in Figure 15 are for V

DAC

= +2.8V

(DAC = 10111). The V

OVP

(overvoltage trip-point) can be

set using the following equation:

V

OVP

= V

BEQ3

(

1 +

)

Figure 13: OVP response to an input-to-output short circuit by immedi­ately providing 0% duty cycle, crow-barring the input voltage to
ground.

Figure 14: OVP response to an input-to-output short circuit by pulling
the input voltage to ground.

Figure 15: Circuit to implement a dedicated OVP output using the
CS5166H.

Power-Good Circuit

The Power-Good pin (pin 13) is an open-collector signal
consistent with TTL DC specifications. It is externally
pulled -up, and is pulled low (below 0.3V) when the regu­lator output voltage typically exceeds ± 8.5% of the nomi­nal output voltage. Maximum output voltage deviation
before Power-Good is pulled low is ± 12%.

Figure 16: PWRGD signal becomes logic high as V

OUT

enters -8.5% of

lower PWRGD threshold, V

OUT

= +2.825V (DAC = 10111).

Figure 17: Power-Good response to an out of regulation condition.

R2
R1

CS5166H

11

Application Information: continued

Trace 4 = 5V from PC Power Supply (5V/div.)
Trace1 = Regulator Output Voltage (1V/div.)
Trace 2 = Inductor Switching Node (5V/div.)

V

CORE

15K

R1

Q3

2N3906

R2

10K

CS5166H

PWRGD

+5V

+5V

10K

Q1

2N3906

56K

5K

20K

Q2

2N3904

10K

OVP

Trace 4 = 5V from PC Power Supply (2V/div.)
Trace 1 = Regulator Output Voltage (1V/div.)

Trace 2 - PWRGD (2V/div)
Trace 4 - V

OUT

(1V/div)

2.825V

Trace 1 PWRGD (2V/div)
Trace 4 VFB (1V/div)

Figure 17 shows the relationship between the regulated
output voltage V

FB

and the Power-Good signal. To prevent
Power-Good from interrupting the CPU unnecessarily, the
CS5166H has a built-in delay to prevent noise at the V

FB

pin from toggling Power-Good. The internal time delay is
designed to take about 75µs for Power-Good to go low and
65µs for it to recover. This allows the Power-Good signal to
be completely insensitive to out of regulation conditions
that are present for a duration less than the built in delay
(see Figure 18).

It is therefore required that the output voltage attains an
out of regulation or in regulation level for at least the built­in delay time duration before the Power-Good signal can
change state.

Figure 18: Power-Good is insensitive to out of regulation conditions that
are present for a duration less than the built in delay.

External Output Enable Circuit

On/off control of the regulator can be implemented
through the addition of two additional discrete compo­nents (see Figure 19). This circuit operates by pulling the
Soft Start pin high, and the I

SENSE

pin low, emulating a cur-

rent limit condition.

Figure 19: Implementing shutdown with the CS5166H.

Selecting External Components

The CS5166H buck regulator can be used with a wide
range of external power components to optimize the cost
and performance of a particular design. The following
information can be used as general guidelines to assist in
their selection.

NFET Power Transistors

Both logic level and standard FETs can be used. The refer­ence designs derive gate drive from the 12V supply which
is generally available in most computer systems and utilize
logic level FETs. A charge pump may be easily implement­ed to permit use of standard FET’s or support 5V or 12V
only systems (maximum of 20V). Multiple FET’s may be
paralleled to reduce losses and improve efficiency and
thermal management.

Voltage applied to the FET gates depends on the applica­tion circuit used. Both upper and lower gate driver outputs
are specified to drive to within 1.5V of ground when in the
low state and to within 2V of their respective bias supplies
when in the high state. In practice, the FET gates will be
driven rail to rail due to overshoot caused by the capacitive
load they present to the controller IC. For the typical appli­cation where V

CC

= 12V and 5V is used as the source for
the regulator output current, the following gate drive is
provided:

V

GS (TOP)

= 12V - 5V = 7V, V

GS(BOTTOM)

= 12V,

(see Figure 20).

Figure 20: Gate drive waveforms depicting rail to rail swing.

CS5166H

12

Application Information: continued

Trace 1 PWRGD (2V/div)
Trace 4 V

FB

(1V/div)

IN4148

Shutdown

Input

5V

MMUN2111T1 (SOT-23)

5

SS

CS5166H

8

I

SENSE

Trace 3 = GATE(H) (10V/div.)

GATE(H) - 5V

Trace 1=
Trace 4 =
Trace 2 = Inductor Switching Node (5V/div.)

GATE(L)

IN

(10V/div.)

13

Application Information: continued

CS5166H

Figure 21: Normal Operation showing the guaranteed Non-Overlap
time between the High and Low - Side MOSFET Gate Drives, I

LOAD

=

14A.

The CS5166H provides adaptive control of the external
NFET conduction times by guaranteeing a typical 65ns
non-overlap (as seen in Figure 21) between the upper and
lower MOSFET gate drive pulses. This feature eliminates
the potentially catastrophic effect of “shoot-through cur­rent”, a condition during which both FETs conduct causing
them to overheat, self-destruct, and possibly inflict irre­versible damage to the processor.

The most important aspect of FET performance is RDSON,
which effects regulator efficiency and FET thermal man­agement requirements.

The power dissipated by the MOSFETs may be estimated
as follows:

Switching MOSFET:

Power = I

LOAD

2

× RDSON× duty cycle

Synchronous MOSFET:

Power = I

LOAD

2

× RDSON× (1 - duty cycle)

Duty Cycle =

Off Time Capacitor (C

OFF

)

The C

OFF

timing capacitor sets the regulator off time:

T

OFF

= C

OFF

× 4848.5

The preceding equation for Duty Cycle can also be used to
calculate the regulator switching frequency and select the
C

OFF

timing capacitor:

C

OFF

=

where

period =

.

Schottky Diode for Synchronous FET

For synchronous operation, A Schottky diode may be
placed in parallel with the synchronous FET to conduct the
inductor current upon turn off of the switching FET to
improve efficiency. The CS5166H reference circuit does not
use this device due to its excellent design. Instead, the body
diode of the synchronous FET is utilized to reduce cost and
conducts the inductor current. For a design operating at
200kHz or so, the low non-overlap time combined with
Schottky forward recovery time may make the benefits of
this device not worth the additional expense. The power
dissipation in the synchronous MOSFET due to body diode
conduction can be estimated by the following equation:

Power = Vbd× I

LOAD

× conduction time × switching fre-

quency

Where Vbd= the forward drop of the MOSFET body diode.
For the CS5166H demonstration board:

Power = 1.6V × 14.2A × 100ns × 200kHz = 0.45W
This is only 1.1% of the 40W being delivered to the load.

“Droop” Resistor for Adaptive Voltage Positioning

Adaptive voltage positioning is used to help keep the out­put voltage within specification during load transients. To
implement adaptive voltage positioning a “Droop
Resistor” must be connected between the output inductor
and output capacitors and load. This resistor carries the full
load current and should be chosen so that both DC and AC
tolerance limits are met. An embedded PC trace resistor
has the distinct advantage of near zero cost implementa­tion. However, this droop resistor can vary due to three
reasons: 1) the sheet resistivity variation causes the thick­ness of the PCB layer to vary. 2) the mismatch of L/W, and

3) temperature variation.

1) Sheet Resistivity

for one ounce copper, the thickness variation is
typically 1.15 mil to 1.35 mil. Therefore the error due to
sheet resistivity is:

= 16%

2) Mismatch due to L/W

The variation in L/W is governed by variations due to
the PCB manufacturing process that affect the
geometry and the power dissipation capability of the
droop resistor. The error due to L/W mismatch is
typically 1%

1.35 - 1.15

1.25

1

switching frequency

Period × (1-Duty Cycle)

4848.5

V

OUT

+ (I

LOAD

× RDS

ON OF SYNCH FET

)

VIN+ (I

LOAD

× RDS

ON OF SYNCH FET

) - (I

LOAD

× RDS

ON OF SWITCH FET

)

Trace 1 - GATE(H) (5V/div)
Trace 2 - GATE(L) (5V/div)

CS5166H

14

3) Thermal Considerations

Due to I2× R power losses the surface temperature of
the droop resistor will increase causing the resistance
to increase. Also, the ambient temperature variation
will contribute to the increase of the resistance,
according to the formula:

R = R

20

[1+ α20(Τ−20)]
where:
R20= resistance at 20˚C

α =

T= operating temperature

R = desired droop resistor value
For temperature T = 50˚C,
the % R change = 12%

Droop Resistor Tolerance

Tolerance due to sheet resistivity variation 16%
Tolerance due to L/W error 1%
Tolerance due to temperature variation 12%
Total tolerance for droop resistor 29%
In order to determine the droop resistor value the nominal

voltage drop across it at full load has to be calculated. This
voltage drop has to be such that the output voltage full
load is above the minimum DC tolerance spec.

V

DROOP(TYP)

=

Example: for a 300MHz Pentium®II, the DC accuracy spec
is 2.74 < V

CC(CORE)

< 2.9V, and the AC accuracy spec is

2.67V < V

CC(CORE)

<2.93V. The CS5166H DAC output volt-

age is +2.796V < V

DAC

< +2.853V. In order not to exceed

the DC accuracy spec, the voltage drop developed across
the resistor must be calculated as follows:

V

DROOP(TYP)

=

= = 43mV

With the CS5166H DAC accuracy being 1%, the internal
error amplifier’s reference voltage is trimmed so that the
output voltage will be 25mV high at no load. With no load,
there is no DC drop across the resistor, producing an out­put voltage tracking the error amplifier output voltage,
including the offset. When the full load current is deliv­ered, a drop of -43mV is developed across the resistor.
Therefore, the regulator output is pre-positioned at 25mV
above the nominal output voltage before a load turn-on.
The total voltage drop due to a load step is ∆V-25mV and
the deviation from the nominal output voltage is 25mV
smaller than it would be if there was no droop resistor.
Similarly at full load the regulator output is pre-positioned
at 18mV below the nominal voltage before a load turn-off.
the total voltage increase due to a load turn-off is ∆V-18mV
and the deviation from the nominal output voltage is
18mV smaller than it would be if there was no droop resis­tor. This is because the output capacitors are pre-charged
to value that is either 25mV above the nominal output
voltage before a load turn-on or, 18mV below the nominal
output voltage before a load turn-off (see Figure 8).

Obviously, the larger the voltage drop across the droop
resistor (the larger the resistance), the worse the DC and
load regulation, but the better the AC transient response.

Current Limit Setpoint Calculations

The following is the design equation used to set the cur­rent limit trip point by determining the value of the
embedded PCB trace used as a current sensing element.

The current limit setpoint has to be higher than the normal
full load current. Attention has to be paid to the current

2.796V-2.74V

1.3

[V

DAC(MIN)-VDC PENTIUM®II(MIN)

]

1+R

DROOP(TOLERANCE)

[V

DAC(MIN)-VDC(MIN)

]

1+R

DROOP(TOLERANCE)

0.00393
˚C

Application Information: continued

Figure 22: Circuit used to determine the voltage across the droop resistor that will trip the internal current sense comparator.

V

IN

IFB

Q1

LR

Q2

DROOP

V

OUT

C

OUT

RFB

R

ISENSE

ISENSE

V

FB

I

SENSE

Current Limit Comparator

I

SENSE

V

CS5166H

TH

+

-

15

rating of the external power components as these are the
first to fail during an overload condition. The MOSFET
continuous and pulsed drain current rating at a given case
temperature has to be accounted for when setting the cur­rent limit trip point. For example the IRL 3103S (D2 PAK)
MOSFET has a continuous drain current rating of 45A at
V

GS

= 10V and TC= 100˚C. Temperature curves on MOS­FET manufacturers’ data sheets allow the designer to
determine the MOSFET drain current at a particular V

GS

and TJ(junction temperature). This, in turn, will assist the
designer to set a proper current limit, without causing
device breakdown during an overload condition.

For a 300MHz Pentium ® II CPU the full load is 14.2A. The
internal current sense comparator current limit voltage
limits are: 55mV < V

TH

< 130mV. Also, there is a 29% total

variation in R

SENSE

as discussed in the previous section.

We select the value of the current sensing element (embed­ded PCB trace) for the minimum current limit setpoint:

R

SENSE(MAX)

= ⇒ R

SENSE

× 1.29 = ⇒

R

SENSE

× 1.29 = 3.87mΩ ⇒ R

SENSE

= 3mΩ

We calculate the range of load currents that will cause the
internal current sense comparator to detect an overload
condition.

From the overcurrent detection data section (pg 3),

Nominal Current Limit Setpoint

V

TH(TYP)

= 76mV.

I

CL(NOM) =

Maximum Current Limit Setpoint

Therefore , I

CL(NOM)

= = 25.3A

V

TH(MAX)

= 110mV.

Therefore,

I

CL(MAX)

=

= = = 51.6A

Therefore, the range of load currents that will cause the
internal current sense comparator to detect an overload
condition through a 3mΩ embedded PCB trace is: 14.2A <
I

CL

< 51.6A, with 25.3A being the nominal overload condi-

tion.
There may be applications whose layout will require the

use of two extra filter components, a 510Ω resistor in series
with the I

SENSE

pin, and a 0.1µF capacitor between the

I

SENSE

and VFBpins. These are needed for proper current

limit operation and the resistor value is layout dependent.
This series resistor affects the calculation of the current

limit setpoint, and has to be taken into account when
determining an effective current limit.

The calculations below show how the current limit set­point is determined when this 510Ω is taken into consider­ation.

V

TRIP

= VTH+ (I

SENSE

× R

ISENSE

) – (RFB× IFB)

Where V

TRIP

= voltage across the droop resistor that trips

the I

SENSE

comparator

VTH= internal I

SENSE

comparator threshold

I

SENSE

= I

SENSE

bias current

R

ISENSE

= I

SENSE

pin 510Ω filter resistor
RFB= VFBpin 3.3K filter resistor
IFB= VFBbias current

Minimum current sense resistor (droop resistor) voltage
drop required for current limit when R

ISENSE

is used

V

TRIP(MIN)

= 55mV + (13µA × 510) – (3.3K × 1µA) = 55mV +

6.6mV – 3.3mV = 58.3mV

Nominal current sense resistor (droop resistor) voltage
drop required for current limit when R

ISENSE

is used

V

TRIP(NOM)

= 76mV + (30µA × 510) – (3.3K × 0.1µA) =

76mV + 15.3mV – 0.33mV = 90.97mV

Maximum current sense resistor (droop resistor) voltage
drop required for current limit when R

ISENSE

is used

V

TRIP(MAX)

= 110mV + (50µA × 510) = 110mV + 25.5mV =

135.5mV

The value of R

SENSE

(current sense PCB trace) is then calcu-

lated:
R

SENSE(MAX)

= = 4.1mΩ

R

SENSE(NOM)

= = = 3.18mΩ

The range of load currents that will cause the internal cur­rent sense comparator to detect an overload condition is as
follows:

Nominal Current Limit Setpoint

I

CL(NOM)

= V

TRIP(NOM)

/ R

SENSE(NOM)

Therefore,

I

CL(NOM)

= 90.97mV / 3.18mΩ = 28.6A

4.1mΩm

1.29

R

SENSE(MAX)

1.29

58.3mV

14.2A

110mV

3mΩ × 0.71

110mV

R

SENSE

× 0.71

110mV

R

SENSE(MIN)

76mV

3mΩ

V

TH(TYP)

R

SENSE(NOM)

55mV

14.2A

V

TH(MIN)

I

CL(MIN)

Application Information: continued

CS5166H

CS5166H

16

Maximum Current Limit Setpoint

I

CL(MAX)

= V

TRIP(MAX)

/ R

SENSE(MAX)

Therefore,

I

CL(MAX)

= 135mV / 3.18mΩ × 0.71 = 60A

Therefore, the range of load currents that will cause the
internal current sense comparator to detect an overload
condition through a 3mΩ embedded PCB trace is: 14.2A <
ICL 60A, with 28.6A being the nominal overload condition.

Design Rules for Using a Droop Resistor

The basic equation for laying an embedded resistor is:

R

AR

= ρ × or R = ρ ×

where:

A= W × t = cross-sectional area
ρ= the copper resistivity (µΩ - mil)

L= length (mils)
W = width (mils)
t = thickness (mils)
For most PCBs the copper thickness, t, is 35µm (1.37 mils)

for one ounce copper. ρ = 717.86µΩ-mil
For a Pentium®II load of 14.2A the resistance needed to

create a 43mV drop at full load is:

R

DROOP

= = = 3.0mΩ

The resistivity of the copper will drift with the temperature
according to the following guidelines:

∆R = 12% @ TA = +50˚C
∆R = 34% @TA= +100˚C

Droop Resistor Width Calculations

The droop resistor must have the ability to handle the load
current and therefore requires a minimum width which is
calculated as follows (assume one ounce copper thickness):

43mV

14.2A

43mV

I

OUT

L

(W × t)

L

A

Application Information: continued

Figure 23: Current sharing of a 2.8V/30A power supply using two CS5166H synchronous buck regulators.

12V

5V

1200µF/10V x 3

330pF

0.1µF

0.1µF

330pF

0.1µF

1µF

1µF

C

OFF

SS

COMP

V

ID0

V

ID1

V

ID2

V

ID3

V

C

OFF

SS

COMP

V

ID0

V

ID1

V

ID2

V

ID3

V

IRL3103S

5V

IRL3103S

IRL3103S

1.2µH

3.3K

1000pF

1200µF/10V x 3

IRL3103S

1.2µH

0.1µF

3.3K

0.1µF

3.0mΩ

510

3.0mΩ

510

1200µF
10V x 5

2.8V/30A
Power
Supply

PWRGD

V

ID4

V

ID3

V

ID2

V

ID1

V

ID0

CC

CC

GATE(H)

I

SENSE

GATE(L)

PGnd

LGnd

V

FB

GATE(H)

I

SENSE

GATE(L)

PGnd

LGnd

V

FB

V

CS5166H

ID4

PWRGD

12V

V

CS5166H

ID4

1000pF

CS5166H

17

Application Information: continued

W =

where:
W = minimum width (in mils) required for proper power

dissipation, and I

LOAD

Load Current Amps.
The Pentium®II maximum load current is 14.2A.
Therefore:

W = = 284 mils = 0.7213cm

Droop Resistor Length Calculation

L = = = 1626 mil = 4.13cm

Implementing current sharing using the “Droop
Resistor”

In addition to improving load transient performance, the
CS5166H V

2

TM

control method allows the droop resistor to
provide the additional capability to easily implement cur­rent sharing. Figure 23 shows a simplified schematic of
two current sharing synchronous buck regulators.
Each buck regulator’s droop resistor is terminated at the
load. The PWM control signal from each Error Amp is con­nected together, causing the inner PWM loop to regulate to
a common voltage. Since the voltage at each resistor termi­nal is the same, this configuration results in equal voltage
being applied across each matched droop resistor. The
result is equal current flowing through each buck regula­tor. An additional benefit is that synchronization to a com­mon switching frequency tends to be achieved because
each regulator shares a common PWM ramp signal.

In practice, each buck regulator will regulate to a slightly
different output voltage due to mismatching of the PWM
comparators, slope of the PWM ramp (output voltage rip­ple), and propagation delays. At light loads, the result can
be very poor current sharing. With zero output current,
some regulators may be sourcing current while others may
be sinking current.

This results in additional power dissipation and lower effi­ciency than would be obtained by a single regulator. This
is usually not an issue since efficiency is most important
when a supply is fully loaded.

This effect is similar to the difference in efficiency between
synchronous and non-synchronous buck regulators.
Synchronous Buck regulators have lower efficiency at light
loads because inductor current is always continuous, flow­ing from the load to ground during switch off-time
through the synchronous rectifier. Under full load condi­tions, the synchronous design is more efficient due to the
lower voltage drop across the synchronous rectifier.
Likewise, the efficiency of droop sharing regulators will be
lower at light loads due to the continuous current flow in
the droop resistors. Efficiency at heavy loads tends to be
higher due to reduced I2R losses.

The output current of each regulator can be calculated
from:

I

N

= (V

OUT(N)

- V

OUT

) / R

DROOP(N)

where: V

OUT(N)

and R

DROOP(N)

are the output voltage and

droop resistance of a particular regulator and V

OUT

is the
system output voltage. Output current is the sum of each
regulator’s current:

I

OUT

= I1 + I2 + … + I

N

Current sharing improves with increasing load current.
The increasing voltage drop across the droop resistor due
to increasing load current eventually swamps out the dif­ferences in regulator output voltages. If a large enough
voltage can be developed across the droop resistors, cur­rent sharing accuracy will be determined solely by their
matching. To realize the benefits of current sharing, it is
not necessary to obtain perfect matching. Keeping output
currents within +/- 10% is usually acceptable.

For microprocessor applications, the value of the droop
resistor must be selected to optimize adaptive voltage
positioning, current sharing, current limit and efficiency.
Current sharing is realized by simply connecting the
COMP pins of the respective buck regulators, as shown in
Figure 23.

Figure 24 shows operation with no load. In this case, there
is insufficient output voltage ripple across the droop resis­tors to produce complete synchronization. Duty Cycle is
close to the theoretical 56% (V

OUT/VIN

) resulting in a

switching frequency of approximately 275kHz.

Figure 25 shows operation with a 30 Amp load.
Synchronization between the two regulators is now
obtained due to increased ripple voltage. Increased losses
cause the V

2

TM

control loop to increase on-time to compen­sate. This results in a larger duty cycle and a correspond­ing decrease in switching frequency to 233kHz.

Figure 24: No load waveforms.

0.0030 × 284 × 1.37

717.86

R

DROOP

× W × t

ρ

14.2A

0.05

I

LOAD

0.05

Trace 1 Output voltage ripple
Trace 2 Buck regulator #1 inductor switching node
Trace 3 Buck regulator #2 inductor switching node

Figure 25: 30A load waveforms.

Figure 26: 15A load transient waveforms.

Figure 26 shows supply response to a 15A load step with a
30A/µs slew rate. The V

2

TM

control loop immediately
forces the duty cycle to 100%, ramping the current in both
inductors up. A voltage spike of 136mV due to output
capacitor impedance occurs. The inductive component of
the spike due to ESL recovers within several microseconds.
The resistive component due to ESR decreases as inductor
current replaces capacitor current.

The benefit of adaptive voltage positioning in reducing the
voltage spike can readily be seen. The differences in DC
voltage and duty cycle can also be observed. This particu­lar transient occurred near the beginning of regulator off­time, resulting in a longer recovery time and increased
voltage spike.

Output Inductor

The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the induc­tor value will decrease output voltage ripple, but degrade
transient response.

Inductor Ripple Current

Ripple current =

Example: V

IN

= +5V, V

OUT

= +2.8V, I

LOAD

= 14.2A, L =

1.2µH, Freq = 200KHz

Ripple current = = 5.1A

Output Ripple Voltage

V

RIPPLE

= Inductor Ripple Current × Output Capacitor

ESR

Example:
V

IN

= +5V, V

OUT

= +2.8V, I

LOAD

= 14.2A, L = 1.2µH,

Switching Frequency = 200KHz
Output Ripple Voltage = 5.1A × Output Capacitor ESR

(from manufacturer’s specs)
ESR of Output Capacitors to limit Output Voltage Spikes

ESR =

This applies for current spikes that are faster than regula­tor response time. Printed Circuit Board resistance will
add to the ESR of the output capacitors.

In order to limit spikes to 100mV for a 14.2A Load Step,
ESR = 0.1/14.2 = 0.007Ω

Inductor Peak Current

Peak Current = Maximum Load Current +

()

Example: V

IN

= +5V, V

OUT

= +2.8V, I

LOAD

= 14.2A, L = 1.2µH,

Freq = 200KHz

Peak Current = 14.2A + (5.1/2) = 16.75A

A key consideration is that the inductor must be able to
deliver the Peak Current at the switching frequency with­out saturating.

Response Time to Load Increase
(limited by Inductor value unless Maximum On-Time is

exceeded)

Response Time =

Example: V

IN

= +5V, V

OUT

= +2.8V, L = 1.2µH, 14.2A

change in Load Current

Response Time = = 7.7µs

1.2µH × 14.2A

(5V-2.8V)

L × ∆ I

OUT

(VIN-V

OUT

)

Ripple

Current

2

∆ V

OUT

∆ I

OUT

[(5V-2.8V) × 2.8V]

[200KHz × 1.2µH × 5V]

[(VIN- V

OUT

) × V

OUT

]

(Switching Frequency × L × VIN)

Application Information: continued

18

CS5166H

Trace 1 Output voltage ripple
Trace 2 Buck regulator #1 inductor switching node
Trace 3 Buck regulator #2 inductor switching node

Trace 1 Output voltage ripple
Trace 2 Buck regulator #1 inductor switching node
Trace 3 Buck regulator #2 inductor switching node

19

Response Time to Load Decrease

(limited by Inductor value)

Response Time =

Example: V

OUT

= +2.8V, 14.2A change in Load Current,

L = 1.2µH

Response Time = = 6.1µs

Input and Output Capacitors

These components must be selected and placed carefully to
yield optimal results. Capacitors should be chosen to pro­vide acceptable ripple on the input supply lines and regu­lator output voltage. Key specifications for input capacitors
are their ripple rating, while ESR is important for output
capacitors. For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.

Thermal Considerations for Power MOSFETs and Diodes

In order to maintain good reliability, the junction tempera­ture of the semiconductor components should be kept to a
maximum of 150°C or lower. The thermal impedance
(junction to ambient) required to meet this requirement can
be calculated as follows:

Thermal Impedance =

A heatsink may be added to TO-220 components to reduce
their thermal impedance. A number of PC board layout
techniques such as thermal vias and additional copper foil
area can be used to improve the power handling capability
of surface mount components.

EMI Management

As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing
for compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions.
These components are not required for regulator operation
and experimental results may allow them to be eliminated.
The input filter inductor may not be required because bulk
filter and bypass capacitors, as well as other loads located
on the board will tend to reduce regulator di/dt effects on
the circuit board and input power supply. Placement of the
power component to minimize routing distance will also
help to reduce emissions.

Figure 27: Filter components. Figure 28: Input Filter.

Layout Guidelines

When laying out the CPU buck regulator on a printed cir­cuit board, the following checklist should be used to
ensure proper operation of the CS5166H.

1) Rapid changes in voltage across parasitic capacitors and
abrupt changes in current in parasitic inductors are major
concerns for a good layout.

2) Keep high currents out of sensitive ground connections.
Avoid connecting the IC Gnd (LGnd) between the source
of the lower FET and the input capacitor Gnd.

3) Avoid ground loops as they pick up noise. Use star or
single point grounding.

4) For high power buck regulators on double-sided PCBs a
single large ground plane (usually the bottom) is recom­mended.

5) Even though double-sided PCBs are usually sufficient
for a good layout, four-layer PCBs are the optimum
approach to reducing susceptibility to noise. Use the two
internal layers as the +5V and Gnd planes, the top layer for
the power connections and component vias, and the bot­tom layer for the noise sensitive traces.

6) Keep the inductor switching node small by placing the
output inductor, switching and synchronous FETs close
together.

7) The FET gate traces to the IC must be as short, straight,
and wide as possible. Ideally, the IC has to be placed right
next to the FETs.

8) Use fewer, but larger output capacitors, keep the capaci­tors clustered, and use multiple layer traces with heavy
copper to keep the parasitic resistance low.

9) Place the switching FET as close to the +5V input capaci­tors as possible.

10) Place the output capacitors as close to the load
as possible.

T

J(MAX)

- T

A

Power

Thermal Management

1.2µH × 14.2A

2.8V

L × Change in I

OUT

V

OUT

Application Information: continued

CS5166H

2µH

33Ω

1000pF

2µH

1200µF x 3/16V

+

CS5166H

20

Figure 31: Percent Output Error vs DAC Voltage Setting,

VCC= 12V, TA = 25˚C, V

ID4

= 0.

Figure 34: Percent Output Error vs. DAC Output Voltage Setting

VCC= 12V, TA = 25˚C, V

ID4

= 1.

Typical Performance Characteristics

Figure 30: GATE(H) & GATE(L) Falltime vs. Load Capacitance.

Figure 33: DAC Output Voltage vs Temperature, DAC Code = 10111,

VCC= 12V.

Figure 29: GATE(L) Risetime vs. Load Capacitance. Figure 32: GATE(H) Risetime vs. Load Capacitance.

11) Place the VFBfilter resistor in series with the
VFBpin (pin 16) right at the pin.

12) Place the VFBfilter capacitor right at the VFBpin (pin

16).

13) The “Droop” Resistor (embedded PCB trace) has to be
wide enough to carry the full load current.

14) Place the VCCbypass capacitor as close as possible to
the V

CC

pin and connect it to the PGnd pin of the IC.

Connect the PGnd pin directly to the Gnd plane.

15) Create a subground (local Gnd) plane preferably on
the PCB top layer and under the IC controller. Connect all
logic capacitor returns and the LGnd pin of the IC to this
plane. Connect the subground plane to the main Gnd
plane using a minimum of four (4) vias.

Application Information: continued

200
180
160
140
120
100

80
60

Risetime (ns)

40
20

0

0 2000 4000 6000 8000 10000 12000 14000 16000

Load Capacitance (pF)

VCC=12V
T

=25C˚

A

200
180
160
140
120
100

80
60

Risetime (ns)

40

20

0

0

2000 4000 6000 8000 10000 12000 14000 16000

Load Capacitance (pF)

VCC=12V
TA=25C˚

200
180

160
140
120
100

80
60

Falltime (ns)

40

20

0

0 2000 4000 6000 8000 10000 12000 14000 16000

Load Capacitance (pF)

VCC=12V
T

=25C˚

A

0.04

0.02

0

-0.02

-0.04

-0.06

-0.08

DAC Output Voltage Deviation (%)

-0.1
0

Junction Temperature (˚C)

0.04

0.02

0

-0.02

-0.04

-0.06

Output Error (%)

-0.08

-0.1

1.325 1.375 1.425 1.475 1.525 1.575 1.625 1.675 1.725 1.775 1.825 1.875 1.925 1.975 2.025 2.075

DAC Output Voltage Setting (V)

0.05

0

-0.05

-0.1

-0.15

Output Error (%)

-0.2

-0.25

2.125 2.225 2.325 2.425 2.525 2.625 2.725 2.825 2.925 3.025 3.125 3.225 3.325 3.425 3.525

DAC Output Voltage Setting (V)

12010080604020

CS5166H

21

Figure 35: +12V to +2.8V @ 14.2A for 300 MHz Pentium®II.

Figure 36: +5V to +2.8V @ 14.2A for 300 MHz Pentium®II.

Additional Application Circuits

+12V

0.1µF

1000pf

0.1µF

18V 1N4746

C

SS

COMP

V

ID0

V

ID1

V

ID2

V

ID3

V

ID4

I

SENSE

V

OFF

GATEH

CS5166H

GATEL

LGND

PWRGD

18Ω

CC

V

PGND

1N5818

1N5818

FB

1µF

1000pF

0.1µF

3.3K

0.1µF

+12V

IRL3103S

1.2µH

IRL3103S

510

1200µF/16V

x3

Droop Resistor

(Embedded PCB trace)

3mΩ

1200µF/10V

x5

V

CC

V

SS

PWRGD

PENTIUM

SYSTEM

V

ID4

V

ID3

V

ID2

V

ID1

V

ID0

®

II

+5V

CC
ID0

ID1

CS5166H

ID2

ID3

ID4

OFF

0.1µF

1µF

V

GATEH

V

GATEL

PGND

I

SENSE

PWRGD

LGND

MBRS120

1µF

MBRS120

MBRS120

330pF

0.1µF

V
V

V

V

V
V

C

SS

COMP

1200uF/10V

x3

IRL3103S

1.2µH

IRL3103S

Droop Resistor

(Embedded PCB trace)

3mΩ

1200µF/10V

x5

V

cc

V

ss

510

V

FB

0.1µF

3.3K

1000pF

PWRGD

PENTIUM

SYSTEM

V

ID4

V

ID3

V

ID2

V

ID1

V

ID0

®

II

Package Specification

D

Lead Count Metric English

Max Min Max Min

16L SO Wide 10.50 10.10 .413 .398

Thermal Data 16L

SO Wide

R

ΘJC

typ 23 ˚C/W

R

ΘJA

typ 105 ˚C/W

PACKAGE DIMENSIONS IN mm (INCHES)

PACKAGE THERMAL DATA

Ordering Information

Part Number Description

CS5166HGDW16 16L SO Wide
CS5166HGDWR16 16L SO Wide (tape & reel)

Cherry Semiconductor Corporation reserves the right to
make changes to the specifications without notice. Please
contact Cherry Semiconductor Corporation for the latest
available information.

22

CS5166H

Rev. 6/28/99 © 1999 Cherry Semiconductor Corporation

Surface Mount Wide Body (DW); 300 mil wide

1.27 (.050) BSC

7.60 (.299)

7.40 (.291)

10.65 (.419)

10.00 (.394)

D

0.32 (.013)

0.23 (.009)

1.27 (.050)

0.40 (.016)

REF: JEDEC MS-013

2.49 (.098)

2.24 (.088)

0.51 (.020)

0.33 (.013)

2.65 (.104)

2.35 (.093)

0.30 (.012)

0.10 (.004)