Page 1
1
Features
■ 1A Totem Pole Output
Driver
■ High Speed Oscillator
(700kHz max)
■ No Stability
Compensation Required
■ Lossless Short Circuit
Protection
■ V
CC
Monitor
■ 2% Precision Reference
■ Programmable Soft Start
Package Options
CS51031
Fast PFET Buck Controller
Does Not Require Compensation
CS51031
Description
The CS51031 is a switching controller for use in DC-DC converters.
It can be used in the buck topology
with a minimum number of external components. The CS51031 consists of a VCCmonitor for controlling the state of the device, 1.0A
power driver for controlling the
gate of a discrete P-channel transistor, fixed frequency oscillator, short
circuit protection timer, programmable soft start, precision reference, fast output voltage monitoring comparator, and output stage
driver logic with latch.
The high frequency oscillator
allows the use of small inductors
and output capacitors, minimizing
PC board area and systems cost.
The programmable soft start
reduces current surges at start up.
The short circuit protection timer
significantly reduces the duty cycle
to approximately 1/30 of its cycle
during short circuit conditions.
The CS51031 is available in 8L SO
and 8L PDIP plastic packages.
Typical Application Diagram
V
GATE
PGnd
C
OSC
Gnd
V
C
CS
V
CC
V
FB
8 Lead SO Narrow & PDIP
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
A Company
¨
Rev. 2/13/98
5V - 12V
C
OSC
150pF
V
GATE
V
PGnd
C
Gnd
C
IN
47mF
V
GATE
CS51031
OSC
C
CS
V
CC
V
FB
20W
MP
IRF7416
MBRS360
D
1
RV
10W
CV
100mF
.01mF
CC
CC
100
CS
0.1mF
R
B
2.5kW
L
4.7mH
1
V
O
3.3V @ 3A
1
R
1.5kW
C
A
RR
0.1mF
C
O
100mF ´ 2
Page 2
Power Supply Voltage, VCC........................................................................................................................................................20V
Driver Supply Voltage, VC..........................................................................................................................................................20V
Driver Output Voltage, V
GATE
...................................................................................................................................................20V
C
OSC
, CS, VFB(Logic Pins) ............................................................................................................................................................6V
Peak Output Current................................................................................................................................................................. 1.0A
Steady State Output Current ................................................................................................................................................200mA
Operating Junction Temperature, TJ..................................................................................................................................... 150¡C
Operating Temperature Range, TA............................................................................................................................-40¡ to 125¡C
Storage Temperature Range, TS...................................................................................................................................-65 to 150¡C
ESD (Human Body Model).........................................................................................................................................................2kV
Lead Temperature Soldering
Wave Solder (through hole styles only) .....................................................................................10 sec. max, 260¡C peak
Reflow (SMD styles only) ......................................................................................60 sec. max above 183¡C, 230¡C peak
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
2
CS51031
Absolute Maximum Ratings
Electrical Characteristics: Specifications apply for 4.5 ² VCC² 16V, 3V ² VC² 16V,
-40¡C ² TJ² 125¡C, unless otherwise specified.
■ Oscillator V
FB
= 1.2V
Frequency C
OSC
= 470pF 160 200 240 kHz
Charge Current 1.4V < V
COSC
< 2V 110 µA
Discharge Current 2.7V > V
COSC
> 2V 660 µA
Maximum Duty Cycle 1 Ð (t
OFF/tON
) 80.0 83.3 %
■ Short Circuit Timer V
FB
= 1.0V; CS = 0.1µF; V
COSC
= 2V
Charge Current 1V < V
CS
< 2V 175 264 325 µA
Fast Discharge Current 2.55V > V
CS
> 2.4V 40 66 80 µA
Slow Discharge Current 2.4V > V
CS
> 1.5V 4 6 10 µA
Start Fault Inhibit Time 0V < V
CS
< 2.5V 0.70 0.85 1.40 ms
Valid Fault Time 2.6V > V
CS
> 2.4V 0.2 0.3 0.45 ms
GATE Inhibit Time 2.4V > V
CS
> 1.5V 9 15 23 ms
Fault Duty Cycle 2.5 3.1 4.6 %
■ CS Comparator V
FB
= 1V
Fault Enable CS Voltage 2.5 V
Max. CS Voltage VFB= 1.5V 2.6 V
Fault Detect Voltage VCSwhen GATE goes high 2.4 V
Fault Inhibit Voltage Minimum V
CS
1.5 V
Hold Off Release Voltage VFB= 0V 0.4 0.7 1.0 V
Regulator Threshold VCS= 1.5V 0.725 0.866 1.035 V
Voltage Clamp
■ V
FB
Comparators V
COSC
= VCS= 2V
Regulator Threshold Voltage TJ= 25¡C (note 1) 1.225 1.250 1.275 V
TJ= -40 to 125¡C 1.210 1.250 1.290 V
Fault Threshold Voltage TJ= 25¡C (note 1) 1.12 1.15 1.17 V
TJ= -40 to 125¡C 1.10 1.15 1.19 V
Threshold Line Regulation 4.5V ² VCC² 16V 6 15 mV
Input Bias Current VFB= 0V 1 4 µA
Voltage Tracking (Regulator Threshold Voltage - 70 100 120 mV
Fault Threshold Voltage)
Input Hysteresis Voltage 4 20 mV
Page 3
CS51031
3
Electrical Characteristics: Specifications apply for 4.5 ² VCC² 16V, 3V ² VC² 16V, -40¡C ² TJ² 125¡C,
unless otherwise specified.
Package Pin Description
PACKAGE PIN # PIN SYMBOL FUNCTION
8L SO Narrow & PDIP
1V
GATE
Driver pin to gate of external PFET.
2 PGnd Output power stage ground connection.
3C
OSC
Oscillator frequency programming capacitor.
4 Gnd Logic ground.
5V
FB
Feedback voltage input.
6V
CC
Logic supply voltage.
7 CS Soft start and fault timing capacitor.
8V
C
Driver supply voltage.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
■ Power Stage V
CC
= VC= 10V; VFB= 1.2V
GATE DC Low Saturation V
COSC
= 1V; 200mA Sink 1.2 1.5 V
Voltage
GATE DC High Saturation V
COSC
= 2.7V; 200mA Source; VC= V
GATE
1.5 2.1 V
Voltage
Rise Time C
GATE
= 1nF; 1.5V < V
GATE
< 9V 25 60 ns
Fall Time C
GATE
= 1nF; 9V > V
GATE
> 1.5V 25 60 ns
■ V
CC
Monitor
Turn On Threshold 4.200 4.400 4.600 V
Turn Off Threshold 4.085 4.300 4.515 V
Hysteresis 65 130 200 mV
■ Current Drain
I
CC
4.5V < VCC< 16V, Gate switching 4.5 6.0 mA
I
C
3V < VC< 16V, Gate non-switching 2.7 4.0 mA
Shutdown I
CC
VCC= 4, 500 900 µA
Note 1: Guaranteed by design not 100% tested in production.
Page 4
CS51031
4
Block Diagram
Control Scheme
The CS51031 monitors and the output voltage to determine
when to turn on the PFET. If VFBfalls below the internal
reference voltage of 1.25V during the oscillatorÕs charge
cycle, the PFET is turned on and remains on for the duration of the charge time. The PFET gets turned off and
remains off during the oscillatorÕs discharge time with the
maximum duty cycle to 80%. It requires 7mV typical, and
20mV maximum ripple on the VFBpin is required to operate. This method of control does not require any loop stability compensation.
Startup
The CS51031 has an externally programmable soft start feature that allows the output voltage to come up slowly, preventing voltage overshoot on the output.
At startup, the voltage on all pins is zero. As V
CC
rises, the
VCvoltage along with the internal resistor RGkeeps the
PFET off. As VCCand VCcontinue to rise, the oscillator
capacitor (C
OSC
) and the Soft start/Fault Timing capacitor
(CS) charges via internal current sources. C
OSC
gets
charged by the current source ICand CS gets charged by
the ITsource combination described by:
ICS= IT - (+).
The internal Holdoff Comparator ensures that the external
PFET is off until VCS> 0.7V, preventing the GATE flip-flop
(F2) from being set. This allows the oscillator to reach its
operating frequency before enabling the drive output. Soft
start is obtained by clamping the VFBcomparatorÕs (A6)
reference input to approximately 1/2 of the voltage at the
CS pin during startup, permitting the control loop and the
output voltage to slowly increase. Once the CS pin charges
above the Holdoff Comparator trip point of 0.7V, the low
feedback to the VFBComparator sets the GATE flip-flop
during C
OSC
Õs charge cycle. Once the GATE flip-flop is set,
V
GATE
goes low and turns on the PFET. When VCSexceeds
I
T
5
I
T
55
Theory of Operation
Circuit Description
Figure 1: Block Diagram for CS51031
V
RG
C
V
GATE
PGnd
V
FB
Gnd
V
REF
I
C
OSC
V
CC
CS
C
7I
C
1.5V
V
CC
OK
V
CC
V
= 3.3V
REF
G3
I
T
I
55
I
T
T
5
2.4V
Oscillator
Comparator
A1
2.5V
V
REF
3.3V
CS
Comparator
A2
2.5V1.5V
A3
+
G1
G2
G4
G5
Slow Discharge
Comparator
V
GATE
Flip-Flop
Q
R
F2
S
Q
+
Hold
Off
Comp
-
-
Fault
Comp
1.15V
+
R
Q
F1
S
Q
Slow Discharge
Flip-Flop
A6
0.7V
-
+
V
FB
Comparator
1.25V
CS Charge
Sense
Comparator
A4
+
-
2.3V
Page 5
CS51031
5
2.4V, the CS charge sense comparator (A4) sets the V
FB
comparator reference to 1.25V completing the startup
cycle.
Lossless Short Circuit Protection
The CS51031 has ÒlosslessÓ short circuit protection since
there is no current sense resistor required. When the voltage at the CS pin (the fault timing capacitor voltage ) reaches 2.5V during startup, the fault timing circuitry is enabled.
During normal operation the CS voltage is 2.6V. During a
short circuit or a transient condition, the output voltage
moves lower and the voltage at V
FB
drops. If VFBdrops
below 1.15V, the output of the fault comparator goes high
and the CS51031 goes into a fast discharge mode. The fault
timing capacitor, CS, discharges to 2.4V. If the VFBvoltage
is still below 1.15V when the CS pin reaches 2.4V, a valid
fault condition has been detected. The slow discharge
comparator output goes high and enables gate G5 which
sets the slow discharge flip flop. The Vgate flip flop resets
and the output switch is turned off. The fault timing
capacitor is slowly discharged to 1.5V. The CS51031 then
enters a normal startup routine. If the fault is still present
when the fault timing capacitor voltage reaches 2.5V, the
fast and slow discharge cycles repeat as shown in figure 2.
If the VFBvoltage is above 1.15V when CS reaches 2.4V a
fault condition is not detected, normal operation resumes
and CS charges back to 2.6V. This reduces the chance of
erroneously detecting a load transient as a fault condition.
Figure 2. Voltage on start capacitor (VGS), the gate (V
GATE
), and in the
feedback loop (VFB), during startup, normal and fault conditions.
Buck Regulator Operation
Figure 3. Buck regulator block diagram.
A block diagram of a typical buck regulator is shown in
Figure 3. If we assume that the output transistor is initially
off, and the system is in discontinuous operation, the
inductor current ILis zero and the output voltage is at its
nominal value. The current drawn by the load is supplied
by the output capacitor CO. When the voltage across C
O
drops below the threshold established by the feedback
resistors R1 and R2 and the reference voltage V
REF
, the
power transistor Q1 switches on and current flows through
the inductor to the output. The inductor current rises at a
rate determined by (VIN-V
OUT
)/L. The duty cycle (or ÒonÓ
time) for the CS51031 is limited to 80%. If output voltage
remains higher than nominal during the entire C
OSC
change time, the Q1 does not turn on, skipping the pulse.
Control
Feedback
V
IN
L
D
1
R
1
R
2
R
LOAD
C
O
Q1
C
IN
2.5V
0V
FAULT
NORMAL OPERATION
START
T
START td1
td2
t
FAULTtRESTARTtFAULT
S2
S2
S2
S3
S3
S3
S3
S1
S1
S1
2.6V
2.4V
1.5V
0V
1.25V
1.15V
V
CS
V
GATE
V
FB
Circuit Description: continued
Applications Information
Specifications 12V to 5V, 3A Buck converter
V
IN
= 12V ±20% (i.e. 14.4V max., 12Vnom., 9.6V min.)
V
OUT
= 5V ±2%
I
OUT
= 0.3A to 3A
Output ripple voltage < 50mV max.
Efficiency > 80%
fSW= 200kHz
1) Duty cycle estimates
Since the maximum duty cycle D, of the CS51031 is limited
to 80% min., it is necessary to estimate the duty cycle for
the various input conditions over the complete operating
range.
The duty cycle for a buck regulator operating in a continuous conduction mode is given by:
D =
V
OUT
+ V
F
VIN- V
SAT
CS51031 Design Example
Page 6
CS51031
6
Applications Information: continued
where V
SAT
= R
ds(on)
´ I
OUT
max. and R
ds(on)
is the value at
TJ 100ûC.
If VF= 0.60V and V
SAT
= 0.60V then the above equation
becomes:
D
MAX
=
= 0.62
D
MIN
=
= 0.40
2) Switching frequency and on and off time calculations
Given that f
SW
= 200kHz and D
MAX
= 0.80
T = = 5µs
T
ON(max) =
T ´ D
MAX
= 5µs ´ 0.62 @ 3µs
T
ON(min) =
T ´ D
MIN
= 5µs ´ 0.40 = 2µs
T
OFF(max) = TON(min)
= 5µs - 2µs = 3µs
3) Oscillator Capacitor Selection
The switching frequency is set by C
OSC
, whose value is
given by:
C
OSC
in pF =
95 ´ 10
-6
F
sw
(
1+ -
()
2
)
4) Inductor selection
The inductor value is chosen for continuous mode operation down to 0.3Amps.
The ripple current ÆI = 2 ´ I
OUT
min = 2 ´ 0.3A = 0.6A.
L
min
= = =28µH
This is the minimum value of inductor to keep the ripple
current to <0.6A during normal operation.
A smaller inductor will result in larger ripple current.
Ripple current at a minimum off time is
ÆI = = =0.4A
The core must not saturate with the maximum expected
current, here given by:
I
MAX
= I
OUT
+ ÆI/2 = 3A+0.4A/2 = 3.2A
5) Output capacitor
The output capacitor and the inductor form a low pass filter. The output capacitor should have a low ESL and ESR.
Low impedance aluminum electrolytic, tantalum or organic semiconductor capacitors are a good choice for an output capacitor. Low impedance aluminum are less expensive. Solid tantalum chip capacitors are available from a
number of suppliers and are the best choice for surface
mount applications.
The output capacitor limits the output ripple voltage. The
CS51031 needs a maximum of 20mV of output ripple for
the feedback comparator to change state. If we assume that
all the inductor ripple current flows through the output
capacitor and that it is an ideal capacitor (i.e. zero ESR), the
minimum capacitance needed to limit the output ripple to
50mV peak to peak is given by:
C = = = 7.5µF
The minimum ESR needed to limit the output voltage ripple to 50mV peak to peak is:
ESR = = = 83m½
The output capacitor should be chosen so that its ESR is
less than 83m½.
During the minimum off time, the ripple current is 0.4A
and the output voltage ripple will be:
ÆV=ESR ´ ÆI = 83m½
´ 0.4 = 33mV.
6) V
FB
divider
V
OUT
= 1.25V
()
= 1.25V
(
+ 1
)
The input bias current to the comparator is 4µA. The resistor divider current should be considerably higher than this
to ensure that there is sufficient bias current. If we choose
the divider current to be at least 250 times the bias current
this permits a divider current of 1mA and simplifies the
calculations.
= R1 + R2 = 5k½
Let R2 = 1K
Rearranging the divider equation gives:
R1 = R2
(
- 1)= 1k½
(
- 1)= 3k½
5V
1.25
V
OUT
1.25
5V
1mA
R1
R2
R1 + R2
R2
50 ´ 10
-3
0.6A
ÆV
ÆI
0.6A
8 ´ (200 ´ 103Hz) ´ (50 ´ 10-3V)
ÆI
8 ´ fSW´ ÆV
5.6V ´ 2µs
28µH
(V
OUT
+ VF) ´ T
OFF(min)
L
MIN
5.6V ´ 3µs
0.6A
(V
OUT
+ VD) ´ T
OFF(max)
ÆI
30 ´ 10
3
F
sw
F
sw
3 ´ 10
6
1
f
SW
5.6
13.8
5.6
9
Page 7
CS51031
7
Applications Information: continued
7) Divider bypass Capacitor Crr
Since the feedback resistors divide the output voltage by a
factor of 4, i.e. 5V/1.25V= 4, it follows that the output ripple
is also divided by four. This would require that the output
ripple be at least 60mV (4 ´ 15mV) to trip the feedback comparator. We use a capacitor Crr to act as an AC short .
The ripple voltage frequency is equal to the switching frequency so we choose Crr = 1nF.
8) Soft start and Fault timing capacitor CS.
CS performs several important functions. First it provides a
delay time for load transients so that the IC does not enter
a fault mode every time the load changes abruptly.
Secondly it disables the fault circuitry during startup, it
also provides soft start by clamping the reference voltage
during startup, allowing it to rise slowly, and, finally it
controls the hiccup short circuit protection circuitry. This
reduces the duty cycle to approximately 0.035 during short
circuit conditions.
An important consideration in calculating CS is that itÕs
voltage does not reach 2.5V (the voltage at which the fault
detect circuitry is enabled) before V
FB
reaches 1.15V other-
wise the power supply will never start.
If the VFBpin reaches 1.15V, the fault timing comparator
will discharge CSand the supply will not start. For the V
FB
voltage to reach 1.15V the output voltage must be at least
4 ´ 1.15 = 4.6V.
If we choose an arbitrary startup time of 900µs, the value of
CSis:
t
Startup
=
C
S
min = = 950nF @ 0.1µF
The fault time is the sum of the slow discharge time the fast
discharge time and the recharge time. It is dominated by the
slow discharge time.
The first parameter is the slow discharge time, it is the time
for the CScapacitor to discharge from 2.4V to 1.5V and is
given by:
t
SlowDischarge(t)
=
Where I
Discharge
is 6µA typical.
t
SlowDischarge(t)
= CS´ 1.5 ´ 10
5
The fast discharge time occurs when a fault is first detected. The CScapacitor is discharged from 2.5V to 2.4V.
t
FastDischarge(t)
=
Where I
FastDischarge
is 66µA typical.
t
FastDischarge(t)
= CS´ 1515
The recharge time is the time for C
S
to charge from 1.5V to
2.5V.
t
Charge(t)
=
Where I
Charge
is 264µA typical.
t
Charge(t)
= CS´ 3787
The fault time is given by:
t
Fault
= CS´ (3787 + 1515 + 1.5 ´ 105)
t
Fault
= CS´ (1.55 ´ 105)
For this circuit
t
Fault
= 0.1 ´ 10-6´ 1.55 ´ 105= 15.5µS
A larger value of CSwill increase the fault time out time
but will also increase the soft start time.
9) Input Capacitor
The input capacitor reduces the peak currents drawn from
the input supply and reduces the noise and ripple voltage
on the V
CC
and VCpins. This capacitor must also ensure
that the VCCremains above the UVLO voltage in the event
of an output short circuit. A low ESR capacitor of at least
100µF is good. A ceramic surface mount capacitor should
also be connected between VCCand ground to filter high
frequency noise.
10) MOSFET Selection
The CS51031 drives a P-channel MOSFET. The V
GATE
pin
swings from Gnd to VC. The type of PFET used depends on
the operating conditions but for input voltages below 7V a
logic level FET should be used.
A PFET with a continuous drain current (ID) rating greater
than the maximum output current is required.
The Gate-to-Source voltage VGSand the Drain-to Source
Breakdown Voltage should be chosen based on the input
supply voltage.
The power dissipation due to the conduction losses is
given by:
PD= I
OUT
2
´ R
DS(ON)
´ D where
R
DS(ON)
is the value at TJ = 100ûC.
The power dissipation of the PFET due to the switching losses is given by:
PD= 0.5 ´ V
IN
´ I
OUT
´ (tr) ´ f
SW
Where tr= Rise Time.
11) Diode Selection
The flyback or catch diode should be a Schottky diode
because of itÕs fast switching ability and low forward voltage drop. The current rating must be at least equal to the
maximum output current. The breakdown voltage should
be at least 20V for this 12V application.
The diode power dissipation is given by:
P
D
= I
OUT
´ VD´ (1 - D
min
)
C
S
´ (2.5V - 1.5V)
I
Charge
CS ´ (2.5V - 2.4V)
I
FastDischarge
CS´ (2.4V - 1.5V)
I
Discharge
900µs ´ 264µA
2.5V
C
S
´ 2.5V
I
Charge
Page 8
CS51031
8
8L PDIP; 300 mil wide
8
© 1999 Cherry Semiconductor Corporation
Rev. 2/13/98
Ordering Information
Part Number Description
CS51031YD8 8L SO Narrow
CS51031YDR8 8L SO Narrow (tape & reel)
CS51031YN8 8L PDIP
0.39 (.015)
MIN.
2.54 (.100) BSC
1.77 (.070)
1.14 (.045)
D
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.
.203 (.008)
.356 (.014)
REF: JEDEC MS-001
3.68 (.145)
2.92 (.115)
8.26 (.325)
7.62 (.300)
7.11 (.280)
6.10 (.240)
.356 (.014)
.558 (.022)
Cherry Semiconductor Corporation reserves the right to
make changes to the specifications without notice. Please
contact Cherry Semiconductor Corporation for the latest
available information.
Package Specification
Thermal Data 8L SO Narrow 8L PDIP
R
QJC
typ 45 52 ûC/W
R
QJA
typ 165 100 ûC/W
D
Lead Count Metric English
Max Min Max Min
8L SO Narrow 5.00 4.80 .197 .189
8L PDIP 10.16 9.02 .400 .355
PACKAGE DIMENSIONS IN mm (INCHES)
PACKAGE THERMAL DATA
8L SO Narrow; 150 mil wide
1.27 (.050) BSC
0.51 (.020)
0.33 (.013)
6.20 (.244)
5.80 (.228)
4.00 (.157)
3.80 (.150)
1.57 (.062)
1.37 (.054)
D
0.25 (0.10)
0.10 (.004)
1.75 (.069) MAX
1.27 (.050)
0.40 (.016)
REF: JEDEC MS-012
0.25 (.010)
0.19 (.008)
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