Datasheet CS44L10-KZ Datasheet (Cirrus Logic)

Digital PWM Headphone Monitor

CS44L10

Features

l

Up to 100 dB Dynamic Range

l

2.4 V to 5.0 V supply

l

Sample rates up to 96 kHz

l

Digital Tone Control

—3 selectable HPF and LPF corner frequencies
—12 dB boost for bass and treble - 1 dB step size

l

Programmable Digital volume control

—+18 to -96 dB in 1 dB steps

l

Peak signal soft limiting

l

De-emphasis for 32 kHz, 44.1 kHz, and 48
kHz

l

Selectable outputs for each channel including

—Channel A: R, L, mono (L + R) / 2, mute
—Channel B: R, L, mono (L + R) / 2, mute

l

PWM PopGuard

l

100 mW/Channel into 16 Ω @ 3.6 V

®

Description

The CS44L10 is a complete stereo digital-to-PWM Class D au­dio amplifier system controller including interpolation, volume
control, and a headphone amplifier in a 16-pin TSSOP
package.

The CS44L10 architecture uses a direct-to-digital approach
that maintains digital signal integrity to the final output filter.
This minimizes analog interference effects that can negatively
affect system performance.

The CS44L10 contains on-chip digital bass and treble boost,
peak signal limiting, and de-emphasis. The PWM amplifier can
achieve greater than 90% efficiency. This efficiency leads to
longer battery life for portable systems, smaller device pack­age, less heat sink requirements, and smaller power supplies.

The CS44L10 is ideal for portable audio, headphone amplifi­ers, and mobile phones.

ORDERING INFORMATION

CS44L10-KZ -10 to 70 °C 16-pin TSSOP

SCL/DIF0

Control Port

VL

Digital Volume

SDIN

SCLK

LRCK

Serial
Audio

Port

RST

Control,

Bass/Treble

Boost,

Compression

Limiting,

De-emphasis

Advance Product Information

SDA/DEM

Multibit ∆Σ

Modul ator with

Correction

Interpolation

Multibit ∆Σ

Input Sampling Rate

LRCLK/MCLK Ratio

MCLK

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Modul ator with

Correction

PWM

Conversion

PWM

Conversion

Level

Shifter

Level

Shifter

VA_HPA

HP_A

GND_HPA

VA_HPB

HP_B

GND_HPB

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

Copyright  Cirrus Logic, Inc. 2001

(All Rights Reserved)

MAY ‘01

DS541PP1

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4

2. TYPICAL CONNECTION DIAGRAMS ...................................................................................10

3. REGISTER QUICK REFERENCE ...................................................................................... 12

4. REGISTER DESCRIPTIONS .................................................................................................. 13

5. PIN DESCRIPTION ................................................................................................................. 25

6. APPLICATIONS ..................................................................................................................... 26

6.1 Grounding and Power Supply Decoupling ...................................................................... 26

6.2 Clock Modes ................................................................................................................... 26

6.3 De-Emphasis .................................................................................................................. 26

6.4 PWM PopGuard Transient Control .................................................................................26

6.5 Recommended Power-up Sequence .............................................................................. 27

6.5.1 Stand Alone Mode ................................................................................................ 27

6.5.2 Control Port Mode ................................................................................................ 27

7. CONTROL PORT INTERFACE ..............................................................................................28

7.1 Two-Wire Format ............................................................................................................ 28

7.1.1 Writing in Two-Wire Format ................................................................................. 28

7.1.2 Reading in Two-Wire Format ............................................................................... 28

7.2 Memory Address Pointer (MAP) ...................................................................................29

7.2.1 INCR (Auto Map Increment Enable) ....................................................................29

7.2.2 MAP3-0 (Memory Address Pointer) ..................................................................... 29

8. PARAMETER DEFINITIONS .................................................................................................. 32

9. PACKAGE DIMENSIONS ....................................................................................................... 33

CS44L10

LIST OF FIGURES

Figure 1. Serial Audio Data Interface Timing .................................................................................. 7

Figure 2. Control Port Timing - Two-Wire Format ...........................................................................9

Figure 3. Typical CS44L10 Connection Diagram Stand-Alone Mode ........................................... 10

Figure 4. Typical CS44L10 Connection Diagram Control Port Mode ............................................ 11

Figure 5. Dynamics Control Block Diagram .................................................................................. 20

Figure 6. De-Emphasis Curve ....................................................................................................... 23

Figure 7. Control Port Timing, Two-Wire Format .......................................................................... 28

Figure 8. Single Speed Stopband Rejection ................................................................................. 30

Figure 9. Single Speed Transition Band........................................................................................ 30

Figure 10. Single Speed Transition Band (Detail) ......................................................................... 30

Figure 11. Single Speed Passband Ripple.................................................................................... 30

Figure 12. Double Speed Stopband Rejection .............................................................................. 30

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

Preliminary product informati on describes products which are in producti on, but for which full characterization data is not yet available. Advance product infor­mation descr ibes products which are in dev elopment and subject to development changes. Ci rrus Logic, Inc. has made best eff orts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of

any kind (express or implied). Customers are advised to obtain the latest version of relevant i nformati on to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and condi tions of sale supplied at the time of order acknowledgment, includi ng those
pertaini ng to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including
use of this information as the basis for manufacture or sale of any items, nor for infri ngements of patents or other rights of third parties. This document is the
property of Cirrus Logic, Inc. and by furnishing thi s information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, tr ade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained
herein, gi ves consent for copies to be made of the informati on only for use within your organization with respect to Cirrus Logic integrated circuits or other parts
of Cirrus Logic, Inc. The same consent is gi ven for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other
copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic,
Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be register ed in some
jurisdictions. A li st of Cirrus Logi c, Inc. trademarks and service marks can be f ound at http://www.cirrus.com

.

2 DS541PP1

Figure 13. Double Speed Transition Band .................................................................................... 30

Figure 14. Double Speed Transition Band (Detail) ....................................................................... 31

Figure 15. Double Speed Passband Ripple.................................................................................. 31

Figure 16. Left Justified, up to 24-Bit Data....................................................................................31

Figure 17. Right Justified, 24-Bit Data ......................................................................................... 31

Figure 18. I

Figure 19. Right Justified, 16-Bit Data .......................................................................................... 32

2

S, Up to 24-Bit Data ................................................................................................. 31

LIST OF TABLES

Table 1. Register Quick Reference ..............................................................................................12

Table 2. Example Volume Settings .............................................................................................. 15

Table 3. Example Bass Boost Settings ........................................................................................ 15

Table 4. Example Treble Boost Settings ...................................................................................... 15

Table 5. Base Boost Corner Frequencies in Single Speed Mode ................................................ 16

Table 6. Base Boost Corner Frequencies in Double Speed Mode .............................................. 16

Table 7. Treble Boost Corner Frequencies in Single Speed Mode .............................................. 17

Table 8. Example Limiter Attack Rate Settings ............................................................................ 18

Table 9. Example Limiter Release Rate Settings ......................................................................... 18

Table 10. ATAPI Decode ............................................................................................................. 19

Table 11. Single Speed Clock Modes - Control Port Mode .......................................................... 21

Table 12. Single Speed Clock Modes - Stand-Alone Mode ......................................................... 22

Table 13. Double Speed Clock Modes - Control Port Mode ........................................................ 22

Table 14. Double Speed Clock Modes - Stand-Alone Mode ........................................................ 22

Table 15. Digital Interface Format (Stand-Alone Mode) ............................................................... 25

CS44L10

DS541PP1 3

CS44L10

1. CHARACTERISTICS AND SPECIFICATIONS

(TA = 25 °C; GND = 0 V; Logic "1" = VL = 2.4 V; Logic "0" = GND = 0 V; Full-Scale Output Sine Wave, 997 Hz,
MCLK = 12.288 MHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for Single Speed
Mode = 48 kHz, SCLK = 3.072 MHz; Fs for Double Speed Mode = 96 kHz, SCLK = 6.144 MHz. Test load
R

=16Ω, CL = 10pF.) (See Typical CS44L10 Connection Diagram.)

L

Parameter Symbol Min Typ Max Unit

Headphone Output Dynamic Performance for VD = VL = VA_HPx = 2.4 V

Dynamic Range 18 to 24-Bit A-Weighted

UnWeighted

16-Bit A-Weighted

Unweighted

Total Harmonic Distortion + Noise 0 dBFS

THD+N -

-20 dBFS

-60 dBFS

Interchannel Isolation (1 kHz)

Headphone Output Dynamic Performance for VD = VL = VA_HPx = 3.0 V

Dynamic Range 18 to 24-Bit A-Weighted

UnWeighted

16-Bit A-Weighted

Unweighted

Total Harmonic Distortion + Noise 0 dB

THD+N -

-20 dB

-60 dB

Interchannel Isolation (1 kHz)

Headphone Output Dynamic Performance for VD = VL = VA_HPx = 5.0 V

Dynamic Range 18 to 24-Bit A-Weighted

UnWeighted

16-Bit A-Weighted

Unweighted

Total Harmonic Distortion + Noise 0 dB

THD+N -

-20 dB

-60 dB

Interchannel Isolation (1 kHz)

TBD
TBD

-

-

-

-

93
91
91
89

-62

-71

-31

-

-

-

-

TBD

-

-

dB
dB
dB
dB

dB
dB
dB

-TBD-dB

TBD
TBD

-

-

-

-

95
92
92
90

-64

-72

-32

-

-

-

-

TBD

-

-

dB
dB
dB
dB

dB
dB
dB

-TBD-dB

TBD
TBD

-

-

-

-

99
96
91
93

-67

-76

-36

-

-

-

-

TBD

-

-

dB
dB
dB
dB

dB
dB
dB

-TBD-dB

4 DS541PP1

CHARACTERISTICS AND SPECIFICATIONS (Continued)

Parameters Symbol Min Typ Max Units

PWM Headphone Output

Full Scale Headphone Output Voltage

Headphone Output Quiescent Voltage

Interchannel Gain Mismatch

Modulation Index
Maximum Headphone Output VA_HPx= 2. 4V

AC-Current VA_H P x=5.0V

Parameter

Symbol Min Typ Max Min Typ Max Unit

Digital Filter Response (Note 1))

Passband to -0.05 dB corner
(Note 2) to -0.1 dB corner

to -3 dB corner

Frequency Response 10 Hz to 20 kHz

(Note 3)

StopBand

StopBand Attenuation (Note 4)

Group Delay

Passband Group Delay Deviation 0 - 40 kHz

tgd - 9/Fs - - 4/Fs - s

.5465 - - .577 - - Fs

0 - 20 kHz

De-emphasis Error Fs = 32 kHz
(Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

I

HP

Single Speed Mode Double Speed Mode

0

-

0

-.02 - +.08 0 - +0.11 dB

50 - - 55 - - dB

-

--±0.36/Fs

-

-

-

TBD 0.85 x VA_HP TBD Vp

-0.5 x VA_HP- VDC

-0.1-dB

--85%

-

-

-

.4535

-

-

-

-

-

.4998

+.2/-.1

+.05/-.14

+0/-.22

CS44L10

45
80

-

-

0
0

-

-

--±1.39/Fs
±0.23/Fs--

(Note 5)

-

-

-

-

-

­.4426
.4984

mA
mA

Fs
Fs
Fs

s
s

dB
dB
dB

Note:

1. Filter response is not tested but is guaranteed by design.

2. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 8-15) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

3. Referenced to a 1 kHz, full-scale sine wave.

4. For Single Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For Double Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.

5. De-emphasis is not available in double speed mode.

DS541PP1 5

CS44L10

ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Max Units

DC Power Supplies: Headphone

Interface

Digital

Input Current, Any Pin Except Supplies

Digital Input Voltage

Ambient Operating Temperature (power applied)

Storage Temperature

CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.)

Parameters Symbol Min Typ Max Units

Ambient Temperature
DC Power Supplies: Headphone

Interface

Digital

VA_H P x

VL

VD

I

in

V

IND

T

A

T

stg

T

A

VA_H Px

VL

VD

2.4

2.4

2.4

5.5

5.5

5.5

±10 mA

-0.3 VL + 0.4 V

-55 125 °C

-65 150 °C

-10 - 70 °C

2.4

2.4

2.4

-

-

-

5.0

5.0

5.0

V
V
V

V
V
V

SWITCHING CHARACTERISTICS (T

Logic 1 = VL, CL = 20pF)

Parameters Symbol Min Typ Max Units

Input Sample Rate Single Speed Mode

Double Speed Mode

MCLK Duty Cycle

LRCK Duty Cycle

SCLK Pulse Width Low

SCLK Pulse Width High

SCLK Period Single Speed Mode

Double Speed Mode

SCLK rising to LRCK edge delay

SCLK rising to LRCK edge setup time

SDIN valid to SCLK rising setup time

SCLK rising to SDIN hold time

= -10 to 70°C; VL = 2.4V - 5.0V; Inputs: Logic 0 = GND,

A

Fs
Fs

8

50

-

-

50

100

40 50 60 %

40 50 60 %

t

sclkl

t

sclkh

t

sclkw

t

sclkw

t

slrd

t

slrs

t

sdlrs

t

sdh

20 - - ns

20 - - ns

1

---------------------­128()Fs

1

------------------­64()Fs

--ns

--ns

20 - - ns

20 - - ns

20 - - ns

20 - - ns

kHz
kHz

6 DS541PP1

CS44L10

LRCK

t

slrs

SCLK

SDATA

t

slrd

t

sclkw

t

sdlrs

Figure 1. Serial Audio Data Interface Timing

POWER AND THERMAL CHARACTERISTICS (GND = 0 V; All voltages with respect to

ground. All measurements taken with all zeros input and open outputs, unless otherwise specified.)

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current- VA_HPx= 2.4 V
Normal Operation VD = 2.4 V

VL= 2.4 V

Power Supply Current- VA_HPx = 2.4V
Power Down Mode (Note 6) VD = 2.4V

VL = 2.4V

Power Supply Current- VA_HPx = 5.0 V
Normal Operation VD = 5.0 V

VL = 5.0 V

Power Supply Current- VA_HPx = 5.0V
Power Down Mode (Note 6) VD = 5.0V

VL = 5.0 V

Total Power Dissipation- All Supplies = 2.4 V
Normal Operation All Supplies = 5.0 V

Power Supply Rejection Ratio

Maximum Headphone Power Dissipation
(1 kHz full-scale sine wave
into 16 ohm load) VA=5 . 0 V

Package Thermal Resistance

VA=2 . 4 V

Note:

6. Power Down Mode is defined as RST

= LO with all clocks and data lines held static.

I

VA_ HP

I

D

I

L

I

VA_ HP

I

D

I

L

I

VA_ HP

I

D

I

L

I

VA_ HP

I

D

I

L

PSRR - 0 - dB

θ

JA

t

sclkh

t

sclkl

t

sdh

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

1

10

1

TBD
TBD
TBD

2

20

2

TBD
TBD
TBD

29

120

-

23

100

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-75-°C/Watt

mA
mA
mA

µA
µA
µA

mA
mA
mA

µA
µA
µA

mW
mW

mW
mW

DS541PP1 7

CS44L10

DIGITAL CHARACTERISTICS (T

= 25° C; VL = 2.4V - 3.6V; GND=0V)

A

Parameters Symbol Min Typ Max Units

High-Level Input Voltage

Low-Level Input Voltage
Input Leakage Current

Input Capacitance

V

IH

V

IL

I

in

0.7 x VL - - V

--0.3 x VLV

--±10µA

-8-pF

SWITCHING CHARACTERISTICS- CONTROL PORT- TWO-WIRE FORMAT

(Note 7) (T

SCL Clock Frequency

RST Rising Edge to Start

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first clock pulse)

Clock Low time

Clock High Time

Setup Time for Repeated Start Condition

SDA Hold Time from SCL Falling (Note 8)

SDA Setup time to SCL Rising

Rise Time of SCL and SDA

Fall Time SCL and SDA

Setup Time for Stop Condition

Acknowledge Delay from SCL Falling (Note 9)

=25° C; VL = 2.4 V - 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VL, CL=30pF)

A

Parameter Symbol Min Max Unit

f

scl

t

irs

t

buf

t

hdst

t

low

t

high

t

sust

t

hdd

t

sud

trc, t

tfc, t

t

susp

t

ack

rc

fc

- 100 kHz

500 - ns

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs

0-µs

250 - ns

-1µs

- 300 ns

4.7 - µs

- (Note 10) ns

Note:

2

7. The Two-Wire Format is compatible with the I

8. Data must be held for sufficient time to bridge the transition time, t

C protocol.

, of SCL.

fc

9. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

5

---------------------

10. for Single-Speed Mode and for Double-Speed Mode.

256 Fs×

5

--------------------­128 F s×

8 DS541PP1

RST

SDA

SCL

t

irs

Stop S t a rt

t

buf

t

hdst

CS44L10

Repeated

Start

t

rd

t

high

t

hdst

t

fc

Stop

t

fd

t

susp

t

low

t

hdd

t

sud

t

ack

Figure 2. Control Port Timing - Two-Wire Format

t

sust

t

rc

DS541PP1 9

2. TYPICAL CONNECTION DIAGRAMS

2.4 to 5.0 V
Supply

100 µF

+

0.1 µ

F

12 13

VA_HPA

CS44L10

VA_HPB

2.4 to 5.0 V
Supply

2.4 to 5.0 V
Supply

1.0 µF

1.0 µF

Mode

Control

+

+

Digi tal

A

udio

Source

0.1 µF

5

0.1 µF

4

2

3

1

9

16

7

VL

VD

CS44L10

Cout
+

Cout
+

100 µH

100 µH

0.15
µF

0.15
µF

Ω

16

Headphone s

MCLK

LRCK

SCLK

SDIN

DEM

RST

8

DIF 0

HP_A

HP_B

11

220 µ F

14

220 µ F

GNDGNDGND

10

15

6

Figure 3. Typical CS44L10 Connection Diagram Stand-Alone Mode

10 DS541PP1

2.4 to 5.0 V
Supply

100 µF

CS44L10

+

0.1 µ

F

12 13

VA_HPA

VA_HPB

2.4to5.0V
Supply

2.4 to 5.0 V

Supply

1.0 µF

1.0 µ F

µC/

Mode

Control

+

+

Digital

A

udio

Source

7

0.1 µF

5

0.1 µF

4

2

3

1

9

16

8

VL

VD

MCLK

LRCK

SCLK

SDIN

SDA

RST

SCL

CS44L10

HP_A

HP_B

Cout

11

+

220 µ F

Cout

14

+

220 µF

100 µH

100 µH

0.15
µF

0.15
µF

Ω

16

Headphones

G

NDGNDGND

10

15

6

Figure 4. Typical CS44L10 Connection Diagram Control Port Mode

DS541PP1 11

CS44L10

3. REGISTER QUICK REFERENCE

Addr Function 7 6 5 4 3 2 1 0

2h Power and Muting

Control

default10100000

3h Channel A

Volume Control

default00000000

4h Channel B

Volume Control

default00000000

5h Tone Control BB3 BB2 BB1 BB0 TB3 TB2 TB1 TB0

default00000000

6h Mode Control 1 BBCF1 BBCF0 TBCF1 TBCF0 TC1 TC0 TC_EN LIM_EN

default00000000

7h Limiter Attack Rate ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0

default00010000

8h Limiter Release Rate RRATE7 RRATE6 RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0

default00100000

9h Volume and Mixing

Control

default00011001

Ah Mode Control2 MCLKDIV CLKDV1 CLKDV0 DBS FRQSFT1 FRQSFT0 DEM1 DEM0

default00000000

Bh Mode Control 3 DIF1 DIF0 A=B VCBYP CP_EN FREEZE Reserved Reserved

default00000000

Ch Revision Indicator Reserved Reserved Reserved Reserved REV3 REV2 REV1 REV0

default 0 0 0 0 Read Only Read Only Read Only Read Only

SZC1 SZC0 PDN FLT RUPBYP RDNBYP Reserved Reserved

VOLA7 VOLA6 VOLA5 VOLA4 VOLA3 VOLA2 VOLA1 VOLA0

VOLB7 VOLB6 VOLB5 VOLB4 VOLB3 VOLB2 VOLB1 VOLB0

Reserved Reserved RMP_SP1 RMP_SP0 ATAPI3 ATAPI2 ATAPI1 ATAPI0

Table 1. Register Quick Reference

12 DS541PP1

CS44L10

4. REGISTER DESCRIPTIONS

4.1 Power and Muting Control (address 02h)

76543210

SZC1 SZC0 PDN FLT RUPBYP RDNBYP Reserved Reserved

10100000

4.1.1 SOFT RAMP AND ZERO CROSS CONTROL (SZC)

Default = 10

00 - Immediate Change
01 - Zero Cross Control
10 - Ramped Control
11 - Reserved

Function:

Immediate Change

When Immediate Change is selected, all level changes will take effect immediately in one step.

Zero Cross Control

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
time-out period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a
zero crossing. The zero cross function is independently monitored and implemented for each channel.

Ramped Control

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp­ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.

Note: Ramped Control is not available in Double Speed Mode.

4.1.2 POWER DOWN (PDN)

Default = 1

0 - Disabled
1 - Enabled

Function:

The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation in Control Port mode can occur.

DS541PP1 13

4.1.3 FLOAT OUTPUT (FLT)

Default = 0

0 - Disabled
1 - Enabled

Function:

When enabled, this bit will cause the headphone output of the CS44L10 to float when in the power down
state (PDN=1). The float function can be used in single-ended applications to maintain the charge on the
DC-blocking capacitor during power transients. On power transitions, the output will quickly change to the
bias point, however, if the DC-blocking capacitor still has a full charge, as in short power cycles, the tran­sition will be very small, often inaudible. Refer to Section 6.4.

4.1.4 RAMP UP BYPASS (RUPBYP)

Default = 0

0 - Normal
1 - Bypass

Function:

When in normal mode, the duty cycle of the output PWM signal is increased at a rate determined by the
Ramp Speed variable (RMP_SPx). Normal mode is used in Single Ended applications to reduce pops in
the output caused by the DC-blocking capacitor. When the ramp up function is bypassed in Single Ended
applications, there will be an abrupt change in the output signal. Refer to Section 6.4.

CS44L10

4.1.5 RAMP DOWN BYPASS (RDNBYP)

Default = 0

0 - Disabled
1 - Enabled

Function:

When in normal mode, the duty cycle of the output PWM signal is decreased at a rate determined by the
Ramp Speed variable (RMP_SPx). Normal mode is used in Single Ended applications to reduce pops in
the output caused by the DC-blocking capacitor and changes in bias conditions. When the ramp down
function is bypassed in Single Ended applications, there will be an abrupt change in the output signal. Re­fer to Section 6.4.

4.2 Channel A Volume Control (address 03h) (VOLA)

4.3 Channel B Volume Control (address 04h) (VOLB)

76543210

VOLx7 VOLx6 VOLx5 VOLx4 VOLx3 VOLx2 VOLx1 VOLx0

00000000

Default = 0 dB (No attenuation)

Function:

The Volume Control registers allow independent control of the signal levels in 1 dB increments from +18
to -96 dB. Volume settings are decoded using a 2’s complement code, as shown in Table 2. The volume
changes are implemented as dictated by the Soft and Zero Cross bits. All volume settings less than -96 dB
are equivalent to muting the channel via the ATAPI bits (see Section 4.8.2).

14 DS541PP1

CS44L10

Note: All volume settings greater than +18 dB are interpreted as +18 dB.

Binary Code Decimal Value Volume Setting

00001010 12 +12 dB
00000111 7 +7 dB
00000000 0 0 dB
11000100 -60 -60 dB
10100110 -90 -90 dB

Table 2. Example Volume Settings

4.4 Tone Control (address 05h)

76543210

BB3 BB2 BB1 BB0 TB3 TB2 TB1 TB0

00000000

4.4.1 BASS BOOST LEVEL (BB)

Default = 0 dB (No Bass Boost)

Function:

The level of the shelving bass boost filter is set by Bass Boost Level. The level can be adjusted in 1 dB
increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 3. Levels above
+12 dB are interpreted as +12 dB.

Binary Code Decimal Value Boost Setting

0000 0 0 dB
0010 2 +2 dB
1010 6 +6 dB
1001 9 +9 dB
1100 12 +12 dB

Table 3. Example Bass Boost Settings

4.4.2 TREBLE BOOST LEVEL (TB)

Default = 0 dB (No Treble Boost)

Function:

The level of the shelving treble boost filter is set by Treble Boost Level. The level can be adjusted in 1 dB
increments from 0 to +12 dB of boost. Boost levels are decoded as shown in Table 4. Levels above
+12 dB are interpreted as +12 dB.

Note: Treble Boost is not available in Double Speed Mode.

Binary Code Decimal Value Boost Setting

0000 0 0 dB
0010 2 +2 dB
1010 6 +6 dB
1001 9 +9 dB
1100 12 +12 dB

Table 4. Example Treble Boost Settings

DS541PP1 15

CS44L10

4.5 Mode Control 1 (address 06h)

76543210

BBCF1 BBCF0 TBCF1 TBCF0 TC1 TC0 TC_EN LIM_EN

00000000

4.5.1 BASS BOOST CORNER FREQUENCY (BBCF)

Default = 00

00 - 50 Hz
01 - 100 Hz
10 - 200 Hz
11 - Reserved

Function:

The bass boost corner frequency is user-selectable. The corner frequency is a function of LRCK (sam­pling frequency), the DBS bit and the BBCF bits as shown in Table 5 and Table 6.

BBCF

Fs

00 50 Hz 25 Hz 12.5 Hz 8.33 Hz
01 100 Hz 50 Hz 25 Hz 16.7 Hz
10 200 Hz 100 Hz 50 Hz 33.3 Hz
11 Reserved Reserved Reserved Reserved

Table 5. Base Boost Corner Frequencies in Single Speed Mode

BBCF

Fs

00 50 Hz 25 Hz 12.5 Hz 8.33 Hz
01 100 Hz 50 Hz 25 Hz 16.7 Hz
10 200 Hz 100 Hz 50 Hz 33.3 Hz
11 Reserved Reserved Reserved Reserved

Table 6. Base Boost Corner Frequencies in Double Speed Mode

4.5.2 TREBLE BOOST CORNER FREQUENCY (TBCF)

Default = 00

00 - 2 kHz
01 - 4 kHz
10 - 7 kHz
11 - Reserved

48 kHz 24 kHz 12 kHz 8 kHz

96 kHz 48 kHz 24 kHz 16 kHz

LRCK in Single Speed Mode (DBS=0)

LRCK in Double Speed Mode (DBS=1)

Function:

The treble boost corner frequency is user selectable. The corner frequency is a function of LRCK (sam­pling frequency) and the TBCF bits as shown in Table 7.

Note: Treble Boost is not available in Double Speed Mode.

16 DS541PP1

CS44L10

TBCF

Fs

00 2 kHz 1 kHz 0.5 kHz 0.33 kHz
01 4 kHz 2 kHz 1 kHz 0.67 kHz
10 7 kHz 3.5 kHz 1.75 kHz 1.17 kHz

11 Reserved Reserved Reserved Reserved

Table 7. Treble Boost Corner Frequencies in Single Speed Mode

4.5.3 TONE CONTROL MODE (TC)

Default = 00

00 - All settings are taken from user registers
01 - 12 dB of Bass Boost at 100 Hz and 6 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
10 - 8 dB of Bass Boost at 100 Hz and 4 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)
11 - 4 dB of Bass Boost at 100 Hz and 2 dB of Treble Boost at 7 kHz (at LRCK = 48 kHz)

Function:

The Tone Control Mode bits determine how the Bass Boost and Treble Boost features are configured.
The user-defined settings from the Bass and Treble Boost Level and Corner Frequency registers are used
when these bits are set to ‘00’. Alternately, one of three pre-defined settings may be used (these settings
are a function of LRCK - refer to tables 5, 6, and 7).

Note: Treble boost is not available in Double Speed Mode.

48 kHz 24 kHz 12 kHz 8 kHz

LRCK in Single Speed Mode (DBS=0)

4.5.4 TONE CONTROL ENABLE (TC_EN)

Default = 0

0 - Disabled
1 - Enabled

Function:

The Bass Boost and Treble Boost features are active when this function is enabled.

4.5.5 PEAK SIGNAL LIMITER ENABLE (LIM_EN)

Default = 0

0 - Disabled
1 - Enabled

Function:

The CS44L10 will limit the maximum signal amplitude to prevent clipping when this function is enabled.
Peak Signal Limiting is performed by first decreasing the Bass and Treble Boost Levels. If the signal is
still clipping, the digital attenuation is increased. The attack rate is determined by the Limiter Attack Rate
register.

Once the signal has dropped below the clipping level, the attenuation is decreased back to the user se­lected level followed by the Bass Boost being increased back to the user selected level. The release rate
is determined by the Limiter Release Rate register.

Note: The A=B bit should be set to ‘1’ for optimal limiter performance.

DS541PP1 17

CS44L10

4.6 Limiter Attack Rate (address 07h) (ARATE)

76543210

ARATE7 ARATE6 ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0

00010000

Default = 10h - 2 LRCK’s per 1/8 dB

Function:

The limiter attack rate is user-selectable. The rate is a function of sampling frequency, As, and the value
in the Limiter Attack Rate register. Rates are calculated using the function RATE = 32/{value}, where {val­ue} is the decimal value in the Limiter Attack Rate register and RATE is in LRCK’s per 1/8 dB of change.

Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.

Use the LIM_EN bit to disable the limiter function (see "Peak Signal Limiter Enable (LIM_EN)").

Binary Code Decimal Value LRCK’s per 1/8 dB

00000001 1 32
00010100 20 1.6
00101000 40 0.8

00111100 60 0.53

01011010 90 0.356

Table 8. Example Limiter Attack Rate Settings

4.7 Limiter Release Rate (address 08h) (RRATE)

76543210

RRATE7 RRATE6 RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0

00100000

Default = 20h - 16 LRCK’s per 1/8 dB

Function:

The limiter release rate is user-selectable. The rate is a function of sampling frequency, Fs, and the value
in the Limiter Release Rate register. Rates are calculated using the function RATE = 512/{value}, where
{value} is the decimal value in the Limiter Release Rate register and RATE is in LRCK’s per 1/8 dB of
change.

Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.

Use the LIM_EN bit to disable the limiter function (see "Peak Signal Limiter Enable (LIM_EN)").

Binary Code Decimal Value LRCK’s per 1/8 dB

00000001 1 512
00010100 20 25
00101000 40 12

00111100 60 8

01011010 90 5

Table 9. Example Limiter Release Rate Settings

18 DS541PP1

CS44L10

4.8 Volume and Mixing Control (address 09h)

76543210

Reserved Reserved RMP_SP1 RMP_SP0 ATAPI3 ATAPI2 ATAPI1 ATAPI0

00001001

4.8.1 RAMP SPEED (RMP_SP)

Default = 01

00 - Ramp speed = approximately 0.1 seconds
01 - Ramp speed = approximately 0.2 seconds
10 - Ramp speed = approximately 0.3 seconds
11 - Ramp speed = approximately 0.65 seconds

Function:

This feature is used in Single Ended applications to reduce pops in the output caused by the DC-blocking
capacitor. When in control port mode, the Ramp Speed sets the time for the PWM signal to linearly ramp
up and down from the bias point (50% PWM duty cycle). Refer to Section 6.4.

4.8.2 ATAPI CHANNEL MIXING AND MUTING (ATAPI)

Default = 1001 - HP_A = L, HP_B = R (Stereo)

Function:

The CS44L10 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to
Table 10 and Figure 5 for additional information.

Note: All mixing functions occur prior to the digital volume control.

ATAPI3 ATAPI2 ATAPI1 ATAPI0 HP_A HP_B

0000 MUTE MUTE

0001 MUTE R
0010 MUTE L
0011 MUTE [(L+R)/2]
0100 R MUTE
0101 R R
0110 R L

0111 R [(L+R)/2]
1000 L MUTE
1001 L R
1010 L L
1011 L [(L+R)/2]
1100[(L+R)/2] MUTE

1101[(L+R)/2] R
1110[(L+R)/2] L
1111[(L+R)/2] [(L+R)/2]

Table 10. ATAPI Decode

DS541PP1 19

Left Channel

Audio Data

Right Channel

Audio Data

Σ

Channel A

Digital
Volume
Control
& Mute

Channel B

Digital

Volume

Control
& Mute

EQ

EQ

CS44L10

HP_A

HP_B

Figure 5. Dynamics Control Block Diagram

4.9 Mode Control 2 (address 0Ah)

76543210

MCLKDIV CLKDV1 CLKDV0 DBS FRQSFT1 FRQSFT0 DEM1 DEM0

00000000

4.9.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)

Default = 0

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK require­ments. Refer to Tables 11, 12, 13, 14, and Section 6.2.

4.9.2 CLOCK DIVIDE (CLKDIV)

Default = 00

Function:

MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to
Tables 11, 12, 13, 14, and Section 6.2.

20 DS541PP1

4.9.3 DOUBLE SPEED MODE (DBS)

Default = 0

0 - Single Speed
1 - Double Speed (DBS)

Function:

Single Speed supports 8kHz to 50 kHz sample rates and Double Speed supports 50 kHz to 96kHz sample
rates. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer
to Tables 11, 12, 13, 14, and Section 6.2.

Note: De-emphasis, ramp control, and treble control are not available in Double Speed Mode.

4.9.4 FREQUENCY SHIFT (FRQSFT)

Default = 00

Function:

MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to
Tables 11, 12, 13, 14, and Section 6.2.

CS44L10

DBS = 0

MCLKDIV = 0

LRCK

(kHz)

48 256 12.288 512 24.576 0 0 0 0

48 384 18.432 768 36.864 0 0 0 1 384

48 512 24.576 1024 49.152 0 0 1 0

44.1 256 11.2896 512 22.5792 0 0 0 0

44.1 384 16.9344 768 33.8688 0 0 0 1 352.8

44.1 512 22.5792 1024 45.1584 0 0 1 0

32 512 16.384 1024 32.768 0 1 0 0

32 768 24.576 1536 49.152 0 1 0 1 512

32 1024 32.768 2048 65.536 0 1 1 0

24 512 12.288 1024 24.576 0 1 0 0

24 768 18.432 1536 36.864 0 1 0 1 384

24 1024 24.576 2048 49.152 0 1 1 0

12 1024 12.288 2048 24.576 1 0 0 0

12 1536 18.432 3072 36.864 1 0 0 1 384

12 2048 24.576 4096 49.152 1 0 1 0

8 1536 12.288 3072 24.576 1 1 0 0

8 2304 18.432 4608 36.864 1 1 0 1 384

8 3072 24.576 6144 49.152 1 1 1 0

MCLK/

LRCK

MCLK

(MHz)

DBS = 0

MCLKDIV = 1

MCLK/

LRCK

MCLK
(MHz) FRQSFT1 FRQSFT0 CLKDIV1 CLKDIV0

PWM

Switching

Freq. (kHz)

Table 11. Single Speed Clock Modes - Control Port Mode

DS541PP1 21

CS44L10

PWM

LRCK

(kHz)

48 256 12.288

48 384 18.432 384

48 512 24.576

44.1 256 11.2896

44.1 384 16.9344 352.8

44.1 512 22.5792

32 1024 32.768 512

24 1024 24.576

12 2048 24.576

8 1536 12.288 384

8 2304 18.432

8 3072 24.576

MCLK/

LRCK

MCLK

(MHz)

Table 12. Single Speed Clock Modes - Stand-Alone Mode

Switching

Freq. (kHz)

DBS = 1

MCLKDIV = 0

DBS = 1

MCLKDIV = 1

PWM

LRCK

(kHz)

9612812.28825624.5760000

9619218.43238436.8640001384

9625624.57651249.1520010

MCLK/

LRCK

MCLK
(MHz)

MCLK/

LRCK

MCLK
(MHz) FRQSFT1 FRQSFT0 CLKDIV1 CLKDIV0

Switching

Freq. (kHz)

Table 13. Double Speed Clock Modes - Control Port Mode

PWM

LRCK

(kHz)

96 128 12.288

96 192 18.432

MCLK/

LRCK

MCLK
(MHz)

Switching

Freq. (kHz)

384

Table 14. Double Speed Clock Modes - Stand-Alone Mode

4.9.5 DE-EMPHASIS CONTROL (DEM)

Default = 00

00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz

Function:

Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re­sponse at 32, 44.1 or 48 kHz sample rates (see Figure 6).

Note: De-emphasis is not available in double speed mode.

22 DS541PP1

Gain

dB

0dB

-10dB

CS44L10

T1=50 µs

T2 = 15 µs

F1 F2

3.183 kHz 10.61 kHz

Frequency

Figure 6. De-Emphasis Curve

4.10 Mode Control 3 (address 0Bh)

76543210

DIF1 DIF0 A=B VCBYP CP_EN FREEZE HPSEN Reserved

00000000

4.10.1 DIGITAL INTERFACE FORMATS (DIF)

Default = 00

2

00 - I

S
01 - Right Justified, 16 bit
10 - Left Justified
11 - Right Justified, 24 bit

Function:

The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in figures 16 through 19.

4.10.2 CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)

Default = 0

0 - Disabled
1 - Enabled

Function:

The HP_A and HP_B volume levels are independently controlled by the A and the B Channel Volume
Control Bytes when this function is disabled. The volume on both HP_A and HP_B are determined by the
A Channel Volume Control Byte and the B Channel Byte is ignored when this function is enabled.

DS541PP1 23

4.10.3 VOLUME CONTROL BYPASS (VCBYP)

Default = 0

0 - Disabled
1 - Enabled

Function:

The digital volume control section is bypassed when this function is enabled. This disables the digital vol­ume control, muting, bass boost, treble boost, limiting, and ATAPI functions.

4.10.4 CONTROL PORT ENABLE (CP_EN)

Default = 0

0 - Disabled
1 - Enabled

Function:

This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can
be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg­isters and the pin definitions will conform to Control Port Mode. Refer to Section 6.5.2

CS44L10

.

4.10.5 FREEZE (FREEZE)

Default = 0

0 - Disabled
1 - Enabled

Function:

This function allows modifications to be made to the registers without the changes being taking effect until
the FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneous­ly, you will first enable the FREEZE Bit, then make all register changes, then Disable the FREEZE bit.

4.11 Revision Indicator (address 0Ch)[Read Only]

76543210

Reserved Reserved Reserved Reserved REV3 REV2 REV1 REV0

00000000

Default = none

0000 - Revision A
0001 - Revision B
0010 - Revision C
etc.

Function:

This read-only register indicates the revision level of the device.

24 DS541PP1

5. PIN DESCRIPTION

CS44L10

Serial Data SDIN RST

Left/Right Clock LRCK GND Headphone B Ground

Serial Clock SCLK HP_B Headphone B Output

Master Clock MCLK VA_HPB Headphone B Power

Digital Power VD VA_HPA Headphone A Power

Ground GND HP_A Headphone A Output

Interface Power VL GND Headphone A Ground

SCL/DIF0 SCL/DIF0 SDA/DEM SDA/DEM

SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

LRCK 2 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the

serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.

SCLK 3 Serial Clock (Input) - Serial clock for the serial audio interface.

MCLK 4 Master Clock (Input) - Clock source for the PWM modulator and digital filters. Table 11, 12, 13

and 14 illustrate several standard audio sample rates and required master clock frequencies.

VD 5 Digital Power (Input) - Positive power supply for the digital section. Refer to "Recommended

Operating Conditions" for appropriate voltages.

GND 6, 10

VL 7 Logic Power (Input) - Determines the required signal level for the digital input/output. Refer to

HP_A
HP_B

VA_HPA
VA_HPB

RST

Control Port
Definitions

SCL 8 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external

SDA 9 Serial Control Data (Input/Output) - SDA is a data I/O line in Two-Wire mode and requires an

Stand Alone
Definitions

DIF0 8 Digital Interface Format (Input) - The required relationship between the Left/Right clock, serial

Ground (Input) - Ground Reference.

& 15

"Recommended Operating Conditions" for appropriate voltages.

11

Headphone Outputs (Output) - PWM Headphone Outputs. An external LC filter should be

14

added to suppress high frequency switching noise. A DC blocking capacitor is also required.
Refer to Typical Connection Diagrams.

12

Headphone Amplifier Power (Input) - Positive power supply for the headphone amplifier.

13

Refer to "Recommended Operating Conditions" for appropriate voltages.

16 Reset (Input) - The device enters a low power mode and all internal registers are reset to their

default settings when low. The control port cannot be accessed when Reset is low. See Sec­tion 6.5

pull-up resistor to VL in Two-Wire mode.

external pull-up resistor to the logic interface voltage.

clock and serial data is defined by the Digital Interface Format and the options are detailed
below

DIF0 DESCRIPTION FIGURE

2

0

I

S, up to 24-bit data

1 Right Justified, 16-bit Data 19

1
2
3
4
5
6

7

8

16
15

14
13

12

11

10

Reset

9

18

Table 15. Digital Interface Format (Stand-Alone Mode)

DEM 9 De-emphasis Control (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter

response at 44.1 kHz sample rates. NOTE: De-emphasis is not available in Double or Quad
Speed Modes. When DEM is grounded, de-emphasis is disabled.

DS541PP1 25

CS44L10

6. APPLICATIONS

6.1 Grounding and Power Supply Decoupling

As with any switching converter, the CS44L10 re­quires careful attention to power supply and
grounding arrangements to optimize performance.
Figures 3 and 4 show the recommended power ar­rangement with VD, VA_HPx, and VL connected
to clean supplies. Decoupling capacitors should be
located as close to the device package as possible.
If desired, all supply pins may be connected to the
same supply, but a decoupling capacitor should still
be used on each supply pin.

6.2 Clock Modes

One of the characteristics of a PWM amplifier is
that the frequency content of out-of-band noise
generated by the modulator is dependent on the
PWM switching frequency. The systems designer
will specify the external filter based on this switch­ing frequency. The obvious implementation in a
digital PWM system is to directly lock the PWM
switching rate to the incoming data sample rate.
However, this would require a tuneable filter to at­tentuate the switching frequency across the range
of possible sample rates. To simplify the external
filter design and to accommodate sample rates
ranging from 8 kHz to 96 kHz the CS44L10 Con­troller uses several clock modes that keep the PWM
switching frequency in a small range.

In control port mode, for operation at a particular
sample rate the user selects register settings (refer
to Section 4.9 and Tables 11 and 13) based on their
MCLK and MCLK/LRCK parameters. When us-

ing Stand-Alone mode, refer to Tables 12 and 14
for available clock modes.

6.3 De-Emphasis

The CS44L10 includes on-chip digital de-empha­sis. Figure 6 shows the de-emphasis curve. The fre­quency response of the de-emphasis curve will
scale proportionally with changes in sample rate,
Fs.

The de-emphasis feature is included to accommo­date older audio recordings that utilize pre-empha­sis equalization as a means of noise reduction.

6.4 PWM PopGuard Transient Control

The CS44L10 uses PopGuard® technology to min­imize the effects of output transients during pow­er-up and power-down. This technique minimizes
the audio transients commonly produced by sin­gle-ended, single-supply converters when it is im­plemented with external DC-blocking capacitors
connected in series with the audio outputs.

When the device is initially powered-up, the HP_x
outputs are clamped to GND. Following a delay
each output begins to increase the PWM duty cycle
toward the quiescent voltage point. By a speed set
by the RMP_SP bit, the HP_x outputs will later
reach the bias point (50% PWM duty cycle), and
audio output begins. This gradual voltage ramping
allows time for the external DC-blocking capacitor
to charge to the quiescent voltage, minimizing the
power-up transient.

To prevent transients at power-down, the device
must first enter its power-down state. When this oc­curs, audio output ceases and the PWM duty cycle

26 DS541PP1

CS44L10

is decreased until the HP_x outputs reach GND.
The time required to reach GND is determined by
the RMP_SP bits. This allows the DC-blocking ca­pacitors to slowly discharge. Once this charge is
dissipated, the power to the device may be turned
off, and the system is ready for the next power-on.

To prevent an audio transient at the next power-on,
the DC-blocking capacitors must fully discharge
before turning off the power or exiting the pow­er-down state. If full discharge does not occur, a
transient will occur when the audio outputs are ini­tially clamped to GND. The time that the device
must remain in the power-down state is related to
the value of the DC-blocking capacitance and the
output load. For example, with a 220 µF capacitor
and a 16 ohm load on the headphone outputs, the
minimum power-down time will be approximately

0.4 seconds.

Note that ramp up and ramp down period can be set
to zero with the RUPBYP and RDNBYP bits re­spectively.

6.5 Recommended Power-up Sequence

6.5.1 Stand Alone Mode

1. Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the
control port is reset to its default settings and the
HP_x lines will remain low.

2. Bring RST high. The device will remain in a low
power state and will initiate the Stand-Alone pow­er-up sequence. The control port will be accessible
at this time.

6.5.2 Control Port Mode

1. Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the
control port is reset to its default settings and the
HP_x lines will remain low.

2. Bring RST
power state and will initiate the Stand-Alone pow­er-up sequence. The control port will be accessible
at this time.

3. On the CS44L10 the control port pins are shared
with stand-alone configuration pins. To enable the
control port, the user must set the CP_EN bit. This
is done by performing a Two-Wire or SPI write.
Once the control port is enabled, these pins are ded­icated to control port functionality.

To prevent audible artifacts the CP_EN bit (see
Section 4.10.4) should be set prior to the comple­tion of the Stand-Alone power-up sequence, ap­proximately 21mS. Writing this bit will halt the
Stand-Alone power-up sequence and initialize the
control port to its default settings. Note, the CP_EN
bit can be set any time after RST goes high; how­ever, setting this bit after the Stand-Alone pow­er-up sequence has completed can cause audible
artifacts.

high. The device will remain in a low

DS541PP1 27

CS44L10

7. CONTROL PORT INTERFACE

The control port is used to load all the internal set­tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob­lems, the control port pins should remain static if
no operation is required.

The CS44L10 has MAP auto increment capability,
enabled by the INCR bit in the MAP register,
which is the MSB. If INCR is 0, then the MAP will
stay constant for successive writes. If INCR is set
to 1, then MAP will auto increment after each byte
is written, allowing block reads or writes of succes­sive registers.

7.1 Two-Wire Format

SDA is a bidirectional data line. Data is clocked
into and out of the part by the clock, SCL, with a
clock to data relationship as shown in Figure 7. The
receiving device should send an acknowledge
(ACK) after each byte received. Pins AD0 and
AD1 forms the partial chip address and should be
tied to VL or GND as required. The upper 6 bits of
the 7- bit address field must be 001000.

Note: MCLK is required during all two-wire

transactions. The Two-Wire format is compatible
with the I

2

C protocol.

7.1.1 Writing in Two-Wire Format

To communicate with the CS44L10, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (low for a write). The next byte is the
Memory Address Pointer, MAP, which selects the
register to be read or written. The MAP is then fol­lowed by the data to be written. To write multiple
registers, continue providing a clock and data,
waiting for the CS44L10 to acknowledge between
each byte. To end the transaction, send a STOP
condition.

7.1.2 Reading in Two-Wire Format

To communicate with the CS44L10, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (high for a read). The contents of the reg­ister pointed to by the MAP will be output after the
chip address. To read multiple registers, continue
providing a clock and issue an ACK after each
byte. To end the transaction, send a STOP condi­tion.

Note 1

SDA

SCL

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

001000

Start

ADDR
AD0

Figure 7. Control Port Timing, Two-Wire Format

R/W

ACK

DATA
1-8

ACK

DATA
1-8

ACK

Stop

28 DS541PP1

CS44L10

7.2 Memory Address Pointer (MAP)

76543210

INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0

00000000

7.2.1 INCR (Auto Map Increment Enable)

Default = ‘0’
0 - Disabled
1 - Enabled

7.2.2 MAP3-0 (Memory Address Pointer)

Default = ‘0000’

DS541PP1 29

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

0 0.10.20.30.40.50.60.70.80.9 1

Frequ ency (norm alized t o Fs)

Amplitude (dB)

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

0.4 5 0.4 6 0.47 0. 48 0. 49 0. 5 0 .51 0.52 0.5 3 0.5 4 0.55

Frequency (norm alized to Fs)

Amplitude (dB)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (normalized to Fs)

Amplitude (dB)

0

-10

-20

-30

-40

-50

-60

Amplitude (dB)

-70

-80

-90

-100

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.5 4 0.56 0.58 0.6

Frequency (normalized to Fs)

Figure 8. Single Speed Stopband Rejection Figure 9. Single Speed Transition Band

0.5

0.4

0.3

0.2

0.1

0

-0.1

Ampl itude ( dB )

-0.2

-0.3

-0.4

-0.5

0 0. 05 0. 1 0 .15 0. 2 0. 25 0.3 0. 35 0. 4 0. 45 0. 5

Frequency (norm alized to Fs)

CS44L10

Figure 10. Single Speed Transition Band (Detail) Figure 11. Single Speed Passband Ripple

Figure 12. Double Speed Stopband Rejection Figure 13. Double Speed Transition Band

30 DS541PP1

0

-10

-20

-30

-40

-50

-60

Amplitude (dB)

-70

-80

-90

-100

0.4 0. 42 0.44 0.46 0. 48 0.5 0. 52 0.54 0.56 0.58 0.6

Frequency (normalized to Fs)

CS44L10

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

0.4 5 0. 46 0. 47 0. 48 0. 49 0. 5 0. 51 0. 52 0. 53 0 .5 4 0. 55

Frequency (normalized to Fs)

Amplitude (dB)

0.50

0.40

0.30

0.20

0.10

0.00

-0.10

-0.20

-0.30

-0.40

-0.50

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

F requency (nor maliz ed to F s )

Figure 14. Double Speed Transition Band (Detail) Figure 15. Double Speed Passband Ripple

LRCK

Left Channel

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5

+5 +4

Figure 16. Left Justified, up to 24-Bit Data

LRCK

SCLK

SDATA

0

LRCK

SCLK

SDATA +3 +2 +1

MSB

-1 -2 -3 -4 -5 +3 +2 +1

DS541PP1 31

Left Channel

23 22 21 20 19 18

32 clocks

Left Channel

+5 +4

LSB

65432107

MSB

-1 -2 -3 -4

23 22 21 20 19 18

Figure 17. Right Justified, 24-Bit Data

LSB

MSB

-1 -2 -3 -4

Figure 18. I2S, Up to 24-Bit Data

Right Channel

+3 +2 +1

+5 +4

Right Cha nnel

Right Channel

+5 +4

LSB

65432107

LSB

CS44L10

LRCK

SCLK

SDATA

Left Channel

15 14 13 12 11 10

32 clocks

6543210987

Figure 19. Right Justified, 16-Bit Data

8. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering So­ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Right Channel

15 14 13 12 11 10

6543210987

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

9.0 REFERENCES

1) “The I2C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com

32 DS541PP1

10. PACKAGE DIMENSIONS

16L TSSOP (4.4 mm BODY) PACKAGE DRAWING

N

CS44L10

1

23

TOP VIEW

D

E

e

2

b

SIDE VIEW

A2

A1

A

SEATING

PLANE

L

INCHES MILLIMETERS

1

E1

END VIEW

NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.043 -- -- 1.10
A1 0.002 0.004 0.006 0.05 -- 0.15
A2 0.03346 0.0354 0.037 0.85 0.90 0.95

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3
D 0.193 0.1969 0.201 4.90 5.00 5.10 1
E 0.248 0.2519 0.256 6.30 6.40 6.50

E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.065 BSC --

L 0.020 0.024 0.028 0.50 0.60 0.70

∝

0° 4° 8° 0° 4° 8°

∝

JEDEC #: MO-153

Controlling Dimension is Millimeters

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

DS541PP1 33