Datasheet CS4228A-KS, CDB4228A Datasheet (Cirrus Logic)

CS4228A

24-Bit, 96 kHz Surround Sound Codec

Features

l Six 24-bit D/A Converters

- 100 dB dynamic range

- -90 dB THD+N

l Two 24-bit A/D Converters

- 97 dB dynamic range

- -95 dB THD+N

l Sample rates up to 100 kHz
l Pop-free Digital Output Volume Controls

- 90.5 dB range, 0.5 dB resolution (182 levels)

- Variable smooth ramp rate, 0.125 dB steps

l Mute Control pin for off-chip muting circuits
l On-chip Anti-alias and Output Filters
l De-emphasis filters for 32, 44.1 and 48 kHz

I

SCL/CCLK SDA/CDIN VD

Description

The CS4228A codec provides two analog- to-digital and
six digital-to-analog delta- sigma converters, along with
volume controls, in a compact 28-pin SSOP device.
Combined with an IEC958 (SPDIF) receiver (like the
CS8414) and surround so und decoder (such as one of
the CS492x or CS 493xx families), it is ide al for use in
DVD player, A/V recei ver and car audio s ystems sup­porting multiple s tandards such as Dolby Digital AC-3,
AAC, DTS, Dolby ProLogic, THX, and MPEG.

A flexible serial audio interface al lows operation in Left
Justified, Right Justified, I

ORDERING INFORMATION

CS4228A-KS -10° to +70° C 28-pin SSOP
CDB4228A Evaluation Board

MUTECAD0/CS

RST

2

S, or One Line Data modes.

VA

VL

CONTROL PORT

LRCK
SCLK

SDIN1
SDIN2
SDIN3

SDOUT

SERIAL AUDIO

DATA INTERFACE

CLOCK MANAGER

MCLK

DIGITAL FILTERS

WITH DE-EMPHASIS

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

DIGITAL VOLUME

DIGITAL VOLUME

DIGITAL VOLUME

DIGITAL VOLUME

DIGITAL VOLUME

DIGITAL VOLUME

MUTE CONTROL

DIGITAL FILTERS

∆Σ

∆Σ

∆Σ

∆Σ

∆Σ

∆Σ

DAC #1

DAC #2

DAC #3

DAC #4

DAC #5

DAC #6

LEFT ADC

RIGHT ADC

DGND

DGND AGND

OUTPUT STAGE

ANALOG LOW PASS AND

AGND

FILT

FL
FR
SL

SR

CENTER

SUB

AINL+
AINL-

AINR+
AINR-

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright  Cirrus Logic, Inc. 2000

(All Rights Reserved)

DS511PP1

OCT ‘00

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS .................................. ....... ...... ....... ...... ....... ..... 4

ANALOG CHARACTERISTICS................................................................................................ 4

DIGITAL CHARACTERISTICS................................................................................................. 6

SWITCHING CHARACTERISTICS . ...... ....... ...... ............................................. ....... ..................6

SWITCHING CHARACTERISTICS - CONTROL PORT...........................................................8

ABSOLUTE MAXIMUM RATINGS .........................................................................................10

RECOMMENDED OPERATING CONDITIONS.....................................................................10

2. TYPICAL CONNECTION DIAGRAM ...................................................................................... 11

3. FUNCTIONAL DESCRIPTION ............................................................................................... 12

3.1 Overview ..........................................................................................................................12

3.2 Analog Inputs ...................................................................................................................12

3.2.1 Line Level Inputs .................................................................................................12

3.2.2 High Pass Filter ...................................................................................................12

3.3 Analog Outputs ................................................................................................................ 13

3.3.1 Line Level Outputs .............................................................................................. 13

3.3.2 Digital Volume Control ........................................................................................13

3.4 Mute Control .................................................................................................................... 14

3.5 Clock Generation ............................................................................................................. 14

3.5.1 Clock Source .......................................................................................................14

3.5.2 Synchronization ...................................................................................................14

3.6 Digital Interfaces .............................................................................................................. 14

3.6.1 Serial Audio Interface Signals .............................................................................14

3.6.2 Serial Audio Interface Formats ............................................................................15

3.7 Control Port Signals .........................................................................................................17

3.7.1 SPI Mode ............................................................................................................17

3.7.2 Two Wire Mode ................................................................................................... 17

3.8 Control Port Bit Definitions ...............................................................................................18

3.9 Power-up/Reset/Power Down Mode ................................................................................ 18

3.10 Power Supply, Layout, and Grounding .......................................................................... 19

4. REGISTER QUICK REFERENCE .......................................................................................... 20

5. REGISTER DESCRIPTIONS ..................................................................................................21

5.1 Memory Address Pointer (MAP) .....................................................................................21

5.2 CODEC Clock Mode ........................................................................................................ 21

5.3 Chip Control .....................................................................................................................22

5.4 ADC Control .....................................................................................................................22

5.5 DAC Mute1 Control ..........................................................................................................23

5.6 DAC Mute2 Control ..........................................................................................................23

CS4228A

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

Dolby, Pro Logic, and AC-3 are trademarks of Dolby Laboratories Licensing Corporation.
Preliminary product inf o rmation describes products whi ch are in production, but for which full character izat i on da t a is not yet available. Advance product infor -

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best effort s to ensure that the information
contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other ri g ht s
of third parties. This document is the pro perty of Cirrus Logi c, Inc. and i mplie s no licen se under patents, copyrights, tr ademarks, or trade secre ts. No part of
this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the pr i or writ ten consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or di sk may be pri nt ed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade­marks and service marks can be found at http://www.cirrus.com.

2 DS511PP1

5.7 DAC De-emphasis Control .............................................................................................. 24

5.8 Digital Volume Control .....................................................................................................24

5.9 Serial Port Mode .............................................................................................................. 25

5.10 Chip Status .................................................................................................................... 25

6. PIN DESCRIPTION ................................ ....... ............................................. ...... ....... ................ 26

7. PARAMETER DEFINITIONS .................................................................................................. 29

8. PACKAGE DIMENSIONS ...................................................................................................... 31

LIST OF FIGURES

Figure 1. Serial Audio Port Master Mode Timing .......................................................................... 7

Figure 2. Serial Audio Port Slave Mode Timing ............................................................................ 7

Figure 3. SPI Control Port Timing ................................................................................................. 8

Figure 4. Two Wire Control Port Timing ........................................................................................ 9

Figure 5. Recommended Connection Diagram ........................................................................... 11

Figure 6. Optional Line Input Buffer ............................................................................................12

Figure 7. Passive Output Filter with Mute ................................................................................... 13

Figure 8. Butterworth Output Filter with Mute ............................................................................. 13

Figure 9. I

Figure 10.Left Justified Serial Audio Formats .............................................................................. 16

Figure 11.Right Justified Serial Audio Formats ............................................................................ 16

Figure 12.One Line Data Serial Audio Format ............................................................................. 16

Figure 13.Control Port Timing, SPI Slave Mode Write ................................................................. 17

Figure 14.Control Port Timing, Two Wire Slave Mode Write ....................................................... 18

Figure 15.Control Port Timing, Two Wire Slave Mode Read ....................................................... 18

2

S Serial Audio Formats ............................................................................................. 15

CS4228A

LIST OF TABLES

Table 1. Serial Audio Port Input Channel Allocations ................................................................... 15

Table 2. Common Master Clock Frequencies.............................................................................. 27

DS511PP1 3

1. CHARACTERISTICS AND SPECIFICATIONS

CS4228A

ANALOG CHARACTERISTICS (Unless otherwise specified T

Scale Input Sine wave, 984.375 Hz; Fs = 48 kHz BRM, 96 kHz HRM; Measurement Bandwidth is 20 Hz to 20 kHz;
Local components as shown in Figure 5; SPI control mode, Left Justified serial format, MCLK = 256 x Fs for BRM,
128 x Fs for HRM, SCLK = 64 x Fs)

Base Rate Mode High Rate Mode

Parameter Symbol Min Typ Max Min Typ Max Units

Analog Input Characteristics

Dynamic Range, -60 dBFS input (A weighted)

Total Harmonic Distortion + Noise (Note 1)
Interchannel Isolation
Interchannel Gain Mismatch
Offset Error (with high pass filter)
Full Scale Input Voltage (Differential):
Gain Drift
Input Resistance
Input Capacitance

A/D Decimation Filter Characteristics

Passband (Note 3)
Passband Ripple
Stopband (Note 3)
Stopband Attenuation (Note 4)
Group Delay
Group Delay Variation vs. Frequency

High Pass Filter Characteristics

Frequency Response: -3 dB (Note 5)

Phase Deviation @ 20 Hz

Passband Ripple

- Minimum gain setting (0 dB) Differential Input; unless otherwise specified.
90 97

(unweighted)

(Note 2)

(Note 2)

-0.13 dB

(Note 5)

THD+N - -95 -88 - -95 -88 dB

5.24 5.66 6.09 5.24 5.66 6.09 Vp-p

10--10--kΩ

0.022 - 21.77 0.022 - 43.54 kHz

30.0 - 6114 72.41 - 6071 kHz
80--45--dB

t

gd

∆ t

gd

94

- 100 - - 100 - dB

- 0.1 - - 0.1 - dB

--0--0LSB

- 100 - - 100 - ppm/°C

--15--15pF

- - 0.01 - - 0.05 dB

-TBD- -TBD- s

--0--0µs

-

3.4

-

20

-10- -10-Degree

--0--0dB

= 25° C; VA = VD = VL = +5 V; Full

A

-

-

-

-

90 97

94

-

3.4

-

20

-

-

-

-

dB
dB

Hz
Hz

Notes: 1. Referenced to typical full-scale differential input voltage (2 Vrms), Tested with -1 dBFS input.

2. Filter response is not tested but is guaranteed by design.

3. Filter characteristics scale with output sample rate.

4. The analog modulator samples the input at 128 times Fs. For example, input the sample rate is

6.144 MHz for an output sample rate of 48 kHz. There is no rejection of input signals which are multiples
of the sampling frequency (n × 6.144 MHz ±20.0 kHz where n = 0,1,2,3...).

5. High Pass Filter characteristics are specified for Fs=44.1 KHz.

Specifications are subject to change without notice

4 DS511PP1

ANALOG CHARACTERISTICS (Continued)

Parameter Symbol Min Typ Max Min Typ Max Units

Analog Output Characteristics

Dynamic Range, -60 dBFS input (A weighted)

Total Harmonic Distortion + Noise
Interchannel Isolation
Interchannel Gain Mismatch
Offset Voltage
Full Scale Output Voltage
Gain Drift
Analog Output Load

Minimum Load Resistance:

Maximum Load Capacitance:

Combined Digital and Analog Filter Characteristics

Frequency Response 10 Hz to 20 kHz
Deviation from Linear Phase
Passband: to 0.01 dB corner (Notes 6, 7)
Passband Ripple (Note 7)
Stopband (Notes 6, 7)
Stopband Attenuation (Notes 5, 8)
Group Delay (Fs = Input Word Rate)

Analog Loopback Performance

Signal-to-noise Ratio
(CCIR-2K weighted, -20 dB FS input)

- Minimum Attenuation, 10 kΩ, 10 pF load; unless otherwise specified.

(unweighted)

THD+N - -90 -83 - -90 -83 dB

tgd - 27/Fs - - TBD - s

CCIR-2K - 90 - - 90 - dB

CS4228A

Base Rate Mode High Rate Mode

93-100

97

-95- -95- dB

- 0.1 - - 0.1 - dB

-10- -10- mV

3.42 3.7 3.98 3.42 3.7 3.98 Vp-p

- 100 - - 100 - ppm/°C

-

10

-

100

(Note 2)

±0.1 ±0.1 dB

- ±0.5 - - ±0.5 - Degrees

0 - 21.77 0 - 43.54 kHz

- - ±0.01 - - ±0.01 dB

26.2 - - 62.5 - - kHz
70--65--dB

-

-

-

-

93-100

97

-

10

-

100

-

-

-

-

dB
dB

kΩ

pF

Notes: 6. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz,

the 0.01 dB passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs.

7. Digital filter characteristics.

8. Measurement bandwidth is 10 Hz to 3 Fs.

Specifications are subject to change without notice

DS511PP1 5

ANALOG CHARACTERISTICS (Continued)

Power Supply

Power Supply Current Operating
VA = VD = VL = 5 V VA

Power Down: RST

low, Clocks running

Power Supply Rejection (1 kHz, 10 mV

Symbol Min Typ Max Min Typ Max Units

VL

VD

VA
VL

VD

)

rms

CS4228A

Base Rate Mode High Rate Mode

-

37

-

0.5

-

85

-

0.5

-

0.2

-

0.5

- 50 - 50 dB

42

2

99

1

0.5
1

-

37

-

0.5

-

85

-

0.5

-

0.2

-

0.5

42

2

99

1

0.5
1

mA
mA
mA

mA
mA
mA

DIGITAL CHARACTERISTICS Unless otherwise specified (T

5.25V)

Parameter Symbol Min Max Units

High-level Input Voltage
Low-level Input Voltage
High-level Output Voltage at VL = 5 V

= -2.0 mA

I

0

= -100 uA

I

0

VL = 2.5 V
= -2.0 mA

I

0

Low-level Output Voltage at VL = 5 V

= 2.0 mA

I

0

= 100 uA

I

0

VL = 2.5 V

= -2.0 mA

I

0

Input Leakage Current (Digital Inputs)
Output Leakage Current (High-Impe danc e Digi tal Outputs)

SWITCHING CHARACTERISTICS (T

= 25°C; VA = VD + 5V,VL = 2.375 to 5.25V, CL 30 pF)

A

Parameter Symbol Min Typ Max Units

Audio ADC's and DAC's Sample Rate BRM

HRM
MCLK Frequency
MCLK Duty Cycle BRM

MCLK =128, 384 Fs

MCLK = 256, 512 Fs

HRM

MCLK = 64, 192 Fs

MCLK = 128, 256 Fs

V

IH

V

IL

V

OH

V

OL

Fs 30

= 25 °C; VA = VD + 5V,VL = 2.375 to

A

0.7xVL - V

0.3xVL V

VL - 1.0
VL - 0.7

0.9 X VL

-

-

-

-

-

-

0.4

0.2

0.4

V
V

V

V
V

V

-10µA

-10µA

60

-

-

50

100

kHz
kHz

3.84 - 25.6 MHz

TBD

40

TBD

40

50
50

50
50

TBD

60

TBD

60

%
%

%
%

6 DS511PP1

SWITCHING CHARACTERISTICS (Continued)

Figure 1. Serial Audio Port Master Mode Timing

Parameter Symbol Min Typ Max Units

Low Time (Note 9)

RST
SCLK Falling Edge to SDOUT Output Valid (DSCK=0)
LRCK Edge to MSB Valid
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge

Master Mode

SCLK Falling to LRCK Edge
SCLK Duty Cycle

Slave Mode

SCLK Period
SCLK High Time
SCLK Low Time
SCLK rising to LRCK Edge (DSCK=0)
LRCK Edge to SCLK Rising (DSCK=0)

t

dpd

t

lrpd

t

t

t

mslr

t

sckw

t

sckh

t

sckl

t

lrckd

t

lrcks

ds
dh

CS4228A

1- -ms

-50ns

-20ns

-10ns

-30ns

+10 - ns

50 - %

--ns
50 - - ns
50 - - ns
25 - - ns
25 - - ns

Notes: 9. After powering up the CS4228A, RST

SCLK*
(output)

t

mslr

LRCK
(output)

SDOUT

should be held low until the power supplies and clocks are settled.

LRCK
(input)

SCLK*
(input)

SDIN1
SDIN2
SDIN3

SDOUT

*SCLK shown for DSCK = 0.
SCLK inverted for DSCK = 1.

t

lrckd

t

lrpd

t

lrcks

t

sckh

t

t

dh

ds

MSB

t

sckw

t

sckl

t

dpd

MSB-1

Figure 2. Serial Audio Port Slave Mode Timing

DS511PP1 7

CS4228A

SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25° C, VA = VD = +5 V,

VL =2.375 to 5.25 V; Inputs: logic 0 = DGND, logic 1 = VL, C

Parameter Symbol Min Max Units

SPI Mode

(SDOUT > 47 kΩ to GND)
CCLK Clock Frequency
CS

High Time Between Transmissions

CS

Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time (Note 10)
Rise Time of CCLK and CDIN (Note 11)
Fall Time of CCLK and CDIN (Note 11)

Notes: 10. Data must be held for sufficient time to bridge the transition time of CCLK.

11. For F

SCK

< 1 MHz

= 30 pF)

L

f
t
t

t
t
t

t

sck
csh
css

scl
sch
dsu

dh

t

r2

t

f2

-6MHz

1.0 µs
20 ns
66 ns
66 ns
40 ns
15 ns

100 ns
100 ns

CS

CCLK

CDIN

t

t

css

r2

t

t

scl

t

t

f2

dsu

sch

t

dh

Figure 3. SPI Control Port Timing

t

csh

8 DS511PP1

CS4228A

SWITCHING CHARACTERISTICS - CONTROL PORT (T

VL=2.375 to 5.25 V; Inputs: logic 0 = DGND, logic 1 = VL, C

= 30 pF)

L

= 25° C; VA = VD = +5 V,

A

Parameter Symbol Min Max Units

Two Wire Mode

SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 12)
SDA Setup Time to SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition

(SDOUT < 47 kΩ to ground)

f
t

t

hdst

t

low

t

high

t

sust

t

hdd

t

sud

t

susp

scl
buf

t
t

-100kHz

4.7 µs

4.0 µs

4.7 µs

4.0 µs

4.7 µs
0 µs

250 ns

r
f

4.7 µs

Notes: 12. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

1 µs

300 ns

SDA

SCL

Stop Start

t

buf

t

hdst

t

t

high

low

t

hdd

t

sud

Figure 4. Two Wire Control Port Timing

Repeated

Start

t

sust

t

hdst

Stop

t

f

t

r

t

susp

DS511PP1 9

CS4228A

ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to 0 V.)

Parameter Symbol Min Typ Max Units

Power Supplies Digital

Analog

Interface
Input Current (Note 13)
Analog Input Voltage (Note 14)
Digital Input Voltage Input Pins

Bidirectional Pins

(Notes 14 and 15)
Ambient Temperature (Power Applied)
Storage Temperature

Notes: 13. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause

SCR latch-up.

14. The maximum over or under voltage is limited by the input current.

15. Bidirectional pins configured as inputs.

VD

VA
VL

-0.3

-0.3

-0.3

--±10mA

-0.7 - VA + 0.7 V

-0.7

-0.7

-55 - +125 °C

-65 - +150 °C

-

-

-

-

-

6.0

6.0

6.0

VL + 2.5
VL + 0.7

V
V
V

V
V
V

Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V, all voltages with respect

to 0 V.)

Parameter Symbol Min Typ Max Units

Power Supplies Digital

Analog

Interface

Operating Ambient Temperature

VD

VA
VL

T

A

4.75

4.75

2.375

-10 25 70 °C

5.0

5.0

-

5.25

5.25

5.25

V
V
V

10 DS511PP1

2. TYPICAL CONNECTION DIAGRAM

CS4228A

+5V
Supply

Ferrite Bead

1µF 0.1µF

+

Ferrite Bead

VL

+5V

1

µF0.1

µ

+

F

Supply

µ

F

0.1

+

Ferrite Bead

µ

F

1

+2.5V to +5V
Supply

9821

VA VD

µ

F

22

Ω

150

+

19

AINL-

2.2 nf

0.1µF

0.1µF

+

20

16

17

18

AINL+

AINR­AINR+

FILT

CS4228A

+

100µF

22µF

Ω

150

+

2.2 nf

From Analog Input St age

100

1

VL

+

µ

F

µ

F

0.1

µ

F

VL

2.2 K*

Microcontroller

SDA/CDIN

12

SCL/CCLK

11

AD0/CS

13

RST

14

VL

FL

FR

SL

SR

CENTER

SUB

MUTEC

LRCK

SCLK

SDIN1

SDIN2

SDIN3

SDOUT

23

24

25

26

27

28

15

3

2

1
4

ANALOG
FILTER

ANALOG
FILTER

ANALOG
FILTER

ANALOG
FILTER

ANALOG
FILTER

ANALOG
FILTER

VL

Ω

50

6

50

Ω

5

50

Ω

Ω

Digital Audio

50

Front Left

Front Right

Surround Left

Surround Right

Center

Subwoofer

Peripheral

50

Ω

50

Ω

or

DSP

All unused inputs
should be tied to 0V.

AGND DGND

MCLK

10722

33 K*

* Required for 2-wire

mode only

External Clock Input

Note : MCLK Logic High is VL
Note: AGND and DGND pins should
both be tied t o a c om m on ground plane.

Figure 5. Recommended Connection Diagram

DS511PP1 11

CS4228A

3. FUNCTIONAL DESCRIPTION

3.1 Overview

The CS4228A is a 24-bit audio codec comprised of
2 analog-to-digital converters (ADC) and 6 digital­to-analog converters (DAC), all implemented us­ing single-bit delta-sigma techniques. Other func­tions integrated with the codec include independent
digital volume controls for each DAC, digital DAC
de-emphasis filters, ADC high-pass filters, an on­chip voltage reference, and a flexible serial audio
interface. All functions are configured through a
serial control port operable in SPI mode and in two
wire mode. Figure 5 shows the recommended con­nections for the CS4228A.

3.2 Analog Inputs

3.2.1 Line Level Inputs

AINR+, AINR-, AINL+, and AINL- are the line
level analog inputs (See Figure 5). These pins are
internally biased to a DC operating voltage of ap­proximately 2.3 VDC. AC coupling the inputs pre­serves this bias and minimizes signal distortion.
Figure 5 shows operation with a single-ended input
source. This source may be supplied to either the

positive or negative input as long as the unused in­put is connected to ground through capacitors as
shown. When operated with single-ended inputs,
distortion will increase at input levels higher than

-1 dBFS. Figure 6 shows an example of a differen­tial input circuit.

Muting of the stereo ADC is possible through the
ADC Control Byte.

The ADC output data is in 2’s complement binary
format. For inputs above positive full scale or be­low negative full scale, the ADC will output
7FFFFFH or 800000H, respectively.

3.2.2 High Pass Filter

Digital high pass filters in the signal path after the
ADCs remove any DC offsts present on the analog
inputs. The high pass filter helps prevent audible
"clicks" when switching between audio sources
downstream from the ADCs. The high pass filter
response, given in “High Pass Filter Characteristics
(Note 2)”, scales linearly with sample rate. Thus,
for High Rate Mode, the -3 dB frequency at a 96
kHz sample rate will be equal to 96/44.1 times that
at a sample rate of 44.1 kHz.

4.7 k

10µF

10 k

signal

12 DS511PP1

VA

+

10 k

~ 8.5 k

-

+

10 k

10 k

­+

+

10

Figure 6. Optional Line Input Buffer

0.1µF

µ

f

150

AIN -

2.2 nf

150

AIN +

CS4228A

The high pass filters can be disabled by setting the
HPF bit in the ADC Control register. When assert­ed, any DC present at the analog inputs will be rep­resented in the ADC outputs. The high pass filter

may also be “frozen” using the HPFZ bit in the
ADC Control register. In this condition, it will re­member the DC offset present at the ADC inputs at
the moment the HPFZ bit was asserted, and will
continue to remove this DC level from the ADC
outputs. This is useful in cases where it is desirable
to eliminate a fixed DC offset while still maintain­ing full frequency response down to DC.

3.3 Analog Outputs

3.3.1 Line Level Outputs

The CS4228A contains on-chip buffer amplifiers
capable of producing line level outputs. These am­plifiers are biased to a quiescent DC level of ap­proximately 2.3 V. This bias, as well as variations
in offset voltage, are removed using off-chip AC
load coupling.

3.3.2 Digital Volume Control

Each DAC’s output level is controlled via the Dig­ital Volume Control register operating over the
range of 0 to 90.5 dB attenuation with 0.5 dB reso­lution. Volume control changes do not occur in­stantaneously. Instead they ramp in increments of

0.125 dB at a variable rate controlled by the
RMP1:0 bits in the Digital Volume Control regis­ter.

MUTEC

AOUT

C=142µF

F

s

10 k

10 k

µ

22

F

+

560

100 k

2SC2878

or

2SC3326

MUN2IIIT1

MUTEDRV

Line Out

C

2.2 k

The delta-sigma conversion process produces high
frequency noise beyond the audio passband, most
of which is removed by the on-chip analog filters.
The remaining out-of-band noise can be attenuated
using an off-chip low pass filter. For most applica­tions, a simple passive filter as show in Figure 7 can
be used. Note that this circuit also serves to block
the DC present at the outputs. Figure 8 gives an ex­ample of a filter which can be used in applications
where greater out of band attenuation is desired.
The 2-pole Butterworth filter has a -3 dB frequency
of 50 kHz, a passband attenuation of 0.1 dB at
20 kHz providing optimal out-of-band filtering for
sample rates from 44.1 kHz to 96 kHz. The filter
has and a gain of 1.56 providing a 2 Vrms output
signal.

Figure 7. Passive Output Filter with Mute

1 nf

3.57 k

10 µf

3.57 k

+

GND

3.57 k

A

OUT

_

5

7

6

1 nf

+

MC33078

2 k

100 pf

2-Pole Butterworth Filter

+

10µf

MUTE

MUTE DRV

Figure 8. Butterworth Output Filter with Mute

2 VRMS

Line
Out

DS511PP1 13

CS4228A

Each output can be independently muted via mute
control bits MUT6-1 in the DAC Mute1 Control
register. When asserted, MUT attenuates the corre­sponding DAC to its maximum value (90.5 dB).
When MUT is deasserted, the corresponding DAC
returns to the attenuation level set in the Digital
Volume Control register. The attenuation is
ramped up and down at the rate specified by the
RMP1:0 bits.

To achieve complete digital attenuation of an in­coming signal, Hard Mute controls are provided.
When asserted, Hard Mute will send zero data to a
corresponding pair of DACs. Hard Mute is not
ramped, so it should only be asserted after setting
the two corresponding MUT bits to prevent high
frequency transients from appearing on the DAC
outputs. Hard Mute is controlled by the
HMUTE56/34/12 bits in the DAC Mute2 Control
register.

3.4 Mute Control

The Mute Control pin is typically connected to an
external mute control circuit as shown in Figure 7
and Figure 8. The Mute Control pin is asserted dur­ing power up, power down, and when serial port
clock errors are present. The pin can also be con­trolled by the user via the control port, or automat­ically asserted when zero data is present on all six
DAC inputs. To prevent large transients on the out­put, it is desirable to mute the DAC outputs before
the Mute Control pin is asserted. Please see the
MUTEC pin in the Pin Descriptions section for
more information.

3.5 Clock Generation

The master clock, MCLK, is supplied to the
CS4228A from an external clock source. If MCLK
stops for 10 µs, the CS4228A will enter Power

Down Mode in which the supply current is reduced
as specified under “Power Supply”. In all modes it
is required that the number of MCLK periods per
SCLK and LRCK period be constant.

3.5.1 Clock Source

The CS4228A internal logic requires an external
master clock, MCLK, that operates at multiples of
the sample rate frequency, Fs. The MCLK/Fs ratio
is determined by the CI1:0 bits in the CODEC
Clock Mode register.

3.5.2 Synchronization

The serial port is internally synchronized with
MCLK. If from one LRCK cycle to the next, the
number of MCLK cycles per LRCK cycle changes
by more than 32, the CS4228A will undergo an in­ternal reset of its data paths in an attempt to resyn­chronize. Consequently, it is advisable to mute the
DACs and clear the DIGPDN bit when changing
from one clock source to another to avoid the out­put of undesirable audio signals as the device re­synchronizes. It is adviseable to ensure that MCLK
complies with the Switching Characteristics at all
times when switching clock sources without reset­ting the part.

3.6 Digital Interfaces

3.6.1 Serial Audio Interface Signals

The serial audio data is presented in 2's comple­ment binary form with the MSB first in all formats.
The serial interface clock, SCLK, is used for both
transmitting and receiving audio data. SCLK can
be generated by the CS4228A (master mode) or it
can be input from an external source (slave mode).
Mode selection is made with the DMS1:0 bits in
the Serial Port Mode register. The number of
SCLK cycles in one sample period can be set using
the DCK1:0 bits as detailed in the Serial Port Mode
register.

The Left/Right clock (LRCK) is used to indicate
left and right data frames and the start of a new
sample period. It may be an output of the CS4228A
(master mode), or it may be generated by an exter­nal source (slave mode). The frequency of LRCK is
the same as the system sample rate, Fs.

14 DS511PP1

CS4228A

SDIN1, SDIN2, and SDIN3 are the data input pins.
SDOUT, the data output pin, carries data from the
two 24-bit ADC’s. The serial audio port may also
be operated in One Line Data Mode in which all 6
channels of DAC data is input on SDIN1 and the
stereo ADC data is output on SDOUT. Table 1 out­lines the serial port input to DAC channel alloca­tions.

DAC Inputs

SDIN1 left channel

right channel

single line

SDIN2 left channel

right channel

SDIN3 left channel

right channel

Table 1. Serial Audio Port Input Channel Allocations

DAC #1
DAC #2
All 6 DAC channels (BRM)

DAC #3
DAC #4

DAC #5
DAC #6

3.6.2 Serial Audio Interface Formats

The digital audio port supports 6 formats, shown in
Figures 9, 10, 11 and 12. These formats are selected
using the DDF2:0 bits in the Serial Port Mode reg­ister.

In One Line Data Mode, all 6 DAC channels are in­put on SDIN1. One Line Data Mode is only avail­able in BRM. See Figure 12 for channel
allocations.

LRCK

SCLK

SDIN1/2/3
SDOUT

Left Channel

+3 +2 +1

MSB

-1 -2 -3 -4 -5

+5 +4

LSB

I2S Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
16 32, 48, 64, 128 Fs

32, 64 Fs

18 to 24 48, 64, 128 Fs

64 Fs

BRM, 48 Fs available in slave mode only
HRM

BRM, 48 Fs available in slave mode only
HRM

Figure 9. I2S Serial Audio Formats

MSB

-1 -2 -3 -4

Right Channel

+3 +2 +1

+5 +4

LSB

DS511PP1 15

CS4228A

LRCK

SCLK

SDIN1/2/3
SDOUT

LRCK

SCLK

SDIN1/2/3
SDOUT

Left Channel

+3 +2 +1

MSB

-1 -2 -3 -4 -5

+5 +4

LSB

Left Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
16 32, 48, 64, 128 Fs

32, 64 Fs

18 to 24 48, 64, 128 Fs

64 Fs

BRM, 48 Fs av ailable in slave mode onl y
HRM

BRM, 48 Fs av ailable in slave mode onl y
HRM

Figure 10. Left Justified Serial Audio Formats

Left Channel

15 14 13 12 11 10

6543210987

MSB

-1 -2 -3 -4

Right Channel

+3 +2 +1

+5 +4

Right Channel

15 14 13 12 11 10

LSB

6543210987

Right Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
16 32, 48, 64, 128 Fs

32, 64 Fs

20 48, 64, 128 Fs

64 Fs

24 48, 64, 128 Fs

64 Fs

BRM, 48 Fs available in slave mode only
HRM

BRM, 48 Fs available in slave mode only
HRM

BRM, 48 Fs available in slave mode only
HRM

Figure 11. Right Justified Serial Audio Formats

64 clks 64 clks

LRCK

SCLK

SDIN1/2/3

DAC1 DAC3 DAC5 DAC2 DAC4 DAC6

20 clks

SDOUT

ADCL ADCR

20 clks

One Line Data Mode, Data Valid on Rising Edge of SCLK
Bits/Sample SCLK Rate(s) Notes
20 128 Fs 6 inputs, 2 outputs, BRM only

Left Channel Right Channel

LSBMSB

LSBMSB LSBMSB LSBMSB LS BMSB LSBMSB MSB

20 clks

20 clks 20 cl ks

20 clks

20 clks 20 clks

Figure 12. One Line Data Serial Audio Format

16 DS511PP1

CS4228A

3.7 Control Port Signals

Internal registers are accessed through the control
port. The control port may be operated asynchro­nously with respect to audio sample rate. However,
to avoid potential interference problems, the con­trol port pins should remain static if no register ac­cess is required.

The control port has 2 operating modes: SPI mode
and two wire mode. In both modes the CS4228A
operates as a slave device. Mode selection is deter­mined by the state of the SDOUT pin when RST
transitions from low to high: high for SPI, low for
two wire mode. SDOUT is internally pulled high to
VL. A resistive load from SDOUT to GND of less
than 47 kΩ will enable two wire mod e after a ha rd­ware reset.

3.7.1 SPI Mode

In SPI mode, CS is the CS4228A chip select signal,
CCLK is the control port bit clock input, and CDIN
is the input data line. There is no data output line,
therefore all registers are write-only in SPI mode.
Data is clocked in on the rising edge of CCLK.

Figure 13 shows the operation of the control port in
SPI mode. The first 7 bits on CDIN, after CS goes
low, form the chip address (0010000). The eighth
bit is a read/write indicator (R/W), which should al­ways be low to write. The next 8 bits set the Mem­ory Address Pointer (MAP) which is the address of
the register that is to be written. The following

bytes contain the data which will be placed into the
registers designated by the MAP.

The CS4228A has a MAP auto increment capabili­ty, enabled by the INCR bit in the MAP registe r. If
INCR is zero, then the MAP will stay constant for
successive writes. If INCR is 1, then the MAP will
increment after each byte is written, allowing block
reads or writes of successive registers.

3.7.2 Two Wire Mode

In two wire mode, SDA is a bidirectional data line.
Data is clocked into and out of the port by the SCL
clock. The signal timing is shown in Figures 14
and 15. A Start condition is defined as a falling
transition of SDA while the clock is high. A Stop
condition is a rising transition while the clock is
high. All other transitions of SDA occur while the
clock is low.

The first byte sent to the CS4228A after a Start con­dition consists of a 7 bit chip address field and a
R/W bit (high for a read, low for a write). The AD0
pin determines the LSB of the chip address field.
The upper 6 bits of the address field must be 00100
and the seventh bit must match AD0. If the opera­tion is to be a write, the second byte is the Memory
Address Ponter (MAP), which selects the register
to be written. The succeeding byte(s) are data. If
the operation is to be a read, the second byte is sent
from the chip to the controller and contains the con­tents of the register pointed to by the current value
of the MAP.

CS

(input)

8 9 10 114 5 6 7 0 1 2 3 16 17 18 19 20 21 22

CCLK

(input)

CDIN

(input)

DS511PP1 17

CHIP ADDRESS (WRITE) MAP BYTE

INCR

0 0 1 0 0 0 0 0

MSB

Figure 13. Control Port Timing, SPI Slave Mode Write

6 5 4 3 2 1 0

R/W

12 13 14 15

DATA DATA +n

7 6 5 4 3 2 1 0

23

7 6 5 4 3 2 1 0

CS4228A

4 5 6 7 24 25

INCR

6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0

ACK

SCL

SDA

0 1 2 3 8 9 12 16 17 18 1910 11 13 14 15 27 28

CHIP ADDRESS (WRITE) MAP BYTE DATA

0 0 1 0 0 AD1 AD0 0

START

Figure 14. Control Port Timing, Two Wire Slave Mode Write

168 9 12 13 14 154 5 6 7 0 1 20 2 1 2 2 23 2 4

SCL

SDA

2 3 10 11 17 1 8 1 9 25

CHIP ADDRESS (W RITE)

0 0 1 0 0 AD 1 A D0 0

START

MAP BYTE

INCR 6 5 4 3 2 1 0

ACK

Figure 15. Control Port Timing, Two Wire Slave Mode Read

Since the read operation can not set the MAP, an
aborted write operation is used as a preamble. As
shown in Figure 15, the write operation is aborted
after the acknowledge for the MAP byte by sending
a stop condition. The following pseudocode illus­trates an aborted write operation followed by a read
operation.

Send start condition.
Send 001000x0 chip address & write operation.
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 001000x1 chip address & read operation.
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.

26

ACK

DATA +n

DATA +1

ACKACKACK

DATA + n

STOP

ACK

CHIP ADDRESS (READ)

0 0 1 0 0 AD 1 A D 0 1

START

DATA +1

26 27 28

DATA

7 0 7 0 7 0

ACK

Setting the auto increment bit in the MAP allows
successive reads or writes of consecutive registers.
Each byte is separated by an acknowledge bit.

3.8 Control Port Bit Definitions

All registers are read/write, except the Chip Status
register which is read-only. For more detailed in­formation, see the bit definition tables.

3.9 Power-up/Reset/Power Down Mode

Upon power up, the user should hold RST = 0 until
the power supplies and clocks stabilize. In this
state, the control registers a re reset t o their default
settings, and the device remains in a low power
mode in which the control port is inactive. The part
may be held in a low power reset state by clearing
the DIGPDN bit in the Chip Control register. In this
state, the digital portions of the CODEC are in re­set, but the control port is active and the desired
register settings can be loaded. Normal operation is
achieved by setting the DIGPDN bit to 1, at which
time the CODEC powers up and normal operation
begins.

STOP

NO

ACK

STOP

18 DS511PP1

CS4228A

The CS4228A will enter a stand-by mode if the
master clock source stops for approximately 10 µs
or if the number of MCLK cycles per LRCK period
varies by more than 32. Should this occur, the con­trol registers retain their settings.

The CS4228A will mute the analog outputs, assert
the MUTEC pin and enter the Power Down Mode
if the supply drops below approximately 4 volts.

3.10 Power Supply, Layout, and Grounding

The CS4228A requires careful attention to power
supply and grounding details. VA is normally sup­plied from the system 5 VDC analog supply. VD is
from a 5 VDC digital supply, or for optimum ADC
performance, connect VD through a diode to a
+5 V supply to lower the digital core voltage. VL
should be from the supply used for the devices dig­itally interfacing with the CS4228A. The power up
sequence of these three supply pins is not impor­tant.

AGND and DGND pins should both be tied to a
solid ground plane surrounding the CS4228A. The

system analog and digital ground planes should not
be separated under normal circumstances. A solid
ground plane underneath the part is recommended.

Decoupling capacitors should be mounted and
routed in such a way as to minimize the circuit path
length from the CS4228A supply pin or FILT pin,
through the capacitor, and back to the applicable
CS4228A AGND or DGND pin. The small value
ceramic capacitors should be closest to the part. In
some cases, ferrite beads in the VL, VD and VA
supply lines, and low-value resistances (~ 50 Ω) in
series with the LRCK, SCLK, SDIN and SDOUT
lines can help reduce coupling of digital signals
into the analog portions of the CS4228A.

The both capacitors on the FILT pin should be as
close to the CS4228A as possible. Any noise that
couples onto the FILT pin will couple directly onto
all of the analog outputs. Please see the CDB4228
evaluation board data sheet for recommended lay­out of the decoupling components.

DS511PP1 19

CS4228A

4. REGISTER QUICK REFERENCE

Addr Function 7 6 5 4 3 2 1 0

MAP Memory Address

Pointer

0x01 CODEC Clock Mode HRM Reserved

default=0x04

0x02 Chip Control DIGPDN

default=0x00

0x03 ADC Control MUTL MUTR HPF HPFZ Reserved Reserved Reserved Reserved

default=0x00

0x04 DAC Mute1 Control MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 RMP1 RMP0

default=0xFC

0x05 DAC Mute2 Control MUTEC MUTCZ Reserved Reserved HMUTE56 HMUTE34 HMUTE12 Reserved

default=0x80

0x06 DAC De-emphasis

Control

default=0x80 1 0 0 0 0 0 0 0

0x07 DAC 1 Volume Cntrl Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0

default=0x00

0x08 DAC 2 Volume Cntrl Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0

default=0x00

0x09 DAC 3 Volume Cntrl Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0

default=0x00

0x0A DAC 4 Volume Cntrl Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0

default=0x00

0x0B DAC 5 Volume Cntrl Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0

default=0x00

0x0C DAC 6 Volume Cntrl Vol7 Vol6 Vol5 Vol4 Vol3 Vol2 Vol1 Vol0

default=0x00

0x0D

Serial Port Mode

default=0x84

0x0E

Chip Status

read only

INCR Reserved Reserved MAP4 MAP3 MAP2 MAP1 MAP0

1000 0 0 0 1

Reserved

00

Reserved Reserved ADCPDN DACPDN56 DACPDN34 DACPDN12 Reserved

1000 0 0 0 0

0000 0 0 0 0

1111 1 1 0 0

1000 0 0 0 0

DEMS1 DEMS0 DEM6 DEM5 DEM4 DEM3 DEM2 DEM1

0000 0 0 0 0

0000 0 0 0 0

0000 0 0 0 0

0000 0 0 0 0

0000 0 0 0 0

0000 0 0 0 0

DCK1 DCK0 DMS1 DMS0 Reserved DDF2 DDF1 DDF0

1000 0 1 0 0

CLKERR ADCOVL Reserved Reserved Reserved Reserved Reserved Reserved

XX00 0 0 0 0

0

Reserved CI1 CI0 Reserved Reserved

00 1 00

7654 3 2 1 0

20 DS511PP1

CS4228A

5. REGISTER DESCRIPTIONS

All registers are read/write except for Chip Status, which is read only. See the following bit definition tables for bit
assignment information. The default state of each bit after a power-up sequence or reset is listed in the tables un-

derneath each bit’s label. Default values are also marked in the text with an asterisk.

5.1 Memory Address Pointer (MAP)

Not a register

76543210

INCR RESERVED MAP4 MAP3 MAP2 MAP1 MAP0

10000001

INCR memory address pointer auto increment control

0 - MAP is not incremented automatically.
*1 - internal MAP is automatically incremented after each read or write.

MAP4:0 Memory address pointer (MAP). Sets the register address that will be read or written by the con-

trol port.

5.2 CODEC Clock Mode

Address 0x01

76543210

HRM RESERVED CI1 CI0 RESERVED

00000100

HRM Sets the sample rate mode for the ADCs and DACs

*0 - Base Rate Mode (BRM) supports sample rates up to 50 kHz
1 - High Rate Mode (HRM) supports sample rates up to 100 kHz. Typically used for

96 kHz sample rate.

CI1:0 Specifies the ratio of MCLK to the sample rate of the ADCs and DACs (Fs)

CI1:0 BRM (Fs) HRM (Fs)

0 128 64
*1 256 128
2384192
3512256

DS511PP1 21

5.3 Chip Control

Address 0x02

7 6543210

DIGPDN

1 0000000

CS4228A

RESERVED ADCPDN DACPDN56 DACPDN34 DACPDN12 RESERVED

DIGPDN

ADCPDN Power down the analog section of the ADC

DACPDN12 Power down the analog section of DAC 1 and 2

DACPDN34 Power down the analog section of DAC 3 and 4

DACPDN56 Power down the analog section of DAC 5 and 6

Power down the digital portions of the CODEC
0 - Digital power down.
*1 - Normal operation

*0 - Normal
1 - ADC power down.

*0 - Normal
1 - Power down DAC 1 and 2.

*0 - Normal
1 - Power down DAC 3 and 4.

*0 - Normal
1 - Power down DAC 5 and 6.

5.4 ADC Control

Address 0x03

76543210

MUTL MUTR HPF HPFZ RESERVED

00000000

MUTL, MUTR ADC left and right channel mute control

*0 - Normal
1 - Selected ADC output muted

HPF ADC DC offset removal. See “High Pass Filter” for more information

*0 - Enabled
1 - Disabled

HPFZ ADC DC offset averaging freeze. See “High Pass Filter” for more information

*0 - Normal. The DC offset average is dynamically calculated and subtracted from incoming

ADC data.

1 - Freeze. The DC offset average is frozen at the current value and subtracted from

incoming ADC data. Allows passthru of DC information.

22 DS511PP1

CS4228A

5.5 DAC Mute1 Control

Address 0x04

76543210

MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 RMP1 RMP0

11111100

MUT6 - MUT1 Mute control for DAC6 - DAC1 respectively. When asserted, the corresponding DAC is digitally

attenuated to its maximum value (90.5 dB). When deasserted, the corresponding DAC atten­uation value returns to the value stored in the corresponding Digital Volume Control register.
The attenuation value is ramped up and down at the rate specified by RMP1:0.
0 - Normal output level
*1 - Selected DAC output fully attenuated.

RMP1:0 Attenuation ramp rate.

*0 - 0.5 dB change per 4 LRCKs
1 - 0.5 dB change per 8 LRCKs
2 - 0.5 dB change per 16 LRCKs
3 - 0.5 dB change per 32 LRCKs

5.6 DAC Mute2 Control

Address 0x05

76543210

MUTEC MUTCZ RESERVED HMUTE56 HMUTE34 HMUTE12 RESERVED

10000000

MUTEC Controls the MUTEC

0 - Normal operation
*1 - MUTEC

MUTCZ Automatically asserts the MUTEC

zeros on all six DAC inputs will cause the MUTEC
value on any DAC input will cause the MUTEC
*0 - Disabled
1 - Enabled

HMUTE56/34/12 Hard mute the corresponding DAC pair. When asserted, zero data is sent to the corresponding

DAC pair causing an instantaneous mute. To prevent high frequency transients on the outputs,
a DAC pair should be fully attenuated by asserting the corresponding MUT6-MUT1 bits in the
DAC Mute Control register or by writing 0xFF to the corresponding Digital Volume Control reg­isters before asserting HMUTE.
*0 - Normal operation
1 - DAC pair is muted

pin

pin asserted low

pin on consecutive zeros. When enabled, 512 consecutive

pin to be asserted low. A single non-zero

pin to deassert.

DS511PP1 23

CS4228A

5.7 DAC De-emphasis Control

Address 0x06

76543210

DEMS1 DEMS0 DEM6 DEM5 DEM4 DEM3 DEM2 DEM1

10000000

DEMS1:0 Selects the DAC de-emphasis response curve.

0 - Reserved
1 - De-emphasis for 48 kHz
*2 - De-emphasis for 44.1 kHz
3 - De-emphasis for 32 kHz

DEM6 - DEM1 De-emphasis control for DAC6 - DAC1 respectively

*0 - De-emphasis off
1 - De-emphasis on

5.8 Digital Volume Control

Addresses 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C

76543210

VOLn

00000000

VOL6 - VOL1 Address 0x0C - 0x07 sets the attenuation level for DAC 6 - DAC1 respectively. The attenutation

level is ramped up and down at the rate specified by RMP1:0 in the DAC Volume Control Setup
register.
0 - 181 represents 0 to 90.5 dB of attenuation in 0.5 dB steps.

24 DS511PP1

CS4228A

5.9 Serial Port Mode

Address 0x0D

76543210

DCK1 DCK0 DMS1 DMS0 RESERVED DDF2 DDF1 DFF0

10000100

DCK1:0 Sets the number of Serial Clocks (SCLK) per Fs period (LRCLK)

DCK1:0 BRM (Fs) HRM (Fs)

0 32 (1) (3)
1 48 (2) (3)
2 *64 32 (1)
3 128 64

Notes: 1. All formats will default to 16 bits

2. External Slave mode only

3. Invalid mode

DMS1:0 Sets the master/slave mode of the serial audio port

*0 - Slave (External LRC LK, SCLK)
1 - Reserved
2 - Reserved
3 - Master (No 48 Fs SCLK in BRM

DDF2:0 Serial Port Data Format

0 - Right Justified, 24-bit
1 - Right Justified, 20-bit
2 - Right Justified, 16-bit
3 - Left Justified, maximum 24-bit

2

*4 - I
5 - One-line Data Mode, available in BRM only
6 - Reserved
7 - Reserved

S compatible, maximum 24-bit

5.10 Chip Status

Address 0x0E

76543210

CLKERR ADCOVL RESERVED

XX000000

CLKERR Clocking system status, read only

0 - No Error
1 - No MCLK is present, or a request for clock change is in progress

ADCOVL ADC overflow bit, read only

0 - No overflow
1 - ADC overflow has occurred

DS511PP1 25

6. PIN DESCRIPTION

CS4228A

Serial Audio Data In 3 SDIN3 SUB Analog Out #6,Subwoofer
Serial Audio Data In 2 SDIN2 CENTER Analog Out #5, Center
Serial Audio Data In 1 SDIN1 SR Analog Ou t #4, Surround Right

Serial Audio Data Out SDOUT SL Analog Out #3, Surround Left

Serial Clock SCLK FR Analog Out #2, Front Right

Left/Right Clock LRCK FL Analog Out #1, Front Left

Digital Ground DGND AGND Analog Ground

Digital Power VD VA Analog Power

Digital Interface Power VL AINL+ Left Channel Analog Input+

Master Clock MCLK AINL- Left Channel Analog Input-

SCL/CCLK SCL/CCLK FILT Internal Voltage Filter

SDA/CDIN SDA/CDIN AINR- Right Channel Analog Input-

AD0/CS

AD0/CS AINR+ Right Channel Analog Input+

1

1
2

2
3
4
5

5
6

6
7
8
9
10
11
12
13

Reset RST

28
27
26

25
24
23
22
21
20
19
18
17
16
1514

MUTEC Mute Control

SDIN1, SDIN2,
SDIN3

SDOUT 4

SCLK 5

1, 2, 3 Serial Audio Data In (

pin. The data is clocked into SDIN1, SDIN2, SDIN3 via the serial clock and the channel is
determined by the Left/Right clock. The required relationship between the Left/Right clock,
serial clock and s erial d ata is defin ed by the Seri al Mod e Regis ter . The op tions are det ailed
in Figures 9, 10, 11, and 12.

Serial Audio Data Out (
pin. The data is clocked out of SDOU T via the serial cl ock and the channe l is dete rmined by
the Left/Right clock. The requi red relationsh ip between the Left/Right c lock, serial cloc k and
serial data is de fined by the Ser ial Mo de Register. The options are detailed i n Figur es 9, 10,
11 and 12.
The state of the SDOUT pin during reset is used to set the Control Port Mode (two wire or
SPI). When RST
latches the stat e of the pi n. A weak in ternal pu ll up is presen t such that a res istiv e load le ss
than 47 kΩ will pull the pin low, and the control port mode is two wire. When the resistive
load on SDOUT is greater than 47 k Ω during reset, the control port mode is SPI.

Serial Clock (
and out of the SDOUT pin. The pin is an output in master mode, and an input in slave
mode.
In master mode, SCLK is configured as an output. MCLK is divided internally to generate
SCLK at the desired multiple of the s ample rate.
In slave mode, SCLK is configured as an input. The serial clock can be provided externally,
or the pin can be grounded and the serial clock derived internally from MCLK.
The required relations hi p be tw ee n the Lef t/R ig ht c loc k, serial clock and serial audio data is
defined by the Serial Port Mode register. The options are detaile d in Fig ures 9, 1 0, 11, and

12.

is low, SDOUT is configured as an input, and the rising edge of RST

Bidirectional

Input

) - Two’s comp lement MSB-firs t serial audio dat a is input on this

Output

) - Two’s complement MSB-first serial data is output on this

) - Clocks serial data into the SDIN1, SDIN2, and SDIN3 pins,

26 DS511PP1

CS4228A

LRCK 6

DGND 7 Digital Ground (
VD 8 Digital Power (
VL 9 Digital Interface Power (

MCLK 10

Left/Right Clock (

rently being input or output on the serial audio data output, SDOUT. The frequency of the
Left/Right clock must be at the outpu t sampl e rate, Fs. In Master mode , LRCK is an output,
in Slave Mode, LR CK is an i nput who se fre quenc y mus t be equal to Fs and s ynchr onous to
the Master clock.

Audio samples in Left/Right pairs repre sent simult aneously s ampled analog inpu ts wherea s
Right/Left pairs will exhibit a one sample period difference. The required relationship
between the Left/Right cl ock, s erial cloc k and serial dat a is d efined by the Serial Port Mode
register. The options are detailed in Figures 9, 10, 11 and 12

5.0 VDC. All digital output voltages and input threshholds scale with VL.

Master Clock (
512x the input sample rate in Base Rate Mode (BRM) and either 64x, 128x, 192x, or 256x
the input sample rate in High Rate Mode (HRM). Table 2 illustrates several standard audio
sample rates and the required master clock frequencies. The MCLK/Fs ratio is set by the
CI1:0 bits in the CODEC Clock Mode register.

Sample

Rate

(kHz)

32 - - - - 4.0960 8.1920 12.2880 16.3840

44.1 - - - - 5.6448 11.2896 16.9344 22.5792
48 - - - - 6.1440 12.2880 18.4320 24.5760
64 4.0960 8.1920 12.2880 16.3840 - - - -

88.2 5.6448 11.2896 16.9344 22.5792 - - - ­96 6.1440 12.2880 18.4320 24.5760 - - - -

Bidirectional

Input

) - Digital Ground Reference.

Input

) - Digital Power Supply. Typically 5.0 VDC.

Input

) - The master clock frequency must be either 128x, 256x, 384x or

64x 128x 192x 256x 128x 256x 384x 512x

Table 2 . Common Master Clock Frequencies

) - The Left/Right clock determines which channel is cur-

.

Input

) - Digital interface power supply. Typically 2.5, 3.3 or

MCLK (MHz)

HRM BRM

SCL/CCLK 11 Serial Control Interface Clock (

SDA/CDIN.

SDA/CDIN 12 Serial Control Data I/O (

trol port data line. A pull up re sistor must be pro vided for proper open dra in output operation .
In SPI mode, CDIN is the control port data input line. The state of the SDOUT pin during
reset is used to set the control port mode.

ADO/CS

RST

MUTEC 15 Mute Control (

13

14

Address Bit 0 / Chip Select (Input) - In two wire mode, AD0 is the LSB of the chip
address. In SPI mode, CS

Reset (Input) - When low, the device enters a low power mode and all internal registers
are reset to the default settings, including the control port. The control port can not be
accessed when reset is low.
When high, the control port and the CODEC become operational.

Output

er-up initialization, power-down, reset, no master clock present, or if the master clock to
left/right clock frequ ency ratio is incorrect. The Mute Control pi n can also b e user co ntrolled
by the MUTEC bit in the DAC Mute2 Co ntrol register. M ute Control ca n be automati cally as­serted when 512 consecutive zeros are detected on all six DAC inputs, and automatically
deasserted when a s in gle no n-ze ro v al ue is sent to any of the six DACs. The mu te o n z ero
function is control
is intended to be used as a control fo r an external mute circuit to achie ve a ve ry low noise
floor during periods when no audio is present on the DAC outputs, and to prevent the clicks
and pops that can occur in any single supply system. Use of the Mute Control pin is not man-

tory but recommended.

da

led by the MUTCZ bit in the DAC Mute2 Control register. The MUTEC pin

Bidirectional/Input

is used as a enable for the control port interface.

) - The Mute Control pin goes low during the following c onditions: pow-

Input

) - Clocks the serial control data into or out of

) - In two wire mode, SDA is a bidirectional con-

DS511PP1 27

CS4228A

AINR+, AINR-,
AINL+, AINL-

FIL T 18 Internal Voltage Filter (

VA 21 Analog Power (
AGND 22 Analog Ground (
FR, FL, SR, SL

SUB, CENTER

16, 17, 19, 20 Differential Analog Inputs (

the modulators via the AINR+/- and AINL+/- pins. The + and - input signals are 180° out of
phase resulting in a nominal differential input voltage of twice the input pin voltage. These
pins are biased to the i nternal reference vo ltage of approximate ly 2.3 V. A passive anti-alias­ing filter is required for b est performa nce, as sh own in Figu re 5. The inpu ts can be driv en at

-1 dB FS single-ended if the unused i nput is connected to ground thro ugh a large value ca­pacitor. A single end ed to differential converter circuit can also be used for slightly be tter per­formance.

from FILT to analog ground, as shown in Figure 5. FILT is not intended to supply external
current. FILT+ has a typical source impedance of 250 kΩ and any current drawn from this
pin will alter devi ce performance. Care should be t aken during board layout to kee p dynamic
signal traces away from this pin.

Input

) - Power for the analog and reference circuits. Typically 5.0 VDC.

Input

23, 24, 25,

26, 27, 28

Analog Outputs (
is specified in the Analog Characteristics specifications table. The amplitude of the outputs
is controlled by the Digital Volume Control registers 0x07 - 0x0C..

Output

Input

) - The analog signal inpu ts are prese nted defere ntially to

Output

) - Filter for internal ci rcuits. An external capacitor is re quired

) - Analog ground reference.

) - Analog outputs from the D ACs. The full scale an alog output level

28 DS511PP1

7. PARAMETER DEFINITIONS

Dynamic Range

The ratio of the full scale RMS value of the signal to the RMS sum of all other spectral
components over the specified bandwidth. Dynamic range is a signal-to-noise measurement
over the specified bandwidth made with a -60 dbFs signal. 60 dB is then added to the resulting
measurement to refer the measurement to full scale. This technique ensures that the distortion
components are below the noise level and do not effect the measurement. This measurement
technique has been accepted by the Audio Engineering Society, AES17-1991, and the
Electronic Industries Association of Japan, EIAJ CP-307.

Total Harmonic Distortion + Noise

The ratio of the RMS value of the signal to the RMS sum of all other spectral components over
the specified bandwidth (typically 20 Hz to 20 kHz), including distortion components.
Expressed in decibels. ADCs are measured at -1dBFs as suggested in AES 17-1991 Annex A.

Idle Channel Noise / Signal-to-Noise-Ratio

The ratio of the RMS analog output level with 1 kHz full scale digital input to the RMS analog
output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz
bandwidth. Units in decibels. This specification has been standardized by the Audio
Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has
also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and
referred to as Signal-to-Noise-Ratio.

CS4228A

Total Harmonic Distortion (THD)

THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of
the test signal. Units in decibels.

Interchannel Isolation

A measure of crosstalk between channels. Measured for each channel at the converter’s output
with no signal to the input under test and a full-scale signal applied to the other channel. Units
in decibels.

Frequency Response

A measure of the amplitude response variation from 20 Hz to 20 kHz relative to the amplitude
response at 1 kHz. Units in decibels.

Interchannel Gain Mismatch

For the ADCs, the difference in input voltage that generates the full scale code for each
channel. For the DACs, the difference in output voltages for each channel with a full scale
digital input. Units are in decibels.

DS511PP1 29

Gain Error

The deviation from the nominal full scale output for a full scale input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input
grounded. For the DACs, the deviation of the output from zero (relative to CMOUT) with mid­scale input code. Units are in volts.

CS4228A

30 DS511PP1

8. PACKAGE DIMENSIONS

28L SSOP PACKAGE DRAWING

N

CS4228A

D

E

A2

A

E1

1

∝

2

b

SIDE VIEW

1

23

e

TOP VIEW

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.084 -- -- 2.13
A1 0.002 0.006 0.010 0.05 0.15 0.25
A2 0.064 0.069 0.074 1.62 1.75 1.88

b 0.009 -- 0.015 0.22 -- 0.38 2,3
D 0.390 0.4015 0.413 9.90 10.20 10.50 1
E 0.291 0.307 0.323 7.40 7.80 8.20

E1 0.197 0.209 0.220 5.00 5.30 5.60 1

e 0.022 0.026 0.030 0.55 0.65 0.75

L 0.025 0.0354 0.041 0.63 0.90 1.03

∝

0° 4° 8° 0° 4° 8°

A1

SEATING

PLANE

L

END VIEW

JEDEC #: MO-150

Controlling Dimension is Millimeters

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

DS511PP1 31