Datasheet CS4124YN16 Datasheet (Cherry Semiconductor)

Features

■ 150mA Peak PWM Gate

Drive Output

■ Patented Voltage

Compensation Circuit

■ 100% Duty Cycle

Capability

■ 5V, ± 3% Linear Regulator

■ Low Current Sleep Mode

■ Overvoltage Protection

■ Boost Mode Power

Supply

■ Output Inhibit

Package Option

CS4124

High Side PWM FET Controller

CS4124

Description

Applications Diagram

Preliminary

OUTPUT

Gnd
INH
I

ADJ

PMP
SNI

V

REG

BOOST

FLT

R

OSC

C

OSC

CTL

PGnd

V

CC

I

SENSE+

I

SENSE-

16 Lead PDIP

1195

Consult Factory for 16 Lead SOIC
Wide package.

Rev. 4/26/99

Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: [phone] Fax: [phone]

Email: [e-mail]

Web Site: www.cherry-semi.com

A Company

®

The CS4124 is a monolithic integrat­ed circuit designed primarily to
control the rotor speed of perma­nent magnet, direct current (DC)
brush motors. It drives the gate of
an N channel power MOSFET or
IGBT with a user-adjustable, fixed
frequency, variable duty cycle,
pulse width modulated (PWM) sig­nal. The CS4124 can also be used to
control other loads such as incan­descent bulbs and solenoids.
Inductive current from the motor or
solenoid is recirculated through an
external diode.

The CS4124 accepts a DC level
input signal of 0 to 5V to control the

pulse width of the output signal.
This signal can be generated by a
potentiometer referenced to the on­chip 5V linear regulator, or a fil­tered 0% to 100% PWM signal also
referenced to the 5V regulator.

The IC is placed in a sleep state by
pulling the CTL lead below 0.5V. In
this mode everything on the chip is
shutdown except for the on-chip
regulator and the overall current
draw is less than 275µA. There are a
number of on-chip diagnostics that
look for potential failure modes and
can disable the external power
MOSFET.

V

BAT

42.5µH

1000µF

1000µF

10K

10nF

100µF

.01µF

C

FLT

.25µF

R

OSC

C

OSC

470pF

93.1K

OUTPUT

Gnd

INH

BOOST
FLT

R

OSC

I

ADJ

PMP

SNI

V

REG

C

OSC

CTL
PGnd

V

CC

P1

N1

10µF

10K

100K

10K

10K

10K

R

CS1

51

R

CS2

51

C

CS

.022µF

10K

10K

Input

470µH

MOT+

R

GATE

6

R

SENSE

4m

R

SNI

4

1.5µF

1µF

1M

I

SENSE+

I

SENSE-

MOT-

R

S

10

1

Electrical Characteristics:

4V ≤ VCC≤ 26V, -40˚C < TA< 125°C, (unless otherwise specified)

CS4124

1196

Absolute Maximum Ratings

Storage Temperature ................................................................................................................................................-65˚C to 150˚C

V

CC

.................................................................................................................................................................................-0.3V to 30V

V

CC

Peak Transient Voltage (load dump = 26V w/series 10Ω resistor) ...........................................................................40V

Input Voltage Range (at any input) ...........................................................................................................................-0.3V to 10V

Maximum Junction Temperature ..........................................................................................................................................150˚C

Lead Temperature Soldering

Wave Solder (through hole styles only) ......................................................................................10 sec. max, 260°C peak

ESD Capability (Human Body Model) ....................................................................................................................................2kV

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

■ V

CC

Supply

Operating Current Supply 7V ≤ VCC≤ 18V 5 10 mA

4V ≤ VCC< 7V, 18V < VCC≤ 26V 15 mA
Quiescent Current VCC= 12V 170 275 µA
Overvoltage Shutdown 26.5 29 V

■ Control (CTL)

Control Input Current CTL = 0V to 5V -2 0.1 2 µA
Sleep Mode Threshold 8% 10% 12% V

REG

Sleep Mode Hysteresis 7V ≤ VCC≤ 26V 50 100 150 mV

4V ≤ VCC< 7V 10 150 mV

■ Current Sense

Differential Voltage Sense 7V ≤ VCC≤ 18V

I

ADJ

= 1V and R

CS1

= 51Ω 18 34 mV

I

ADJ

= 4V and R

CS1

= 51Ω 104 125 mV

4V ≤ VCC< 7V

I

ADJ

=1V and R

CS1

= 51Ω 15 39 mV

18V < VCC≤ 26V

I

ADJ

= 1V and R

CS1

= 51Ω 15 39 mV

I

ADJ

= 4V and R

CS1

= 51Ω 102 130 mV

I

ADJ

Input Current 4V ≤ VCC≤ 26V -2 0.3 2 µA

I

ADJ

= 0V to 5V

■ Linear Regulator

Output Voltage, V

REG

VCC= 4V 2.0 V

VCC= 13.2V 4.85 5.15 V

VCC= 26V 4.85 5.20 V

■ Inhibit

Inhibit Threshold 40% 50% 60% V

REG

Inhibit Hysteresis 4V ≤ VCC≤ 7V 100 500 mV

7V ≤ VCC≤ 26V 150 325 500 mV

■ External Drive (OUTPUT)

Output Frequency 4V ≤ VCC< 7V

R

OSC

= 93.1kΩ, C

OSC

= 470pF 10 25 kHz

7V ≤ VCC≤ 18V,

R

OSC

= 93.1kΩ, C

OSC

= 470pF 17 20 23 kHz

18V < VCC≤ 26V

R

OSC

= 93.1kΩ, C

OSC

= 470pF 17 20 25 kHz

CS4124

1197

Electrical Characteristics:

4V ≤ VCC≤ 26V, -40˚C < TA= 125°C, (unless otherwise specified)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Package Lead Description

PACKAGE LEAD # LEAD SYMBOL FUNCTION

■ External Drive (OUTPUT): continued

Voltage to Duty Cycle 4V ≤ VCC< 7V
Conversion VCC= 13V, CTL = 1V 65 75 %

VCC= 13V, CTL = 2V 100 %
7V ≤ VCC≤ 18V

VCC= 13V, CTL = 30% V

REG

28.3 36.3 %

VCC= 13V, CTL = 55.8% V

REG

56.0 64.0 %

18V < VCC≤ 26V
VCC= 13V, CTL = 1. 5V 11.8 21.8 %
VCC= 13V, CTL = 3. 5V 34.2 44.2 %

Output Rise Time 4V ≤ VCC≤ 26V .25 1 µs

R

GATE

= 6Ω, C

GATE

= 5nF

Output Fall Time 4V ≤ VCC≤ 26V .30 1 µs

R

GATE

= 6Ω, C

GATE

= 5nF

Output Sink Current 4V ≤ V

CC

< 7V 150 mA

R

GATE

= 6Ω, C

GATE

= 5nF

7V ≤ VCC≤ 26V 300 mA
R

GATE

= 6Ω, C

GATE

= 5nF

Output Source Current 4V ≤ VCC< 7V 150 mA

R

GATE

= 6Ω, C

GATE

= 5nF

7V ≤ VCC≤ 26V 300 mA
R

GATE

= 6Ω, C

GATE

= 5nF

Output High Voltage I

OUT

= 1mA V

BOOST

- 1.7 V

Output Low Voltage I

OUT

= -1mA 1.3 V

■ Charge Pump (DRV)

Boost Voltage VCC+ 6.4 V

16 Lead PDIP

1 OUTPUT MOSFET gate drive

2 BOOST Boost voltage

3 FLT Fault time out capacitor

4R

OSC

Oscillator resistor

5C

OSC

Oscillator capacitor

6 CTL Pulse width control input

7 PGnd Power ground for on chip clamp

8V

CC

Positive power supply input

9V

REG

5V linear regulator

10 SNI Sense inductor current

11 PMP Collector of boost power transistor

12 I

SENSE-

Current sense minus

13 I

SENSE+

Current sense plus

14 I

ADJ

Current limit adjust

15 INH Output Inhibit

16 Gnd Ground

CS4124

1198

Application Information

Oscillator

The IC sets up a constant frequency triangle wave at the
C

OSC

lead whose frequency is related to the external com-

ponents R

OSC

and C

OSC

, by the following equation:

Frequency =

The peak and valley of the triangle wave are proportional
to V

CC

by the following:

V

VALLEY

= 0.1 × V

CC

V

PEAK

= 0.7 × V

CC

This is required to make the voltage compensation function
properly. In order to keep the frequency of the oscillator
constant the current that charges C

OSC

must also vary with

supply. R

OSC

sets up the current which charges C

OSC

. The

voltage across R

OSC

is 50% of VCCand therefore:

I

ROSC

= 0.5 ×

I

ROSC

is multiplied by (2) internally and transferred to the

C

OSC

lead. Therefore:

I

COSC

= ±

The period of the oscillator is:

T = 2C

OSC

×

The R

OSC

and C

OSC

components can be varied to create fre­quencies over the range of 15Hz to 25kHz. With the sug­gested values of 93.1kΩ and 470pF for R

OSC

and C

OSC

, the

nominal frequency will be approximately 20 kHz. I

ROSC

, at

VCC= 14V, will be 66.7 µA. I

ROSC

should not change over a

more than 2:1 ratio and therefore C

OSC

should be changed

to adjust the oscillator frequency.

Voltage Duty Cycle Conversion

The IC translates an input voltage at the CTL lead into a
duty cycle at the OUTPUT lead. The transfer function
incorporates Cherry Semiconductor’s patented Voltage
Compensation method to keep the average voltage and
current across the load constant regardless of fluctuations
in the supply voltage. The duty cycle is varied based upon
the input voltage and supply voltage by the following
equation:

Duty Cycle = 100% ×

An internal DC voltage equal to:

VDC= (1.683 × V

CTL

) + V

VALLEY

is compared to the oscillator voltage to produce the com-

pensated duty cycle. The transfer is set up so that when
V

CC

= 14V the duty cycle will equal V

CTL

divided by V

REG

.

For example at VCC= 14V, V

REG

= 5V and V

CTL

= 2.5V, the
duty cycle would be 50% at the output. This would place a
7V average voltage across the load. If V

CC

then drops to
10V, the IC would change the duty cycle to 70% and hence
keep the average load voltage at 7V.

Figure 1: Voltage Compensation

5V Linear Regulator

There is a 5V, 5mA linear regulator available at the V

REG

lead for external use. This voltage acts as a reference for
many internal and external functions. It has a drop out of
approximately 1.5V at room temperature.

Current Sense and Timer

The IC differentially monitors the load current on a cycle
by cycle basis at the I

SENSE+

and I

SENSE-

leads. The differen­tial voltage across these two leads is amplified internally
and compared to the voltage at the I

ADJ

lead. The gain, A

V

is set internally and externally by the following equation:

A

V

==

The current limit (I

LIM

) is set by the external current sense

resistor (R

SENSE

) placed across the I

SENSE+

and I

SENSE-

ter-

minals and the voltage at the I

ADJ

lead.

I

LIM

= ×

The R

CS

resistors and CCScomponents form a differential
low pass filter which filters out high frequency noise gen­erated by the switching of the external MOSFET and the
associated lead noise. R

CS

also forms and error term in the

gain of the I

LIM

equation because the I

SENSE+

and I

SENSE-

leads are low impedance inputs thereby creating a good
current sensing amplifier. Both leads source 50µA while
the chip is in run mode. I

ADJ

should be biased between 1V

and 4V. When the current through the external MOSFET

V

I(ADJ)

R

SENSE

1000 + R

CS

37000

37000

1000 + R

CS

V

I(ADJ)

I

SENSE+

- I

SENSE-

2.8 × V

CTL

V

CC

V

PEAK

- V

VALLEY

I

COSC

V

CC

R

OSC

V

CC

R

OSC

0.83

R

OSC

× C

OSC

Theory Of Operation

120%

100%

80%

60%

Duty Cycle( %)

40%

20%

0%

10% 20% 30% 40% 50% 60% 70% 80% 90% 100%

CTL Voltage (% of V

VCC = 8V

VCC = 14V

VCC = 16V

REG

)

CS4124

1199

Application Information: continued

exceeds I

LIM

, an internal latch is set and the output pulls
the gate of the MOSFET low for the remainder of the oscil­lator cycle (fault mode). At the start of the next cycle, the
latch is reset and the IC reverts back to run mode until
another fault occurs. If a number of faults occur in a given
period of time, the IC “times out” and disables the MOS­FET for a long period of time to let it cool off. This is
accomplished by charging the C

FLT

capacitor each time an
over current condition occurs. If a cycle goes by with no
overcurrent fault occurring, an even smaller amount of
charge will be removed from C

FLT

. If enough faults occur

together, eventually C

FLT

will charge up to 2.4V and the
fault latch will be set. The fault latch will not be reset until
C

FLT

discharges to 0.6V. This action will continue indefi-

nitely if the fault persists.
The off time and on time are set by the following:

Off Time = C

FLT

×

On Time = C

FLT

×

where:

I

AVG

= (295.5µA × DC) - [4.5µA × (1 - DC )]

I

AVG

= (300µA × DC) - 4.5µA

DC = PWM Duty Cycle

Boost Switch Mode Power Supply

The CS4124 has an integrated boost mode power supply
which charges the gate of the external high-side MOSFET
to greater than 5V above V

CC

. Three leads are used for
voltage boost. They are Boost, PMP and SNI. The PMP
lead is the collector of a darlington tied NPN power tran­sistor. This device charges the inductor during its on time.
The boost lead is the input to chip from the external reser­voir capacitor. The SNI lead is the emitter of the power
NPN and is connected externally to the R

SNI

resistor.

The power supply is controlled by the oscillator. At the
start of a cycle an R-S flip flop is set the internal power
NPN transistor is turned on and energy begins to build up
in the inductor. The R

SNI

resistor sets the peak current of
the inductor by tripping a comparator when the voltage
across the resistor is 450mV. The flip flop is reset and the
inductor delivers its stored energy to the load. The ripple
voltage (V

RIPPLE

) at the Boost lead is controlled by C

BOOST

.
A snubber circuit, made up of a series resistor and capaci­tor, is required to dampen the ringing of the inductor. A
value of 4Ω is recommended for R

SNI

.

A zener diode is needed between the boost output voltage
and the battery. This will clamp the boost lead to a speci­fied value above the battery to prevent damage to the IC.
A 9 volt zener diode is recommended.

Sleep State

This device will enter into a low current mode (< 275µA)
when CTL lead is brought to less than 0.5V. All functions
are disabled in this mode, except for the regulator.

Inhibit

When the inhibit is greater than 2.5V the internal latch is
set and the external MOSFET will be turned off for the
remainder of the oscillator cycle. The latch is then reset at
the start of the next cycle.

Overvoltage Shutdown

The IC will disable the output during an overvoltage
event. This is a real time fault event and does not set the
internal latch and therefore is independent of the oscillator
timing (i.e. asynchronous). There is 325mV (typical) of
hysteresis on the overvoltage function. There is no under­voltage lockout. The device will shutdown gracefully once
it runs out of headroom.

Reverse Battery

The CS4124 will not survive a reverse battery condition. A
series diode is required between the battery and the V

CC

lead for reverse battery.

Load Dump

A 10Ω resistor, (RS) is placed in series with V

CC

to limit the

current into the IC during 40V peak transient conditions.

2.4V - 0.6V
I

AVG

2.4V - 0.6V

4.5µA

1200

D

Lead Count Metric English

Max Min Max Min

16L PDIP 19.69 18.67 .775 .735

© 1999 Cherry Semiconductor Corporation

Thermal Data 16 Lead

PDIP

R

ΘJC

typ 42 ˚C/W

R

ΘJA

typ 80 ˚C/W

Rev. 4/26/99

Ordering Information

Package Specification

PACKAGE DIMENSIONS IN mm (INCHES)

PACKAGE THERMAL DATA

Part Number Description

CS4124YN16 16L PDIP

CS4124

Plastic DIP (N); 300 mil wide

0.39 (.015)
MIN.

2.54 (.100) BSC

1.77 (.070)

1.14 (.045)

D

Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.

.203 (.008)

.356 (.014)

REF: JEDEC MS-001

3.68 (.145)

2.92 (.115)

8.26 (.325)

7.62 (.300)

7.11 (.280)

6.10 (.240)

.356 (.014)

.558 (.022)

Cherry Semiconductor Corporation reserves the right to
make changes to the specifications without notice. Please
contact Cherry Semiconductor Corporation for the latest
available information.