Datasheet CS3845BGN8, CS3845BGDR8, CS3845BGDR14, CS3845BGD8, CS3845BGD14 Datasheet (Cherry Semiconductor)

1

Features

■

Optimized for Off-line Use

■

Temperature
Compensated Oscillator

■

50% Maximum Duty-cycle
Clamp

■ Low Start-up Current

(500µA max)

■ Pulse-by-pulse Current

Limiting

■ Undervoltage Active Pull

Down

■ Double Pulse Suppression

■ 1% Trimmed Bandgap

Reference

■ High Current Totem Pole

Output

Package Options

CS3845B

Current Mode PWM

Control Circuit

with 50% Max Duty Cycle

CS3845B

Description

Block Diagram

Absolute Maximum Ratings

Supply Voltage (I

CC

<30mA) ..........................................................Self Limiting

Supply Voltage (Low Impedance Source)...................................................30V

Output Current ...............................................................................................±1A

Output Energy (Capacitive Load) .................................................................5µJ

Analog Inputs (VFB, V

SENSE

)...........................................................-0.3V to 5.5V

Error Amp Output Sink Current...............................................................10mA

Lead Temperature Soldering

Wave Solder (through hole styles only) ..........10 sec. max, 260°C peak

Reflow (SMD styles only)...........60 sec. max above 183°C, 230°C peak

1

COMP

2
3
4

V

FB

Sense

OSC

V

REF

V

CC

V

OUT

Gnd

8
7
6
5

8 Lead PDIP & SO

10

7

14

13

12

8

1

2

3

4

5

6

11

9

COMP

NC

V

FB

NC

Sense

NC

OSC

V

REF

NC
V

CC

VCC Pwr
V

OUT

Pwr Gnd

Gnd

14 Lead SO Narrow

The CS3845B provides all the neces­sary features to implement off-line
fixed frequency current-mode control
with a minimum number of external
components.

The CS3845B incorporates a precision
temperature-controlled oscillator to
minimize variations in frequency. An
internal toggle flip-flop, which blanks
the output off every other clock cycle,
ensures that the duty-cycle never

exceeds 50%. The undervoltage lock­out feature ensures that V

REF

is stabi­lized within specification before the
output stage is enabled. The CS3845B

has been optimized for lower start up
current (500µA max).

Other features include 1% trimmed
band gap reference, pulse-by-pulse
current limiting, and a high-current
totem pole output for driving capaci­tive loads.

Rev. 11/19/98

Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: [phone] Fax: [phone]

Email: [e-mail]

Web Site: www.cherry-semi.com

A Company

®

V

Undervoltage Lock-out

V

CC

CC

V

Pwr

CC

COMP

OSC

Sense

Gnd

V

34V

8.4V/7.6V

FB

Amplifier

2 R

Error

­+

Oscillator

R

2.50V

1V

Reset

R

Undervoltage

R

Current

Sensing

Comparator

Set/

V

REF

Lockout

Toggle

Flip-Flop

S

R
PWM

Latch

5.0 Volt

Reference

NOR

Internal

Bias

V

REF

V

OUT

Pwr Gnd

2

Electrical Characteristics: 0≤TA≤70˚C, VCC=15V; RT=10kΩ, CT=3.3nF for sawtooth mode, unless otherwise stated

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

CS3845B

■ Reference Section

Output Voltage T

J

=25˚C, I

REF

=1mA 4.90 5.00 5.10 V

Line Regulation 12≤V

CC

≤25V 6 20 mV

Load Regulation 1≤I

REF

≤20mA 6 25 mV
Temperature Stability (Note 1) 0.2 0.4 mV/˚C
Total Output Variation Line, Load, Temp. (Note 1) 4.82 5.18 V
Output Noise Voltage 10Hz≤f≤10kHz, TJ=25˚C (Note 1) 50 µV
Long Term Stability TA=125˚C, 1000 Hrs. (Note 1) 5 25 mV
Output Short Circuit T

A

=25˚C -30 -100 -180 mA

■ Oscillator Section

Initial Accuracy Sawtooth Mode, TJ=25˚C 475257kHz
Voltage Stability 12≤V

CC

≤25V 0.2 1.0 %

Temperature Stability Sawtooth Mode T

MIN≤TA≤TMAX

(Note 1) 5 %

Amplitude V

OSC

(peak to peak)(Note 1) 17 V

Discharge TJ=25°C; (Note 1) 7.5 8.3 9.3 mA

T

MIN≤TA≤TMAX

(Note 1) 7.2 9.5 mA

■ Error Amp Section

Input Voltage V

COMP

=2.5V 2.42 2.50 2.58 V
Input Bias Current VFB=0V -0.3 -2.0 µA
AVOL 2≤V

OUT

≤4V 65 90 dB
Unity Gain Bandwidth (Note 1) 0.7 1.0 MHz
PSRR 12≤VCC≤25V 60 70 dB
Output Sink Current VFB=2.7V, V

COMP

=1.1V 2 6 mA

Output Source Current VFB=2.3V, V

COMP

=5V -0.5 -0.8 mA

V

OUT

HIGH VFB=2.3V, RL15kΩ to Gnd 5 6 V

V

OUT

LOW VFB=2.7V, RL=15kΩ to V

REF

0.7 1.1 V

■ Current Sense Section

Gain (Notes 2&3) 2.85 3.00 3.15 V/V
Maximum Input Signal V

COMP

=5V (Note 2) 0.9 1.0 1.1 V

PSRR 12≤V

CC

≤25V (Note 2) 70 dB
Input Bias Current V

Sense

=0V -2 -10 µA

Delay to Output TJ=25˚C (Note 1) 150 300 ns

■ Output Section

Output Low Level I

SINK

=20mA 0.1 0.4 V

I

SINK

=200mA 1.5 2.2 V

Output High Level I

SOURCE

=20mA 13.0 13.5 V

I

SOURCE

=200mA 12.0 13.5 V
Rise Time TJ=25˚C, CL=1nF (Note 1) 50 150 ns
Fall Time TJ=25˚C, CL=1nF (Note 1) 50 150 ns

3

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

CS3845B

Electrical Characteristics: continued

Package Pin Description

PACKAGE PIN # PIN SYMBOL FUNCTION

8L PDIP & SO 14L SO

1 1 COMP Error amp output, used to compensate error amplifier

23VFBError amp inverting input

3 5 Sense Noninverting input in Current Sense Comparator

4 7 OSC Oscillator timing network with Capacitor to Gnd, resistor

to V

REF

5 9 Gnd Ground

610V

OUT

Output drive pin

712VCCPositive power supply

814V

REF

Output of 5V internal reference

8 Pwr Gnd Output driver Gnd

11 V

CC

Pwr Output driver positive supply

2, 4, 6, 13 NC No Connection

■ Total Standby Current

Start-Up Current 300 500 µA
Operating Supply Current V

FB=VSense

=0V RT=10kΩ, CT=3.3nF 11 17 mA

V

CC

Zener Voltage ICC=25mA 34 V

■ PWM Section

Maximum Duty Cycle 46 48 50 %
Minimum Duty Cycle 0%

■ Under-Voltage Lockout Section

Start Threshold 7.8 8.4 9.0 V
Min. Operating Voltage After Turn On 7.0 7.6 8.2 V

Notes: 1. These parameters, although guaranteed, are not 100% test-

ed in production.

2. Parameter measured at trip point of latch with V

FB

=0

3. Gain defined as: A =

; 0 ≤ V

Sense

≤ 0.8V.

∆V

COMP

∆V

Sense

4

CS3845B

Undervoltage Lockout

During Undervoltage Lockout (Figure 1), the output driv­er is biased to sink minor amounts of current. The output
should be shunted to ground with a resistor to prevent
activating the power switch with extraneous leakage cur­rents.

PWM Waveform

To generate the PWM waveform, the control voltage from
the error amplifier is compared to a current sense signal
which represents the peak output inductor current (Figure

2). An increase in V

CC

causes the inductor current slope to
increase, thus reducing the duty cycle. This is an inherent
feed-forward characteristic of current mode control, since
the control voltage does not have to change during
changes of input supply voltage.

When the power supply sees a sudden large output cur­rent increase, the control voltage will increase allowing
the duty cycle to momentarily increase. Since the duty
cycle tends to exceed the maximum allowed to prevent
transformer saturation in some power supplies, the inter­nal oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of OSC compo­nents.

Circuit Description

Test Circuit

V

REF

V

CC

V

OUT

1kΩ
1W

0.1µF

0.1µF

V

REF

V

CC

V

OUT

Gnd

V

FB

Sense

OSC

COMP

5kΩ

100kΩ

4.7kΩ

1kΩ

Error Amp

Adjust

4.7kΩ

Sense

Adjust

R

T

2N2222

C

T

Gnd

A

CS-3845B

Figure 1: Startup voltage for CS3845B.

V

CC

<15mA

I

CC

<1mA

VON 8.4V
V

OFF

V

ONVOFF

ON/OFF Command

to reset of IC

CSX845B

7.6V

CC

V

5

CS3845B

Setting the Oscillator

The parameters Tcand Tdcan be determined as follows:

Grounding

High peak currents associated with capacitive loads neces­sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Gnd in a single
point ground.

The transistor and 5kΩ potentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.

Circuit Description: continued

Substituting in typical values for the parameters in the
above formulas:

V

REF

= 5.0V, V

upper

= 2.7V, V

lower

= 1.0V, Id= 8.3mA,

then

t

c

≈ 0.5534RTC

T

td= RTCTln

For better accuracy RTshould be ≥10kΩ.

)

2.3 - 0.0083 R

T

4.0 - 0.0083 R

T

(

V

Figure 2: Timing Diagram

Figure 3: Timing Parameters.

tc= RTCTln

t

d

= RTCTln

)

V

REF

- IdRT- V

lower

V

REF

- IdRT- V

upper

(

)

V

REF

- V

lower

V

REF

- V

upper

(

OSC

OSC

RESET

Toggle

F/F Output

EA Output

Switch

Current

V

CC

I

O

V

O

V

V

upper

lower

t

on

t

C

t

on = tC

t

off = tC+2td

t

off

t

d

Part Number 0˚C to 70°C Description

CS3845BGN8 • 8L PDIP
CS3845BGD8 • 8L SO
CS3845BGDR8 • 8L SO (tape & reel)
CS3845BGD14 • 14L SO
CS3845BGDR14 • 14L SO (tape & reel)

6

Thermal Data 8 L 8L 14 L

PDIP SO SO

R

QJC

typ 52 45 30 ˚C/W

R

QJA

typ 100 165 125 ˚C/W

Ordering Information

Package Specification

Rev.11/19/98

CS3845B

D

Lead Count Metric English

PACKAGE DIMENSIONS IN mm (INCHES)

PACKAGE THERMAL DATA

Max Min Max Min
8 Lead PDIP 10.16 9.02 .400 .355
8 Lead SO Narrow 5.00 4.80 .197 .189

14 Lead SO Narrow 8.75 8.55 .344 .337

0.39 (.015)
MIN.

2.54 (.100) BSC

1.77 (.070)

1.14 (.045)

D

Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.

.203 (.008)

.356 (.014)

REF: JEDEC MS-001

3.68 (.145)

2.92 (.115)

8.26 (.325)

7.62 (.300)

7.11 (.280)

6.10 (.240)

.356 (.014)

.558 (.022)

PDIP: 300 mil wide

1.27 (.050) BSC

0.51 (.020)

0.33 (.013)

6.20 (.244)

5.80 (.228)

4.00 (.157)

3.80 (.150)

1.57 (.062)

1.37 (.054)

D

0.25 (0.10)

0.10 (.004)

1.75 (.069) MAX

1.27 (.050)

0.40 (.016)

REF: JEDEC MS-012

0.25 (.010)

0.19 (.008)

SO Narrow; 150 mil wide

© 1999 Cherry Semiconductor Corporation

Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.