Datasheet CS3843BGN8, CS3843BGDR8, CS3843BGDR14, CS3843BGD8, CS3843BGD14 Datasheet (Cherry Semiconductor)

1

Features

V

CC

Gnd

OSC

V

FB

COMP

Sense

V

REF

V

OUT

Output
Enable

5V

Reference

Internal

Bias

NOR

S

R

PWM
Latch

Current

Sense

Comparator

Oscillator

1 V

R

2 R

V

C

Error

Amplifier

+
–

2.50V

Set/

Reset

Undervoltage

Lock-out Circuit

34V

( ) Indicates CS-3843B

16V/10V

(8.4V/7.6V)

VCC Pwr

Pwr Gnd

REF

■ Very low Start Up Current

(300µA typ)

■

Optimized Off-line
Control

■

Internally Trimmed,
Temperature
Compensated Oscillator

■

Maximum Duty-cycle
Clamp

■ V

REF

stabilization before

Output Enable

■ Pulse-by-pulse Current

Limiting

■ Improved Undervoltage

Lockout

■ Double Pulse Suppression

■ 1% Trimmed Bandgap

Reference

■ High Current Totem Pole

Output

Package Options

CS3842B/3843B

Off-Line Current Mode PWM

Control Circuit

with Very Low Start Up Current

CS3842B/CS3843B

Description

Block Diagram

Absolute Maximum Ratings

Supply Voltage (I

CC

<30mA) ..........................................................Self Limiting

Supply Voltage (Low Impedance Source)...................................................30V

Output Current ...............................................................................................±1A

Output Energy (Capacitive Load) .................................................................5µJ

Analog Inputs (VFB, Sense) ............................................................-0.3V to 5.5V

Error Amp Output Sink Current...............................................................10mA

Lead Temperature Soldering

Wave Solder (through hole styles only) ...................10 sec. max, 260°C peak

Reflow (SMD styles only) ....................60 sec. max above 183°C, 230°C peak

1

COMP

2
3
4

V

FB

Sense

OSC

V

REF

V

CC

V

OUT

Gnd

8
7
6
5

8 Lead PDIP & SO Narrow

10

7

14

13

12

8

1

2

3

4

5

6

11

9

COMP

NC

V

FB

NC

Sense

NC

OSC

V

REF

NC
V

CC

VCC Pwr

V

OUT

Pwr Gnd
Gnd

14L SO Narrow

Rev. 6/23/99

Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: [phone] Fax: [phone]

Email: [e-mail]

Web Site: www.cherry-semi.com

A Company

®

The CS384XB provides all the neces­sary features to implement off-line
fixed frequency current-mode control
with a minimum number of external
components. The family has been opti­mized for very low start up current
(300µA, typ).

The CS384XB family incorporates a
precision temperature-controlled oscil­lator with an internally trimmed dis­charge current to minimize variations
in frequency. A precision duty-cycle
clamp eliminates the need for an exter­nal oscillator when a 50% duty-cycle is
used. Duty-cycles of almost 100% are

possible. On board logic ensures that
V

REF

is stabilized before the output
stage is enabled. Ion-implant resistors
provide tighter control of undervoltage
lockout.

Other features include pulse-by-pulse
current limiting, and a high-current
totem pole output for driving capaci­tive loads, such as the gate of a power
MOSFET. The output is LOW in the off
state, consistent with N-channel
devices.

These ICs are available in 8 and 14 lead
surface mount (SO) and 8 lead PDIP
packages.

2

Electrical Characteristics: 0≤T

A

≤70˚C, VCC=15V (Note 1); RT=680Ω, CT=.022µF for triangular mode,

R

T

=10kΩ, CT=3.3nF for sawtooth mode (see Fig. 3), unless otherwise stated

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

CS3842B/3843B

■ Reference Section

Output Voltage TJ=25˚C, I

OUT

=1mA 4.90 5.00 5.10 V
Line Regulation 12≤VIN≤25V 6 20 mV
Load Regulation 1≤I

OUT

≤20mA 6 25 mV
Temperature Stability (Note 2) 0.2 0.4 mV/˚C
Total Output Variation Line, Load, Temperature (Note 2) 4.82 5.18 V
Output Noise Voltage 10Hz≤f≤10kHz, TJ=25˚C (Note 2) 50 µV
Long Term Stability T

A

=125˚C, 1kHrs. (Note 2) 5 25 mV

Output Short Circuit T

A

=25˚C -30 -100 -180 mA

■ Oscillator Section

Initial Accuracy Sawtooth Mode (see Fig. 3), T

J

=25˚C475257kHz

Triangular Mode (see Fig. 3), TJ=25˚C445260kHz
Voltage Stability 12≤VCC≤25V 0.2 1.0 %
Temp. Stability Sawtooth Mode T

MIN≤TA≤TMAX

(Note 2) 5 %

Triangular Mode T

MIN≤TA≤TMAX

(Note 2) 8 %
Amplitude Oscillator peak to peak 1.7 V
Discharge Current T

J

=25˚C 7.5 8.3 9.3 mA

T

MIN≤TA≤TMAX

7.2 9.5 mA

■ Error Amp Section

Input Voltage V

COMP

=2.5V 2.42 2.50 2.58 V
Input Bias Current -0.3 -2.0 µA
A

VOL

2≤V

OUT

≤4V 65 90 dB
Unity Gain Bandwidth (Note 2) 0.7 1.0 MHz
PSRR 12≤V

CC

≤25V 60 70 dB
Output Sink Current VFB=2.7V, V

OSC

=1.1V 2 6 mA

Output Source Current VFB=2.3V, V

OSC

=5V -0.5 -0.8 mA

V

OUT

High VFB=2.3V, RL=15kΩ to ground 5 6 V

V

OUT

Low VFB=2.7V, RL=15kΩ to V

REF

0.7 1.1 V

■ Current Sense Section

Gain (Notes 3 & 4) 2.85 3.00 3.15 V/V
Maximum Input Signal V

COMP

=5V (Note 3) 0.9 1.0 1.1 V
PSRR 12≤VCC≤25V (Note 3) 70 dB
Input Bias Current -2 -10 µA
Delay to Output TJ=25˚C (Note 2) 150 300 ns

■ Output Section

Output Low Level I

SINK

=20mA 0.1 0.4 V

I

SINK

=200mA 1.5 2.2 V

Output High Level I

SOURCE

=20mA 13.0 13.5 V

I

SOURCE

=200mA 12.0 13.5 V

3

CS3842B/3843B

Electrical Characteristics: continued

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

CS-3842B CS-3843B

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Notes: 1. Adjust VCCabove the start threshold before setting at 15V.

2. These parameters, although guaranteed, are not 100% tested
in production.

3. Parameter measured at trip point of latch with VFB=0.

4. Gain defined as:

A =

; 0 ≤ V

Sense

≤ 0.8V.

∆V

COMP

∆V

Sense

Package Pin Description

PACKAGE PIN # PIN SYMBOL FUNCTION

8L PDIP/SO 14L SO Narrow

1 1 COMP Error amp output, used to compensate error amplifier

23 V

FB

Error amp inverting input

3 5 Sense Noninverting input to Current Sense Comparator

4 7 OSC Oscillator Timing Network with Capacitor to Ground, resistor

to V

REF

5 8 Gnd Ground

9 Pwr Gnd Output driver Ground

610V

OUT

Output drive pin

11 VCCPwr Output driver positive supply

712V

CC

Positive power supply

814V

REF

Output of 5V internal reference

2,4,6,13 NC No Connection

■ Output Section: continued

Rise Time T

J

=25˚C, CL=1nF (Note 2) 50 150 ns
Fall Time TJ=25˚C, CL=1nF (Note 2) 50 150 ns
Output Leakage UVLO Active, V

OUT

=0 -0.01 -10.00 µA

■ Total Standby Current

Start-Up Current 0.3 0.5 mA
Operating Supply Current VFB=V

Sense

=0V RT=10kΩ, CT=3.3nF 11 17 mA

VCCZener Voltage ICC=25mA 34 V

■ Under-Voltage Lockout Section

Start Threshold 14.5 16.0 17.5 7.8 8.4 9.0 V
Min. Operating After Turn On 8.5 10.0 11.5 7.0 7.6 8.2 V

Voltage

Undervoltage Lockout

During Undervoltage Lockout (Figure 1), the output driv­er is biased to a high impedance state. V

OUT

should be
shunted to ground with a resistor to prevent output leak­age current from activating the power switch.

PWM Waveform

To generate the PWM waveform, the control voltage from
the error amplifier is compared to a current sense signal
which represents the peak output inductor current
(Figure 2). An increase in V

CC

causes the inductor current
slope to increase, thus reducing the duty cycle. This is an
inherent feed-forward characteristic of current mode con­trol, since the control voltage does not have to change
during changes of input supply voltage.

When the power supply sees a sudden large output cur­rent increase, the control voltage will increase allowing
the duty cycle to momentarily increase. Since the duty

4

CS3842B/3843B

Test Circuit

Circuit Description

Typical Performance Characteristics:

Oscillator Duty Cycle vs R

T

Oscillator Frequency vs C

T

Figure 1: Typical Undervoltage Characteristics

.0005 .001 .002 .003 .005 .01 .02 .03 .04

800

900

FREQ. (kHz)

CT (µF)

700

600

500

400

300

200

100

.05

RT =1.5kΩ

RT =680Ω

RT =10kΩ

100 200 700 1k 2k 5k 7k 10k

80

90

DUTY CYCLE (%)

RT (Ω)

70
60
50
40

30
20
10

4k3k500400300

100

ERROR AMP

2N2222

100kΩ

4.7kΩ

1kΩ

ADJUST

4.7kΩ

5kΩ

Sense

ADJUST

R

T

COMP

V

FB

Sense

CS-3842B
CS-3843B

V

V

REF

V

OUT

CC

A

0.1µF

0.1µF

1kΩ
1W

V

REF

V

CC

V

OUT

V

CC

I

<15mA

CC

<0.5mA

ON/OFF Command

CS3842B CS3843B

V

16V 8.4V

ON

V

10V 7.6V

OFF

V

ONVOFF

to reset of IC

OSC

C

T

V

CC

Gnd

Gnd

Figure 3: Oscillator Timing Network and parameters

5

CS3842B/3843B

Figure 3: Oscillator

Sawtooth Mode

Triangular Mode

Figure 2: Timing Diagram for key CS-384XB parameters

V

CC

I

OUT

V

OUT

Switch

Current

EA Output

V

OSC

OSC

RESET

cycle tends to exceed the maximum allowed, to prevent
transformer saturation in some power supplies, the inter­nal oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator timing
components.

Setting the Oscillator

The oscillator timing capacitor, CT, is charged by V

REF

through RTand discharged by an internal current source
(Figure 3). During the discharge time, the internal clock
signal blanks out the output to the Low state, thus provid­ing a user selected maximum duty cycle clamp.

Charge and discharge times are determined by the general
formulas:

t

c

= RTCTln

t

d

= RTCTln

Substituting in typical values for the parameters in the
above formulas:

V

REF

= 5.0V, V

upper

= 2.7V, V

lower

= 1.0V, Id= 8.3mA,

then

t

c

≈ 0.5534RTC

T

td= RTCTln

The frequency and maximum duty cycle can be deter­mined from the Typical Performance Characteristics
graphs.

Grounding

High peak currents associated with capacitive loads neces­sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to ground in a single
point ground.

The transistor and 5kΩ potentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.

)

2.3 – 0.0083 R

T

4.0 – 0.0083 R

T

(

)

V

REF

– IdRT–V

lower

V

REF

– IdRT– V

upper

(

)

V

REF

– V

lower

V

REF

– V

upper

(

V

REF

R

T

OSC

C

T

Gnd

V

upper

V

lower

LARGE R

SMALL R

(≈10kΩ)

T

(≈700kΩ)

T

t

c

V

Internal Clock

V

Internal Clock

t

OSC

REF

d

6

D

Lead Count Metric English

Max Min Max Min
8 L PDIP 10.16 9.02 .400 .355
8 L SOIC Narrow 5.00 4.80 .197 .189

14L SOIC Narrow 8.75 8.55 .344 .337

Part Number Description

CS3842BGN8 8L PDIP
CS3842BGD8 8L SO Narrow
CS3842BGDR8 8L SO Narrow (tape & reel)
CS3842BGD14 14L SO Narrow
CS3842BGDR14 14L SO Narrow (tape & reel)
CS3843BGN8 8L PDIP
CS3843BGD8 8L SO Narrow
CS3843BGDR8 8L SO Narrow (tape & reel)
CS3843BGD14 14L SO Narrow
CS3843BGDR14 14L SO Narrow (tape & reel)

Thermal Data 8 L 8L 14 L

PDIP SO Narrow SO Narrow

RΘ

JC

typ 52 45 30 ˚C/W

RΘ

JA

typ 100 165 125 ˚C/W

Package Specification

PACKAGE DIMENSIONS IN mm (INCHES)

Ordering Information

PACKAGE THERMAL DATA

Rev. 6/23/99

CS3842B/3843B

© 1999 Cherry Semiconductor Corporation

Surface Mount Narrow Body (D); 150 mil wide

1.27 (.050) BSC

0.51 (.020)

0.33 (.013)

6.20 (.244)

5.80 (.228)

4.00 (.157)

3.80 (.150)

1.57 (.062)

1.37 (.054)

D

0.25 (0.10)

0.10 (.004)

1.75 (.069) MAX

1.27 (.050)

0.40 (.016)

REF: JEDEC MS-012

0.25 (.010)

0.19 (.008)

Plastic DIP (N); 300 mil wide

0.39 (.015)
MIN.

2.54 (.100) BSC

1.77 (.070)

1.14 (.045)

D

Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.

.203 (.008)

.356 (.014)

REF: JEDEC MS-001

3.68 (.145)

2.92 (.115)

8.26 (.325)

7.62 (.300)

7.11 (.280)

6.10 (.240)

.356 (.014)

.558 (.022)

Cherry Semiconductor Corporation reserves the right to
make changes to the specifications without notice. Please
contact Cherry Semiconductor Corporation for the latest
available information.