Datasheet CS3750ENF16 Datasheet (Cherry Semiconductor)

1

Features

OUT1A

Thermal

Shutdown

V

REF

Overvoltage

1/2 H -Bridge

Driver

with Current

Limit

RC Filter

for PWM Input

OUT1B C1

1/2 H -Bridge

Driver

with Current

Limit

DIRECTION

Control

1/2 H- Bridge

Driver

with Current

Limit

RC Filter

for PWM Input

1/2 H- Bridge

Driver

with Current

Limit

DIRECTION

Control

OUT2A OUT2B C2

Gnd

IN2DIR2IN1DIR1V

S1,2

■ 2 Independent NPN

H-Bridge Drivers

■ No Analog Trim Required

■ Used in Multiplexed

Systems

■ Quiet Gauge Operation

■ Programmable Slew

Rate Minimizes
Switching Noise

■ Fault Protection

Over Voltage

Thermal Shutdown

Short Circuit

Package Options

16 Lead PDIP

(internally fused leads)

CS3750

100mA Dual H-Bridge Air-Core

Gauge Driver

1

DIR1

C1

IN1

Gnd

Gnd

OUT1A

VS1

OUT1B

DIR2

C2

IN2

Gnd

Gnd

OUT2A

VS2

OUT2B

Description

Block Diagram

Absolute Maximum Ratings

The CS3750 is a dual H-bridge four
quadrant air-core gauge driver. The IC
provides all the functions necessary to
drive a tachometer or speedometer as
part of a microprocessor based multi­plexed system. Digital input control
eliminates the need for any analog cali­bration of the gauge.

The controlling microprocessor sends
out a PWM signal to each H bridge
driver input (IN1, IN2). The PWM sig­nal duty cycle is proportional to the
HÐbridge output. Output current

(100mA max) direction is controlled by
the DIRECTION input. PWM switch­ing noise is minimized at each half
bridge by an internal RC filter and
external programmable capacitor.

The CS3750 is protected against 50V
load dump, over voltage and thermal
runaway fault conditions. Any of these
faults causes the IC to shut down. Each
high side of the output driver is current
limited. A short circuit condition in one
driver does not affect the others.

CS3750

Supply Voltage .................................................................................7.5V to +16V

Internal Power Dissipation.....................................................Internally limited

Logic Input Voltages.......................................................................Ð0.3V to 6.5V

Junction Temperature Range ...................................................Ð40¡C to +150¡C

Storage Temperature Range.....................................................Ð55¡C to +165¡C

Lead Temperature Soldering

Wave Solder (through hole styles only)...........10 sec. max, 260¡C peak

Electrostatic Discharge (Human Body Model)............................................8kV

Rev. 7/20/95

Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: [phone] Fax: [phone]

Email: [e-mail]

Web Site: www.cherry-semi.com

A Company

¨

2

Electrical Characteristics: 7.5V <= VCC<=15V; -40¡C ² TA² +85¡C unless otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CS3750

Note 1: Time required for output signal to rise to 90% of its amplitude after input signal switches.
Note 2: Time required for output signal to decrease to 10% of its amplitude after input signal switches.

■ Output Stage

V

OUT

Saturation Voltage I

OUT

=100mA; VIN=0V 0.25 0.50 V

(Low Side) I

OUT

=1mA; VIN=0V 0.01 0.10 V

V

OUT

Offset Voltage VC=5V; I

OUT

=-30mA 15 50 mV

V

OUT

Saturation High Side VIN=5V;I

OUT

=-100mA VS-2 VS-1.5 VS V

Low Side VIN=0V;I

OUT

=-1mA 0.02 0.10 V

V

OUT

Differential VC=5V, I

OUT

=-100mA 100 mV
Matching Voltage
Supply Current VIN=V

DIR

=0; 23 45 mA

■ Input Stage

VINLOW VINdecreasing; V

DIR

=0V 0.8 1.9 V

HIGH V

IN

increasing; V

DIR

=0V 2.0 3.5 V

Hysteresis V

DIR

=0V 100 mV

IINLOW VIN=0.8V; V

DIR

=0V 20 100 µA

HIGH VIN=3.5V 0.4 100.0 µA

Output Slew Rate VIN=250Hz; R

LOAD

=150½ 0.2 0.8 V/us

with respect to input

Output Turn on Delay VIN=250Hz; R

LOAD

=150½, note 1 1.5 6 µs

with respect to input

Output Turn off Delay VIN=250Hz; R

LOAD

=150½, note 2 2.4 9 µs

with respect to input

■ Direction

V

DIR

LOW VIN=5V; V

DIR

decreasing 0.8 1.9 V

HIGH VIN=5V; V

DIR

increasing 2.0 3.5 V

Hysteresis VIN=5V 100 mV

I

DIR

LOW VIN=0V; V

DIR

=0.8V 40 100 µA

HIGH VIN=0V; V

DIR

=3.5V 0.4 100 µA

Output Slew Rate VIN=5V; f

DIR

=250Hz; C=0µF 0.2 1.5 V/µs

with respect to DIR

Output Fall Time VIN=0V; V

DIR

=0V; C=0µF 0.2 2.0 µs

with respect to DIR

Output Turn on Delay VIN=5V; R

LOAD

=150½

with respect to DIR V

DIR

=250Hz; C=0µF, note 1 1 6 µs

Output Turn off Delay VIN=5V; R

LOAD

=150½

with respect to DIR V

DIR

=250Hz; C=0µF, note 2 2.5 9 µs

■ Protection Functions

I

OUT

Current Limit VIN=5V 100 225 mA

(High Side Only)

Over Voltage Threshold VIN=5V 17.0 21.5 26.0 V

Hysteresis 0.5 V

Thermal Shutdown 160 ¡C

Hysteresis 20 ¡C

3

CS3750

Package Pin Description

PACKAGE PIN # PIN SYMBOL FUNCTION

16L PDIP (internally fused leads)

1 DIR1 CMOS compatible input pin controls direction of current

through OUT1

2 C1 RC filter capacitor for OUT1 connected to Ground

3 IN1 CMOS compatible input pin controls output OUT1A and 1B

4,5,12,13 Gnd Ground connection

6 OUT1A One half of H-bridge output stage 1

7 VS1 Supply voltage

8 OUT1B One half of H-bridge output stage 1

9 OUT2B One half of H-bridge output stage 2

10 VS2 Supply voltage

11 OUT2A One half of H-bridge output stage 2

14 IN2 CMOS compatible input pin controls output OUT2A and 2B

15 C2 RC filter capacitor for OUT2 connected to Ground

16 DIR2 CMOS compatible input pin controls direction of current

through OUT2

Each output stage contains 4 power NPN transistors
arranged in a traditional H bridge configuration. Current
flow through the two outputs (OUTxA, OUTxB) in each
H-bridge is controlled by the logic signal DIRx.

PWM input signals from the microprocessor, are filtered
on chip and sent to the output stage. The duty cycle of the
PWM signal is proportional to output voltage. The RC fil­ter reduces the noise of the PWM input signal by slowing
its slew rate: i.e., the output signal is converted from a
square wave to an exponential sawtooth waveform. An
external capacitor (Cx) controls the slew rate for each H
bridge.

When the voltage on the control pin (INx) is low, both
halves of the H bridge are off (Table 1). When INx is high,
DIR controls the flow of current through the H-bridge. If
DIRx=0, current flows from OUTxA out to the coil and
back in through OUTxB. If DIRx=1, current flows from
OUTxB out to the coil and back in through OUTxA.

Table 1. Logic Control of H-Bridge

The high side driver transistor in each H-bridge is current
limited as a protection against a short circuit fault condi­tion. If an over voltage or a thermal runaway fault condi­tions occurs, all outputs shut down.

Output Stage

Motor Direction Control

Protection

Input Direction Outputs

INX DIRX OUTxA OUTxB

0X00

1010

1101

Circuit Description

Application Diagram

1

IN1

C1

Gnd

Gnd

OUT1B

VS1

DIR1

C2

Gnd

Gnd

OUT2A

VS2

CS3750

DIR2

*C

1

COIL1 COIL2

Air Core

Gauge

Circular

Speedometer

*C

2

Microprocessor

I/O

* 0.047mF

V

BAT

OUT1A

OUT2B

IN2

Part Number Description

CS3750ENF16 16L PDIP (internally fused leads)

4

Thermal Data 16L PDIP

(internally fused leads)

R

QJC

typ 15 ûC/W

R

QJA

typ 50 ûC/W

Package Specification

PACKAGE DIMENSIONS IN mm (INCHES)

Ordering Information

PACKAGE THERMAL DATA

Rev. 7/20/95

CS3750

D

Lead Count Metric English

Max Min Max Min

16L PDIP 19.69 18.67 .775 .735
(internally fused leads)

© 1999 Cherry Semiconductor Corporation

Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.

Plastic DIP (N); 300 mil wide

0.39 (.015)
MIN.

2.54 (.100) BSC

1.77 (.070)

1.14 (.045)

D

Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.

.203 (.008)

.356 (.014)

REF: JEDEC MS-001

3.68 (.145)

2.92 (.115)

8.26 (.325)

7.62 (.300)

7.11 (.280)

6.10 (.240)

.356 (.014)

.558 (.022)