Datasheet CS2841BEN8, CS2841BEDR14, CS2841BED14 Datasheet (Cherry Semiconductor)

Page 1
1
Optimized for
Off-line
Control
Internally Trimmed
Temperature Compensated Oscillator
Maximum Duty-cycle
Clamp
V
REF
Stabilized before
Output Stage Enabled
Low Start-up Current
Pulse-by-pulse Current
Limiting
Improved Undervoltage
Lockout
Double Pulse Suppression
1% Trimmed Bandgap
Reference
High Current Totem Pole
Output
Package Options
8 Lead PDIP
10
7
14
13
12
8
1
2
3
4
5
6
11
9
COMP
NC
V
FB
NC
Sense
NC
OSC
V
REF
NC V
CC
V
CC
Pwr
V
OUT
Pwr Gnd Gnd
14 Lead SO Narrow
CS2841B
Automotive Current Mode PWM
Control Circuit
CS2841B
Description
The CS2841B provides all the nec­essary features to implement off­line fixed frequency current-mode control with a minimum number of external components.
The CS2841B (a variation of the CS-2843A) is designed specifically for use in automotive operation. The low start threshold voltage of
8.0V (typ), and the ability to sur­vive 40V automotive load dump transients are important for auto­motive subsystem designs. The CS-2841 series has a history of
quality and reliability in automo­tive applications.
The CS2841B incorporates a preci­sion temperature-controlled oscil­lator with an internally trimmed discharge current to minimize vari­ations in frequency. Duty-cycles greater than 50% are also possible. On board logic ensures that V
REF
is stabilized before the output stage is enabled. Ion implant resistors provide tighter control of under­voltage lockout.
Block Diagram
Absolute Maximum Ratings
Supply Voltage (Low Impedance Source)...................................................40V
Output Current ...............................................................................................±1A
Output Energy (Capacitive Load) .................................................................5µJ
Analog Inputs (V
FB
, Sense) ............................................................-0.3V to 5.5V
Error Amp Output Sink Current...............................................................10mA
Lead Temperature Soldering
Wave Solder (through hole styles only) ..........10 sec. max, 260°C peak
Reflow (SMD styles only)...........60 sec. max above 183°C, 230°C peak
Features
Rev. 6/23/99
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: info@cherry-semi.com
Web Site: www.cherry-semi.com
A Company
®
V
Gnd
OSC
V
COMP
Sense
CC
8.0V/7.4V
+
FB
Amplifier
2.50V
Oscillator
Error
Undervoltage
Lock-out Circuit
V
C
2 R
R
Set/
Reset
Reference
Output Enable
1 V
5V
Current
Sensing
Comparator
Internal
Bias
NOR
S
PWM
R
Latch
VCC Pwr
V
REF
V
OUT
Pwr Gnd
1
COMP
2
V
FB
3
Sense
4
OSC
8
V
7
V
6
V
5
Gnd
CC
OUT
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Electrical Characteristics: d -40≤TA≤85˚C RT=680k, CT=0.022µF for triangular mode, VCC=15V (Note 1),
R
T
=10k, CT=3.3nF for sawtooth mode (See Fig. 3), unless otherwise stated.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CS2841B
Notes: 1. Adjust Vccabove the start threshold before setting at 15V. 3. Parameter measured at trip point of latch with VFB=0.
2.These parameters, although guaranteed, are not 100% tested in production. 4. Gain defined as:
A = ; 0 V
Sense
0.8V.
V
COMP
V
Sense
Reference Section
Output Voltage TJ=25˚C, I
OUT
=1mA 4.90 5.00 5.10 V Line Regulation 8.4≤VCC≤16V 6 20 mV Load Regulation 1≤I
OUT
20mA 6 25 mV Temperature Stability (Note 2) 0.2 0.4 mV/˚C Total Output Variation Line, Load, Temp. (Note 2) 4.82 5.18 V Output Noise Voltage 10Hz≤f≤10kHz, TJ=25˚C (Note 2) 50 µV Long Term Stability TA=125˚C, 1000 Hrs. (Note 2) 5 25 mV Output Short Circuit TA=25˚C -30 -100 -180 mA
Oscillator Section
Initial Accuracy Sawtooth Mode: (See Fig. 3)TJ=25˚C 47 52 57 kHz
Sawtooth Mode: -40˚CTA≤+85˚ 44 52 60 kHz
Triangular Mode (See Fig. 3) TJ=25˚C 44 52 60 kHz Voltage Stability 8.4VVcc≤16V 0.2 1.0 % Temperature Stability Sawtooth Mode T
MIN≤TA≤TMAX
5%
Triangular Mode T
MIN≤TA≤TMAX
8%
(Note 2) Amplitude V
OSC
(peak to peak) 1.7 V
Discharge current TJ=25˚C 7.4 8.3 9.2 mA
T
MIN≤TA≤TMAX
7.2 9.4 mA
Error Amp Section
Input Voltage V
COMP
=2.5V 2.42 2.50 2.58 V Input Bias Current VFB=0V -0.3 -2.0 µA A
VOL
2V
OUT
4V 65 90 dB Unity Gain Bandwidth (Note 2) 0.7 1.0 MHz PSRR 8.4V≤VCC≤16V 60 70 dB Output Sink Current VFB=2.7V, V
COMP
=1.1V 2 6 mA
Output Source Current V
FB
=2.3V, V
COMP
=5V -0.5 -0.8 mA
V
OUT
High VFB=2.3V, RL=15kto ground 5 6 V
V
OUT
Low VFB=2.7V, RL=15kto V
REF
0.7 1.1 V
Current Sense Section
Gain (Notes 3 & 4) 2.85 3.00 3.15 V/V Maximum Input Signal V
COMP
=5V (Note 3) 0.9 1.0 1.1 V PSRR 12V≤VCC≤25V (Note 3) 70 dB Input Bias Current V
Sense
=0V -2 -10 µA
Delay to Output T
J
=25˚C (Note 2) 150 300 ns
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CS2841B
Electrical Characteristics:
continued
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output Section
Output Low Level I
SINK
=20mA 0.1 0.4 V
I
SINK
=200mA 1.5 2.2 V
Output High Level I
SOURCE
=20mA 13.0 13.5 V
I
SOURCE
=200mA 12.0 13.5 V
Rise Time T
J
=25˚C, CL=1nF (Note 2) 50 150 ns
Fall Time T
J
=25˚C, CL=1nF (Note 2) 50 150 ns
Output Leakage Undervoltage Active, V
OUT
=0 -0.01 -10.00 µA
Total Standby Current
Start-Up Current 0.5 1.0 mA Operating Supply Current ICCVFB=V
Sense
=0V, RT=10kΩ, CT=3.3nF 11 17 mA
Under-Voltage Lockout Section
Start Threshold 7.6 8.0 8.4 V Min. Operating Voltage After Turn On 7.0 7.4 7.8 V
Package Pin Description
PACKAGE PIN # PIN SYMBOL FUNCTION
8L PDIP 14L SO Narrow
1 1 COMP Error amp output, used to compensate error amplifier
23 V
FB
Error amp inverting input
3 5 Sense Noninverting input to Current Sense Comparator
4 7 OSC Oscillator timing network with Capacitor to Ground, resistor
to V
REF
5 8 Gnd Ground
9 Pwr Gnd Output driver Ground
610V
OUT
Output drive pin
11 VCCPwr Output driver positive supply
712V
CC
Positive power supply
814V
REF
Output of 5V internal reference
2,4,6,13 NC No Connection
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CS2841B
V
REF
V
CC
V
O
1k 1W
0.1µF
0.1µF
V
REF
V
CC
V
OUT
Gnd
V
FB
Sense
OSC
COMP
5k
100k
4.7k
1k
Error Amp
Adjust
4.7k
Sense
Adjust
R
T
2N2222
C
T
Gnd
A
Test Circuit
Undervoltage Lockout
During Undervoltage Lockout (Figure 1), the output driv­er is biased to a high impedance state. The output should be shunted to ground with a resistor to prevent output leakage current from activating the power switch.
PWM Waveform
To generate the PWM waveform, the control voltage from the error amplifier is compared to a current sense signal which represents the peak output inductor current (Figure
2). An increase in VCCcauses the inductor current slope to increase, thus reducing the duty cycle. This is an inherent feed-forward characteristic of current mode control, since the control voltage does not have to change during changes of input supply voltage.
When the power supply sees a sudden large output cur­rent increase, the control voltage will increase allowing the duty cycle to momentarily increase. Since the duty cycle tends to exceed the maximum allowed to prevent trans-
Circuit Description
Typical Performance Characteristics:
.0005 .001 .002 .003 .005 .01 .02 .03 .04
800
900
FREQ. (kHz)
CT (µF)
700
600
500
400
300
200
100
.05
RT =1.5k
RT =680
RT =10k
100 200 700 1k 2k 5k 7k 10k
80
90
DUTY CYCLE (%)
RT ()
70 60 50 40
30 20 10
4k3k500400300
100
Oscillator Duty Cycle vs R
T
Oscillator Frequency vs C
T
Figure 1: Typical Undervoltage Characteristics
V
CC
V
= 8.0V
ON
V
= 7.4V
OFF
I
CC
7.4V 8.0V
<15mA
<1mA
ON/OFF Command
to reset of IC
V
CC
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5
former saturation in some power supplies, the internal oscillator waveform provides the maximum duty cycle clamp as programmed by the selection of OSC compo­nents.
Setting the Oscillator
Oscillator timing capacitor, CT, is charged by V
REF
through
R
T
and discharged by an internal current source. During the discharge time, the internal clock signal blanks out the output to the Low state, thus providing a user selected maximum duty cycle clamp. Charge and discharge times are determined by the general formulas:
t
c
= RTCTln
t
d
= RTCTln
Substituting in typical values for the parameters in the above formulas:
V
REF
= 5.0V, V
upper
= 2.7V, V
lower
= 1.0V, Id= 8.3mA
tc≈ 0.5534RTC
T
td= RTCTln
The frequency and maximum duty cycle can be deter­mined from the Typical Performance Characteristic graphs.
Grounding
High peak currents associated with capacitive loads neces­sitate careful grounding techniques. Timing and bypass capacitors should be connected close to Gnd pin in a sin­gle point ground.
The transistor and 5kpotentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Sense.
)
2.3 - 0.0083 R
T
4.0 - 0.0083 R
T
(
)
V
REF
- IdRT- V
lower
V
REF
- IdRT- V
upper
(
)
V
REF
- V
lower
V
REF
- V
upper
(
CS2841B
Circuit Description: continued
Sawtooth Mode
Triangular Mode
OSC
Figure 2: Timing Diagram for key CS2841B parameters
Figure 3: Oscillator Timing Network and parameters
Timing parameters
OSC
RESET
EA Output
Switch
Current
V
CC
I
O
V
O
V
REF
R
T
OSC
C
T
Gnd
LARGE R
SMALL RT (700k)
V
V
upper
lower
(10k)
T
t
c
t
d
V
OSC
Internal Clock
V
OSC
Page 6
D
Lead Count Metric English
Max Min Max Min 8 Lead PDIP 10.16 9.02 .400 .355 14 Lead SO Narrow 8.75 8.55 .344 .337
6
Rev. 6/23/99
CS2841B
Part Number Description
CS2841BEN8 8L PDIP CS2841BED14 14L SO Narrow CS2841BEDR14 14L SO Narrow
(tape & reel)
Ordering Information
Thermal Data 8 L 14 L
PDIP SO Narrow
R
ΘJC
typ 52 30 ˚C/W
R
ΘJA
typ 100 125 ˚C/W
Package Specification
PACKAGE DIMENSIONS IN mm (INCHES)
PACKAGE THERMAL DATA
© 1999 Cherry Semiconductor Corporation
Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information.
1.27 (.050) BSC
0.51 (.020)
0.33 (.013)
6.20 (.244)
5.80 (.228)
4.00 (.157)
3.80 (.150)
1.57 (.062)
1.37 (.054)
D
0.25 (0.10)
0.10 (.004)
1.75 (.069) MAX
1.27 (.050)
0.40 (.016)
REF: JEDEC MS-012
0.25 (.010)
0.19 (.008)
Surface Mount Narrow Body (D); 150 mil wide
Plastic DIP (N); 300 mil wide
0.39 (.015) MIN.
2.54 (.100) BSC
1.77 (.070)
1.14 (.045)
D
Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same.
.203 (.008)
.356 (.014)
REF: JEDEC MS-001
3.68 (.145)
2.92 (.115)
8.26 (.325)
7.62 (.300)
7.11 (.280)
6.10 (.240)
.356 (.014)
.558 (.022)
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