z Low Start-up Current (about 8µA)
z Low Operating Current (about 2mA)
z Current Mode Operation
z Under Voltage Lockout (UVLO)
z Built-in Synchronized Slope
Compensation
z Programmable PWM Frequency
z Audio Noise Free Operation
z
Leading edge Blanking on Sense input
Applications
z Switching AC/DC Adaptor
z Battery Charger
General Description
The CR6850 is a highly integrated low cost
current mode PWM controller, which is ideal
for small power current mode of offline
AC-DC fly-back converter applications.
Making use of external resistors, the IC
changes the operating frequency and
automatically enters the PFM/CRM (Cycle
Reset Mode) under light-load/zero-load
conditions. This can minimize standby
power consumption and achieve
green-power functions. With a very low
start-up current, the CR6850 could use a
large value start-up resistor (2Mohm).
Built-in synchronized slope compensation
enhances the stability of the system and
avoids sub-harmonic oscillation. Dynamic
peak limiting circuit minimizes output power
change caused by delay time of the system
CR6850
z Constant output power limiting for
universal AC input
z Cycle-by-cycle current limiting
z Soft clamped gate output voltage 16.8V
z Over voltage protect 25.5V
z High-Voltage CMOS Process with ESD
z SOT-23-6L、SOP8 & DIP-8 Pb-Free
Packaging
z
Compatible with SG5701 & SG5848 &
LD7535 & OB2262/63
z Open Frame Switching Power Supply
z 384X Replacement
over a universal AC input range. Leading
edge blanking circuit on current sense input
could remove the signal glitch due to
snubber circuit diode reverse recovery and
thus greatly reduces the external
component count and system cost in the
design. Pulse-by-pulse current limiting
ensures safe operation even during
short-circuit.
The CR6850 offers more protection like
OVP (Over Voltage Protection) and OCP
(Over current protection). The CR6850’s
output driver is soft clamped to maximum
16.8V to protect the power MOSFET.
Excellent EMI performance is achieved soft
switching control at the totem pole gate
driver output. CR6850 is offered in
SOT-23-6, SOT-8 and DIP-8 packages.
Dec, 2006 V1.5 1/15
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Page 2
CR6850
CR68XX Series
Part
Number
CR6848
CR6850
CR6851
PWM
Frequency
External
Adjustable
External
Adjustable
External
Adjustable
DIP-8、SOP8
SOT-23-6L
DIP-8、SOP8
SOT-23-6L
DIP-8、SOP8
SOT-23-6L
TYPICAL APPLICATION
Package Description
PWM&PF&CRM 、 Current Mode 、 Slope
Compensation Leading-edge Blanking 、 Gate
Clamped、Over-voltage Protection、Over-current
Protection、 Soft Drive.
With All Functions of CR6848 、 Gate soft
Clamped
With All Functions of CR6850、Frequency jitter、
Soft start、Sense Fault Protect、OLP、SCP、
OTP
Pin Assignment
Pin Descriptions
Name Description
GND GND Pin
FB
RI
SEN
VDD Supply voltage pin.
GATE
Analog Input. Voltage feedback pin (same as the COMP pin in UC384X),
This pin is to program the switching frequency. By connecting a resistor
to ground to set the switching frequency.
Current sense pin, connect to sense the MOSFET current.
Symbol Parameter Conditions Min.Typ. Max. Unit
Supply Voltage (VDD Pin)
I
ST
Startup Current 8
µA
VFB=0V 2.9 mA
I
VDD
VDD
VD
SS
CLAMP
Operating Current
Turn-on Threshold Voltage 15.3 V
ON
Turn-off Threshold Voltage 9.8 V
OFF
VDD Clamp Voltage I
VFB=3V 1.9 mA
=Open 1.44 mA
V
FB
=20mA 25.5 V
VDD
Voltage Feedback (FB Pin)
IFB Short Circuit Current VFB=0V 1.68 mA
VFB Open Loop Voltage VFB=Open 4.7 V
I
Enter PFM&PWM, FB current 1.2 mA
PFM
I
CRM
Enter CRM, FB current 1.5 mA
V
PFM Threshold V
PFM
FB
1.15 V
Current Sensing (SEN Pin)
V
V
TH_L
TH_H
Minimum Voltage Lever 0.550.65 0.75 V
Maximum Voltage Lever 0.750.85 0.95 V
TPD Delay to Output 300 ns
RCS Input Impedance
50 KΩ
Oscillator (RI Pin)
F
Normal Frequency RI=100Kohm 60 65 70 KHz
OSC
F
PFM Frequency RI=100Kohm 20.6 KHZ
PFM
DC
Maximum Duty Cycle RI=100Kohm 77 %
MAX
ΔF
T
Frequency Temp. Stability
TEMP
Leading-Edge Blanking Time300 nS
BLANK
-30-85
℃
5 %
GATE Drive Output (GATE Pin)
V
OL
V
OH
Output Low Level VDD=15V, IO=20mA 1 V
Output High Level VDD=15V, IO=20mA8 V
VG
T
T
CLAMP
Rising Time
R
Falling Time CL=1000pF 120 ns
F
CL=1000pF 420 ns
Output Clamp Voltage VDD=20V 16.8 17.8 V
Dec, 2006 V1.5 4/15
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Page 5
CR6850
TYPICAL CHARACTERISTICS
VDD startup Current VS Temperature
VDD Operation Current VS Temperature
VDD (OFF) VS Temperature
PWM frequency VS Temperature
VDD (ON) VS Temperature
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Duty cycle VS Temperature
Page 6
CR6850
F
VS RI Resistor
OSC
OVP VS Temperature
F
VS FB Current
OSC
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Page 7
CR6850
OPERATION DESCRIPTION
Current Model
Compared to voltage model control,
current model control has a current
feedback loop. When the voltage of the
sense resistor peak current of the primary
winding reaches the internal setting value
TH
, comparator reverse, register reset and
V
power MOSFET cut-off. So that to detect
and modulate the peak current cycle by
cycle could control the output of the power
supply. The current feedback has a good
linear modulation rate and a fast input and
output dynamic impact avoid the pole that
the output filter inductance brings and the
second class system descends to first class
and so it widens the frequency range and
optimizes overload protection and short
circuit protection.
Startup Current and Under Voltage
Lockout
The startup current of CR6850 is set to be
very low so that a large value startup
resistor can therefore be used to minimize
the power loss. For AC to DC adaptor with
universal input range design, a 2 MΩ, 1/8 W
startup resistor and a 10uF/25V VDD hold
capacitor could be used.
The turn-on and turn-off threshold of the
CR6850 is designed to 15.3V/9.8V. During
startup, the hold-up capacitor must be
charge to 15.3V through the startup resistor.
The hysteresis is implemented to prevent
the shutdown from the voltage dip during
startup.
Internal Bias and OSC Operation
A resistor connected between RI pin and
GND pin set the internal constant current
source to charge or discharge the internal
fixed cap. The charge time and discharge
time determine the internal clock speed and
the switching frequency. Increasing the
resistance will reduce the value of the input
current and reduce the switching frequency.
The relationship between RI pin and PWM
switching frequency follows the below
equation within the RI allowed range.
F
OSC
For example, a 100kΩ resistor RI could
generate a 50uA constant current and a
65kHz PWM switching frequency. The
6500
=
)(
KRI
Ω
kHz
)(
suggested operating frequency range of
CR6850 is within 50KHz to 100KHz.
Green Power Operation
The power dissipation of switching mode
power supply is very important in zero load
or light load condition. The major dissipation
result from conduction loss、switching loss
and consume of the control circuit. However,
all of them related to the switching
frequency. There are many difference
topologies has been implemented in
different chip. The basic operation theory of
all these approaches intended to reduce the
switching frequency under light-load or
no-load condition.
CR6850`s green power function adapts
PWM、PFM and CRM combining modulation.
When RI resistor is 100k, the PWM
frequency is 65kHz in medium or heavy load
operation. Through modifying the pulse
width, CR6850 could control output voltage.
The current of FB pin increases when the
load is in light condition and the internal
mode controller enters PFM&PWM when
the feedback current is over 1.2mA. The
operation frequency of oscillator is to
descend gradually. The invariable frequency
of oscillator is 21kHz when the feedback
current is over 1.35mA. To decrease the
standby consumption of the power supply ,
Chip-Rail introduces the Cycle Reset Mode
technology;If the feedback current were
over 1.5mA, mode controller of CR6850
would reset internal register all the time and
cut off the gate pin, while the output voltage
is lower than the set value, it would set
register, gate pin operating again. Although
the frequency of the internal OSC is
invariable, the register would reset some
pulses so that the practical frequency is
decreased at the gate pin.
CR6850 Green-Power Function
Dec, 2006 V1.5 7/15
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Page 8
CR6850
Internal Synchronized Slop
Compensation
Although there are more advantages of the
current mode control than conventional
voltage mode control, there are still several
drawbacks of peak-sensing current-mode
converter. Especially the open loop
instability when it operates in higher than
50% of the duty-cycle. CR6850 is introduced
an internal slope compensation adding
voltage ramp to the current sense input
voltage for PWM generation to solve this
problem. It improves the close loop stability
greatly at CCM, prevents the sub-harmonic
oscillation and thus reduces the output
ripple voltage.
V
SLOP
DUTY
DUTY
MAX
DUTY
×=×=4389.033.0
primary wind inductance.
85VAC to
264VAC.
To guarantee the output
V
ranges from
IN
power is a constant for universal input AC
voltage, there is a dynamic peak limit circuit
to compensate the system delay T that the
system delay brings on.
Leading-edge Blanking (LEB)
Each time the power MOSFET is switched
on, a turn-on spike will inevitably occur at
the sense pin, which would disturb the
internal signal from the sampling of the
R
. There is a 300n sec leading edge
SENSE
blanking time built in to avoid the effect of
the turn-on spike and the power MOSFET
cannot be switched off during this time. So
that the conventional external RC filtering on
sense input is no longer required.
Current Sensing & Dynamic peak
limiting
The current flowing by the power MOSFET
comes in to being a voltage V
sense pin cycle by cycle, which compares to
the internal reference voltage, controls the
reverse of the internal register, limits the
peak current IMAX of the primary of the
transformer. The energy
deposited by the transformer. So adjusting
the R
the power supple mode. The current flowing
by the power MOSFET has an extra value
I×=∆
that the current detected from the sense pin
to power MOSFET cut off in the CR6850
(Among these, V
voltage of the transformer and L
Dec, 2006 V1.5 8/15
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SENSE
1
2
can set the Max output power of
SENSE
V
IN
L
P
due to the system delay T
T
D
is the primary winding
IN
on the
ILE××=
MAX
is the
P
Over Voltage Protection (OVP)
There is a 25.5V over-voltage protection
circuit in the CR6850 to improve the
credibility and extend the life of the chip. The
GATE is to shutdown immediately when the
voltage of the VDD is over 25.5V and the
2
voltage of VDD is to descend rapidly.
Gate Driver & Soft Clamped
CR6850’ output designs a totem pole to
drive a periphery power MOSFET. The dead
time is introduced to minimize the transfixion
current when the output is drove. The
NMOS is shut off when the other NMOS is
turned on. The novel soft clamp technology
is introduced to protect the periphery power
MOSFET from breaking down and current
saturation of the Zener.
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Page 9
CR6850
PACKAGE DEMENSIONS
DIP-8L
Dimensions
Symbol
A
A1 0.381
A2 3.175 3.302 3.429 0.125 0.130 0.135
b
b1
D 9.017 9.271 10.160 0.355 0.365 0.400
E
E1 6.223 6.350 6.477 0.245 0.250 0.255
e
L 2.921 3.302 3.810 0.115 0.130 0.150
eB 8.509 9.017 9.525 0.335 0.355 0.375
θ˚ 0˚ 7˚ 15˚ 0˚ 7˚ 15˚
Dec, 2006 V1.5 9/15
Min. Typ. Max. Min. Typ. Max.
Millimeters
1.524
0.457
7.620
2.540
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5.334
0.015
web:www.kingkeyelec.com
Inches
0.210
0.060
0.018
0.300
0.100
Page 10
CR6850
SOT-23-6L
Symbol
A 0.700 1.000 0.028 0.039
A1 0.000 0.100 0.000 0.004
B 1.397 1.803 0.055 0.071
b 0.300 0.559 0.012 0.022
C 2.591 3.000 0.102 0.118
D 2.692 3.099 0.106 0.122
e 0.838 1.041 0.033 0.041
H 0.080 0.254 0.003 0.010
L 0.300 0.610 0.012 0.024
Dimensions In MillimetersDimensions In Inches
Min Max Min Max
SOP-8L
Dec, 2006 V1.5 10/15
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Page 11
CR6850
Dimensions DISCLAIMERS
Millimeter
0.381X45
Symbol
A 1.346
A1 0.101
b
c
D 4.648
E 3.810
e 1.016 1.270 1.524 0.040 0.050 0.060
F
H 5.791
L 0.406
θ˚
Min. Typ. Max. Min. Typ. Max.
0°
0.406
0.203
°
1.752 0.053
0.254 0.004
4.978 0.183
3.987 0.150
6.197 0.228
1.270 0.016
8° 0°
Inch
0.016
0.008
0.015X45
°
0.069
0.010
0.196
0.157
0.244
0.050
8°
Dec, 2006 V1.5 11/15
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Page 12
CR6850
REFERENCE CIRCUIT 1
CR6850 drives a periphery Power MOSFET.
5V/6A 30W Power Supply
Quantity Part Number Description Quantity Part Number Description