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查询COP87L84EGM-XE供应商
COP884CG/COP888CG 8-Bit Microcontroller
with UART and Three Multi-Function Timers
General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconduc-
2
tor’s M
CMOSTMprocess technology. The COP888CG is a
member of this expandable 8-bit core processor family of
microcontrollers. (Continued)
Key Features
Y
Full duplex UART
Y
Three 16-bit timers, each with two 16-bit registers supporting:
Ð Processor independent PWM mode
Ð External event counter mode
Ð Input capture mode
Y
Quiet design (low radiated emissions)
Y
4 kbytes of on-chip ROM
Y
192 bytes of on-chip RAM
Additional Peripheral Features
Y
Idle timer
Y
Multi-Input Wake Up (MIWU) with optional interrupts (8)
Y
Two analog comparators
Y
WATCHDOGTMand Clock Monitor logic
Y
MICROWIRE/PLUSTMserial I/O
I/O Features
Y
Memory mapped I/O
Y
Software selectable I/O options (TRI-STATEÉoutput,
push-pull output, weak pull-up input, high impedance input)
Y
High current outputs
August 1996
Y
Schmitt trigger inputs on Port G
Y
Packages:
Ð 44 PLCC with 40 I/O pins
Ð 40 DIP with 36 I/O pins
Ð 28 DIP with 24 I/O pins
Ð 28 SO with 24 I/O pins
CPU/Instruction Set Feature
Y
1 ms instruction cycle time
Y
Fourteen multi-source vectored interrupts servicing
Ð External interrupt with selectable edge
Ð Idle timer T0
Ð Three timers (each with 2 interrupts)
Ð MICROWIRE/PLUS
Ð Multi-Input WAke Up
Ð Software trap
Ð UART (2)
Ð Default VIS (default interrupt)
Y
Versatile and easy to use instruction set
Y
8-bit Stack Pointer (SP)Ðstack in RAM
Y
Two 8-bit register indirect data memory pointers (B, X)
Fully Static CMOS
Y
Low current drain (typicallyk1 mA)
Y
Single supply operation: 2.5V to 6.0V
Y
Temperature range:b40§Ctoa85§C
Development Support
Y
Emulation and OTP devices
Y
Real time emulation and full program debug offered by
MetaLink Development System
COP884CG/COP888CG 8-Bit Microcontroller with UART and Three Multi-Function Timers
Block Diagram
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS
iceMASTER
C
1996 National Semiconductor Corporation RRD-B30M106/Printed in U. S. A.
TM
,M2CMOSTM, COP8TMmicrocontrollers, MICROWIRETMand WATCHDOGTMare trademarks of National Semiconductor Corporation.
TM
is a trademark of MetaLink Corporation.
TL/DD/9765
FIGURE 1. Block Diagram
TL/DD/9765– 1
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General Description (Continued)
They are fully static parts, fabricated using double-metal silicon gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE/PLUS serial
I/O, three 16-bit timer/counters supporting three modes
(Processor Independent PWM generation, External Event
counter, and Input Capture mode capabilities), full duplex
UART, two comparators, and two power savings modes
(HALT and IDLE), both with a multi-sourced wakeup/interrupt capability. This multi-sourced interrupt capability may
Connection Diagrams
Plastic Chip Carrier
also be used independent of the HALT or IDLE modes.
Each I/O pin has software selectable configurations. The
device operates over a voltage range of 2.5V to 6V. High
throughput is achieved with an efficient, regular instruction
set operating at a maximum of 1 ms per instruction rate.
The device has reduced EMI emissions. Low radiated emissions are achieved by gradual turn-on output drivers and
internal I
filters on the chip logic and crystal oscillator.
CC
Dual-In-Line Package
Top View
TL/DD/9765– 2
Order Number COP888CG-XXX/V
See NS Plastic Chip Package Number V44A
Order Number COP884CG-XXX/N or COP884CG-XXX/WM
See NS Molded Package Number N28A OR M28B
FIGURE 2a. Connection Diagrams
Top View
TL/DD/9765– 4
Order Number COP888CG-XXX/N
See NS Molded Package Number N40A
Dual-In-Line Package
TL/DD/9765– 5
Top View
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Connection Diagrams (Continued)
Pinouts for 28-, 40- and 44-Pin Packages
Port Type Alt. Fun Alt. Fun
L0 I/O MIWU 11 17 17
L1 I/O MIWU CKX 12 18 18
L2 I/O MIWU TDX 13 19 19
L3 I/O MIWU RDX 14 20 20
L4 I/O MIWU T2A 15 21 25
L5 I/O MIWU T2B 16 22 26
L6 I/O MIWU T3A 17 23 27
L7 I/O MIWU T3B 18 24 28
G0 I/O INT 25 35 39
G1 WDOUT 26 36 40
G2 I/O T1B 27 37 41
G3 I/O T1A 28 38 42
G4 I/O SO 1 3 3
G5 I/O SK 2 4 4
G6 I SI 3 5 5
G7 I/CKO HALT Restart 4 6 6
D0 O 19 25 29
D1 O 20 26 30
D2 O 21 27 31
D3 O 22 28 32
I0 I 7 9 9
I1 I COMP1IN
I2 I COMP1IN
I3 I COMP1OUT 10 12 12
I4 I COMP2IN
I5 I COMP2IN
I6 I COMP2OUT 15 15
I7 I 16 16
D4 O 29 33
D5 O 30 34
D6 O 31 35
D7 O 32 36
C0 I/O 39 43
C1 I/O 40 44
C2 I/O 1 1
C3 I/O 2 2
C4 I/O 21
C5 I/O 22
C6 I/O 23
C7 I/O 24
V
CC
GND 23 33 37
CKI 5 7 7
RESET
28-Pin 40-Pin 44-Pin
Pack. Pack. Pack.
b
a
b
a
81010
91111
13 13
14 14
688
24 34 38
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Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
Voltage at Any Pin
Total Current into V
DC Electrical Characteristics
)7V
CC
Pin (Source) 100 mA
CC
b
0.3V to V
a
CC
b
40§CsT
0.3V
Parameter Conditions Min Typ Max Units
Operating Voltage 2.5 6 V
Power Supply Ripple (Note 1) Peak-to-Peak 0.1 V
Supply Current (Note 2)
e
CKI
10 MHz V
e
CKI
4 MHz V
CKIe4 MHz V
e
CKI
1 MHz V
HALT Current (Note 3) V
e
6V, t
CC
e
6V, t
CC
e
4.0V, t
CC
e
4.0V, t
CC
e
6V, CKIe0 MHz
CC
e
V
4.0V, CKIe0 MHz
CC
c
c
IDLE Current
e
CKI
10 MHz V
e
CKI
4 MHz V
CKIe1 MHz V
CC
CC
CC
e
e
e
6V, t
6V, t
4.0V, t
c
c
Input Levels
RESET
Logic High 0.8 V
Logic Low 0.2 V
CKI (External and Crystal Osc. Modes)
Logic High 0.7 V
Logic Low 0.2 V
All Other Inputs
Logic High 0.7 V
Logic Low 0.2 V
Hi-Z Input Leakage V
Input Pullup Current V
CC
CC
e
6V
e
6V, V
G and L Port Input Hysteresis 0.35 V
Output Current Levels
D Outputs
Source V
Sink V
All Others
Source (Weak Pull-Up Mode) V
Source (Push-Pull Mode) V
Sink (Push-Pull Mode) V
TRI-STATE Leakage V
Note 1: Rate of voltage change must be less then 0.5 V/ms.
Note 2: Supply current is measured after running 2000 cycles with a crystal/resonator oscillator, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V
as outputs and set high. The D port set to zero. The clock monitor and the comparators are disabled.
e
4V, V
CC
e
V
2.5V, V
CC
e
4V, V
CC
e
V
2.5V, V
CC
e
4V, V
CC
e
V
2.5V, V
CC
e
4V, V
CC
e
V
2.5V, V
CC
e
4V, V
CC
e
V
2.5V, V
CC
e
6.0V
CC
Total Current out of GND Pin (Sink) 110 mA
Storage Temperature Range
Note:
Absolute maximum ratings indicate limits beyond
b
65§Ctoa140§C
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
s
a
85§C unless otherwise specified
A
CC
e
1 ms 8.0 mA
e
2.5 ms 4.5 mA
e
2.5 ms 2.5 mA
c
e
10 ms 1.4 mA
c
k
110 mA
k
0.5 6 mA
e
1 ms 3.5 mA
e
2.5 ms 2.5 mA
e
10 ms 0.7 mA
c
CC
CC
CC
b
2
e
0V
IN
e
3.3V
OH
e
1.8V
OH
e
1V 10 mA
OL
e
0.4V 2.0 mA
OL
e
2.7V
OH
e
1.8V
OH
e
3.3V
OH
e
1.8V
OH
e
0.4V 1.6 mA
OL
e
0.4V 0.7 mA
OL
b
40
b
0.4 mA
b
0.2 mA
b
10
b
2.5
b
0.4 mA
b
0.2 mA
b
2
CC
CC
CC
a
2 mA
b
250 mA
CC
b
100 mA
b
33 mA
a
2 mA
, L, C, and G0 –G5 configured
CC
V
V
V
V
V
V
V
V
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Page 5
DC Electrical Characteristics
b
40§CsT
s
a
85§C unless otherwise specified (Continued)
A
Parameter Conditions Min Typ Max Units
Allowable Sink/Source
Current per Pin
D Outputs (Sink) 15 mA
All others 3mA
Maximum Input Current T
without Latchup
RAM Retention Voltage, V
r
e
25§C
A
500 ns Rise
and Fall Time (Min)
g
100 mA
2V
Input Capacitance 7pF
Load Capacitance on D2 1000 pF
AC Electrical Characteristics
b
40§CsT
s
a
85§C unless otherwise specified
A
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (tc)
s
4V
2.5V
s
V
6V 1 DC ms
CC
k
s
V
4V 2.5 DC ms
CC
s
s
V
6V 3 DC ms
CC
k
s
V
4V 7.5 DC ms
CC
Crystal, Resonator, 4V
R/C Oscillator 2.5V
Inputs
t
SETUP
t
HOLD
4VsV
2.5V
4VsV
2.5V
Output Propagation Delay (Note 4) R
t
PD1,tPD0
SO, SK 4VsV
2.5V
All Others 4V
2.5V
MICROWIRETMSetup Time (t
MICROWIRE Hold Time (t
MICROWIRE Output Propagation Delay (t
)20ns
UWS
)56ns
UWH
) 220 ns
UPD
s
6V 200 ns
CC
k
s
V
4V 500 ns
CC
s
6V 60 ns
CC
k
s
V
4V 150 ns
CC
e
L
s
s
s
e
2.2k, C
CC
V
V
CC
V
100 pF
L
s
6V 0.7 ms
k
4V 1.75 ms
CC
s
6V 1 ms
k
4V 2.5 ms
CC
Input Pulse Width
Interrupt Input High Time 1 t
Interrupt Input Low Time 1 t
Timer Input High Time 1 t
Timer Input Low Time 1 t
Reset Pulse Width 1 ms
Note 4: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
c
c
c
c
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Comparators AC and DC Characteristics V
CC
e
5V, T
e
25§C
A
Parameter Conditions Min Typ Max Units
Input Offset Voltage 0.4VsV
b
V
CC
1.5V
IN
g
10
s
Input Common Mode Voltage Range 0.4 V
Low Level Output Current V
High Level Output Current V
e
0.4V 1.6 mA
OL
e
4.6V 1.6 mA
OH
DC Supply Current Per Comparator
(When Enabled)
Response Time TBD mV Step, TBD mV
Overdrive, 100 pF Load
1 ms
g
25 mV
b
1.5 V
CC
250 mA
FIGURE 2. MICROWIRE/PLUS Timing
TL/DD/9765– 7
Pin Descriptions
VCCand GND are the power supply pins.
CKI is the clock input. This can come from an R/C generated oscillator, or a crystal oscillator (in conjunction with
CKO). See Oscillator Description section.
RESET
is the master reset input. See Reset Description
section.
The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O
ports.)
Figure 3
DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below:
CONFIGURATION DATA
Register Register
shows the I/O port configurations. The
Port Set-Up
0 0 Hi-Z Input
(TRI-STATE Output)
0 1 Input with Weak Pull-Up
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output
FIGURE 3. I/O Port Configurations
TL/DD/9765– 8
PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
The Port L supports Multi-Input Wake Up on all eight pins.
L1 is used for the UART external clock. L2 and L3 are used
for the UART transmit and receive. L4 and L5 are used for
the timer input functions T2A and T2B. L6 and L7 are used
for the timer input functions T3A and T3B.
The Port L has the following alternate features:
L0 MIWU
L1 MIWU or CKX
L2 MIWU or TDX
L3 MIWU or RDX
L4 MIWU or T2A
L5 MIWU or T2B
L6 MIWU or T3A
L7 MIWU or T3B
Port G is an 8-bit port with 5 I/O pins (G0, G2 –G5), an input
pin (G6), and two dedicated output pins (G1 and G7). Pins
G0 and G2 –G6 all have Schmitt Triggers on their inputs. Pin
G1 serves as the dedicated WDOUT WATCHDOG output,
while pin G7 is either input or output depending on the oscillator mask option selected. With the crystal oscillator option
selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALT mode with a low
to high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (G0, G2 – G5) can be individually configured under software control.
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Pin Descriptions (Continued)
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose
input (R/C clock option), the associated bits in the data and
configuration registers for G6 and G7 are used for special
purpose functions as outlined below. Reading the G6 and
G7 data bits will return zeros.
Note that the chip will be placed in the HALT mode by writing a ‘‘1’’ to bit 7 of the Port G Data Register. Similarly the
chip will be placed in the IDLE mode by writing a ‘‘1’’ to bit 6
of the Port G Data Register.
Writing a ‘‘1’’ to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set
high, enables the clock start up delay after HALT when the
R/C clock configuration is used.
Config Reg. Data Reg.
G7 CLKDLY HALT
G6 Alternate SK IDLE
Port G has the following alternate features:
G0 INTR (External Interrupt Input)
G2 T1B (Timer T1 Capture Input)
G3 T1A (Timer T1 I/O)
G4 SO (MICROWIRE
G5 SK (MICROWIRE Serial Clock)
G6 SI (MICROWIRE Serial Data Input)
Port G has the following dedicated functions:
G1 WDOUT WATCHDOG and/or Clock Monitor dedicat-
ed output
G7 CKO Oscillator dedicated output or general purpose
input
Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated
pins will return unpredicatable values.
PORT I is an eight-bit Hi-Z input port. The 28-pin device
does not have a full complement of Port I pins. The unavailable pins are not terminated i.e., they are floating. A read
operation for these unterminated pins will return unpredictable values. The user must ensure that the software takes
this into account by either masking or restricting the accesses to bit operations. The unterminated Port I pins will draw
power only when addressed.
Port I1–I3 are used for Comparator 1. Port I4 –I6 are used
for Comparator 2.
The Port I has the following alternate features.
I1 COMP1
I2 COMP1aIN (Comparator 1 Positive Input)
I3 COMP1OUT (Comparator 1 Output)
I4 COMP2bIN (Comparator 2 Negative Input)
I5 COMP2
I6 COMP2OUT (Comparator 2 Output)
Port D is an 8-bit output port that is preset high when
RESET
goes low. The user can tie two or more D port out-
puts together in order to get a higher drive.
TM
Serial Data Output)
b
IN (Comparator 1 Negative Input)
a
IN (Comparator 2 Positive Input)
Functional Description
The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store memory (RAM). Both ROM and RAM have their own separate
addressing space with separate address buses. The architecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (t
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.
S is the 8-bit Data Segment Address Register used to extend the lower half of the address range (00 to 7F) into 256
data segments of 128 bytes each.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
The program memory consists of 4096 bytes of ROM.
These bytes may hold program instructions or constant data
(data tables for the LAID instruction, jump vectors for the
JID instruction, and interrupt vectors for the VIS instruction).
The program memory is addressed by the 15-bit program
counter (PC). All interrupts in the devices vector to program
memory location 0FF Hex.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PLUS SIO
shift register, and the various registers, and counters associated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indirectly by the B, X, SP pointers and S register.
The device has 192 bytes of RAM. Sixteen bytes of RAM
are mapped as ‘‘registers’’ at addresses 0F0 to 0FF Hex.
These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and
skip if zero) instruction. The memory pointer registers X, SP,
B and S are memory mapped into this space at address
locations 0FC to 0FF Hex respectively, with the other registers being available for general usage.
The instruction set permits any bit in memory to be set,
reset or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
) cycle time.
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Data Memory Segment RAM Extension
Data memory address 0FF is used as a memory mapped
location for the Data Segment Address Register (S).
The data store memory is either addressed directly by a
single byte address within the instruction, or indirectly relative to the reference of the B, X, or SP pointers (each contains a single-byte address). This single-byte address allows
an addressing range of 256 locations from 00 to FF hex.
The upper bit of this single-byte address divides the data
store memory into two separate sections as outlined previously. With the exception of the RAM register memory from
address locations 00F0 to 00FF, all RAM memory is memory mapped with the upper bit of the single-byte address being equal to zero. This allows the upper bit of the single-byte
address to determine whether or not the base address
range (from 0000 to 00FF) is extended. If this upper bit
equals one (representing address range 0080 to 00FF),
then address extension does not take place. Alternatively, if
this upper bit equals zero, then the data segment extension
register S is used to extend the base address range (from
0000 to 007F) from XX00 to XX7F, where XX represents the
8 bits from the S register. Thus the 128-byte data segment
extensions are located from addresses 0100 to 017F for
data segment 1, 0200 to 027F for data segment 2, etc., up
to FF00 to FF7F for data segment 255. The base address
range from 0000 to 007F represents data segment 0.
Figure 4
illustrates how the S register data memory extension is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XX00
to XX7F. This organization allows a total of 256 data segments of 128 bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are
available for all data segments. The S register must be
changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, I/O registers,
control registers, etc.) is always available regardless of the
contents of the S register, since the upper base segment
(address range 0080 to 00FF) is independent of data segment extension.
The instructions that utilize the stack pointer (SP) always
reference the stack as part of the base segment (Segment
0), regardless of the contents of the S register. The S register is not changed by these instructions. Consequently, the
stack (used with subroutine linkage and interrupts) is always
located in the base segment. The stack pointer will be intitialized to point at data memory location 006F as a result of
reset.
The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
116 bytes of RAM are resident from address 0000 to 006F
in the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at addresses 00F0 to 00FF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.
Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XX00 to XX7F) of
the lower base segment. The additional 64 bytes of RAM
(beyond the initial 128 bytes) are memory mapped at address locations 0100 to 013F hex.
*Reads as all ones.
FIGURE 4. RAM Organization
TL/DD/9765– 9
Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET
pulled low. Upon initialization, the data and configuration
registers for ports L, G and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and/or Clock Monitor error
output pin. Port D is set high. The PC, PSW, ICNTRL,
CNTRL, T2CNTRL and T3CNTRL control registers are
cleared. The UART registers PSR, ENU (except that TBMT
bit is set), ENUR and ENUI are cleared. The Comparator
Select Register is cleared. The S register is initialized to
zero. The Multi-Input Wakeup registers WKEN, WKEDG and
WKPND are cleared. The stack pointer, SP, is initialized to
6F Hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t
the clock frequency reaching the minimum specified value,
at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in
to ensure that the RESET
supply to the chip stabilizes.
clock cycles. The Clock Monitor bit
C
–32 tCclock cycles following
C
Figure 5
pin is held low until the power
input is
should be used
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Reset (Continued)
RCl5cPower Supply Rise Time
FIGURE 5. Recommended Reset Circuit
TL/DD/9765– 10
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction
cycle clock (1/t
Figure 6
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.
Table A shows the component values required for various
standard crystal values.
R/C OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is available as a general purpose input, and/or HALT restart input.
Table B shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
).
c
shows the Crystal and R/C diagrams.
TL/DD/9765– 12
TABLE A. Crystal Oscillator Configuration, T
R1 R2 C1 C2 CKI Freq
(kX)(MX) (pF) (pF) (MHz)
0 1 30 30 –36 10 V
0 1 30 30 –36 4 V
0 1 200 100–150 0.455 V
TABLE B. RC Oscillator Configuration, T
R C CKI Freq Instr. Cycle
(kX) (pF) (MHz) (ms)
3.3 82 2.2 to 2.7 3.7 to 4.6 V
5.6 100 1.1 to 1.3 7.4 to 9.0 V
6.8 100 0.9 to 1.1 8.8 to 10.8 V
Note: 3ksRs200k
50 pF
sCs
200 pF
e
25§C
A
Conditions
e
5V
CC
e
5.0V
CC
e
5V
CC
e
25§C
A
Conditions
e
5V
CC
e
5V
CC
e
5V
CC
Control Registers
CNTRL Register (Address XÊ00EE)
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
IEDG External interrupt edge polarity select
MSEL Selects G5 and G4 as MICROWIRE/PLUS
T1C0 Timer T1 Start/Stop control in timer
T1C1 Timer T1 mode control bit
T1C2 Timer T1 mode control bit
T1C3 Timer T1 mode control bit
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0
Bit 7 Bit 0
e
by (00
(0
2, 01e4, 1xe8)
e
Rising edge, 1eFalling edge)
signals SK and SO respectively
modes 1 and 2
Timer T1 Underflow Interrupt Pending Flag in
timer mode 3
FIGURE 6. Crystal and R/C Oscillator Diagrams
TL/DD/9765– 11
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Page 10
Control Registers (Continued)
PSW Register (Address X
The PSW register contains the following select bits:
GIE Global interrupt enable (enables interrupts)
EXEN Enable external interrupt
BUSY MICROWIRE/PLUS busy shifting flag
EXPND External interrupt pending
T1ENA Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3)
C Carry Flag
HC Half Carry Flag
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 7 Bit 0
The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the carry and Half
Carry flags.
ICNTRL Register (Address X
The ICNTRL register contains the following bits:
T1ENB Timer T1 Interrupt Enable for T1B Input capture
edge
T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
mWEN Enable MICROWIRE/PLUS interrupt
mWPND MICROWIRE/PLUS interrupt pending
T0EN Timer T0 Interrupt Enable (Bit 12 toggle)
T0PND Timer T0 Interrupt pending
LPEN L Port Interrupt Enable (Multi-Input Wakeup/In-
terrupt)
Bit 7 could be used as a flag
Unused LPEN T0PND T0EN mWPND mWEN T1PNDB T1ENB
Bit 7 Bit 0
T2CNTRL Register (Address XÊ00C6)
The T2CNTRL register contains the following bits:
T2ENB Timer T2 Interrupt Enable for T2B Input capture
edge
T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-
ture edge
T2ENA Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1, T2 Underflow in mode 2, T2A capture edge in mode 3)
T2C0 Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3
00EF)
Ê
00E8)
Ê
T2C1 Timer T2 mode control bit
T2C2 Timer T2 mode control bit
T2C3 Timer T2 mode control bit
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
Bit 7 Bit 0
T3CNTRL Register (Address XÊ00B6)
The T3CNTRL register contains the following bits:
T3ENB Timer T3 Interrupt Enable for T3B
T3PNDB Timer T3 Interrupt Pending Flag for T3B pin
T3ENA Timer T3 Interrupt Enable for Timer Underflow
T3PNDA Timer T3 Interrupt Pending Flag (Autoload RA
T3C0 Timer T3 Start/Stop control in timer modes 1
T3C1 Timer T3 mode control bit
T3C2 Timer T3 mode control bit
T3C3 Timer T3 mode control bit
T3C3 T3C2 T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB
Bit 7 Bit 0
(T3B capture edge)
or T3A pin
in mode 1, T3 Underflow in mode 2, T3a capture edge in mode 3)
and 2
Timer T3 Underflow Interrupt Pending Flag in
timer mode 3
Timers
The device contains a very versatile set of timers (T0, T1,
T2, T3). All timers and associated autoreload/capture registers power up containing random data.
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed
rate of the instruction cycle clock, t
or write to the IDLE Timer T0, which is a count down timer.
The Timer T0 supports the following functions:
Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode
The IDLE Timer T0 can generate an interrupt when the thirteenth bit toggles. This toggle is latched into the T0PND
pending flag, and will occur every 4 ms at the maximum
clock frequency (t
interrupt from the thirteenth bit of Timer T0 to be enabled or
disabled. Setting T0EN will enable the interrupt, while resetting it will disable the interrupt.
e
1 ms). A control flag T0EN allows the
c
. The user cannot read
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Page 11
Timers (Continued)
TIMER T1, TIMER T2 AND TIMER T3
The device has a set of three powerful timer/counter
blocks, T1, T2 and T3. The associated features and functioning of a timer block are described by referring to the
timer block Tx. Since the three timer blocks, T1, T2 and T3
are identical, all comments are equally applicable to any of
the three timer blocks.
Each timer block consists of a 16-bit timer, Tx, and two
supporting 16-bit autoreload/capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA
and TxB. The pin TxA supports I/O required by the timer
block, while the pin TxB is an input to the timer block. The
powerful and flexible timer block allows the device to easily
perform all timer functions with minimal software overhead.
The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and
Input Capture mode.
The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.
Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention. The
user only has to define the parameters of the PWM signal
(ON time and OFF time). Once begun, the timer block will
continuously generate the PWM signal completely independent of the microcontroller. The user software services the
timer block only when the PWM parameters require updating.
In this mode the timer Tx counts down at a fixed rate of t
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.
Figure 7
shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxA output pin. The underflows can also be programmed to generate interrupts.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be
reloaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.
Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.
FIGURE 7. Timer in PWM Mode
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, Tx, is clocked by the input signal from the TxA pin.
The Tx timer control bits, TxC3, TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin. Underflows from the timer are latched into
the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.
In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
.
c
Figure 8
shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is
being used as the counter input clock.
FIGURE 8. Timer in External Event Counter Mode
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.
In this mode, the timer Tx is constantly running at the fixed
t
rate. The two registers, RxA and RxB, act as capture
c
registers. Each register acts in conjunction with a pin. The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.
TL/DD/9765– 14
TL/DD/9765– 15
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Page 12
Timers (Continued)
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently.
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.
Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the TxC0 control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
Figure 9
shows a block diagram of the timer in Input Capture
mode.
FIGURE 9. Timer in Input Capture Mode
TL/DD/9765– 16
TIMER CONTROL FLAGS
The timers T1, T2 and T3 have indentical control structures.
The control bits and their functions are summarized below.
TxC0 Timer Start/Stop control in Modes 1 and 2
(Processor Independent PWM and External
Event Counter), where 1
e
Start, 0eStop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag
TxENA Timer Interrupt Enable Flag
TxENB Timer Interrupt Enable Flag
e
1
Timer Interrupt Enabled
e
0
Timer Interrupt Disabled
TxC3 Timer mode control
TxC2 Timer mode control
TxC1 Timer mode control
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Page 13
Timers (Continued)
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
TxC3 TxC2 TxC1 Timer Mode
0 0 0 MODE 2 (External Timer Pos. TxB TxA
Event Counter) Underflow Edge Pos. Edge
0 0 1 MODE 2 (External Timer Pos. TxB TxA
Event Counter) Underflow Edge Neg. Edge
1 0 1 MODE 1 (PWM) Autoreload Autoreload
TxA Toggle RA RB
1 0 0 MODE 1 (PWM) Autoreload Autoreload
No TxA Toggle RA RB
0 1 0 MODE 3 (Capture) Pos. TxA Pos. TxB t
Captures: Edge or Edge
TxA Pos. Edge Timer
TxB Pos. Edge Underflow
1 1 0 MODE 3 (Capture) Pos. TxA Neg. TxB t
Captures: Edge or Edge
TxA Pos. Edge Timer
TxB Neg. Edge Underflow
0 1 1 MODE 3 (Capture) Neg. TxB Pos. TxB t
Captures: Edge or Edge
TxA Neg. Edge Timer
TxB Pos. Edge Underflow
1 1 1 MODE 3 (Capture) Neg. TxA Neg. TxB t
Captures: Edge or Edge
TxA Neg. Edge Timer
TxB Neg. Edge Underflow
Interrupt A Interrupt B Timer
Source Source Counts On
t
c
t
c
c
c
c
c
Power Save Modes
The device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscillator circuitry the WATCHDOG logic, the Clock Monitor and
timer T0 are active but all other microcontroller activities are
stopped. In either mode, all on-board RAM, registers, I/O
states, and timers (with the exception of T0) are unaltered.
HALT MODE
The device can be placed in the HALT mode by writing a
‘‘1’’ to the HALT flag (G7 data bit). All microcontroller activities, including the clock and timers, are stopped. The
WATCHDOG logic is disabled during the HALT mode. However, the clock monitor circuitry if enabled remains active
and will cause the WATCHDOG output pin (WDOUT) to go
low. If the HALT mode is used and the user does not want
to activate the WDOUT pin, the Clock Monitor should be
disabled after the device comes out of reset (resetting the
Clock Monitor control bit with the first write to the WDSVR
register). In the HALT mode, the power requirements of the
device are minimal and the applied voltage (V
decreased to V
machine.
e
2.0V) without altering the state of the
r(Vr
The device supports three different ways of exiting the
HALT mode. The first method of exiting the HALT mode is
with the Multi-Input Wakeup feature on the L port. The second method is with a low to high transition on the CKO (G7)
pin. This method precludes the use of the crystal clock con-
) may be
CC
figuration (since CKO becomes a dedicated output), and so
may be used with an RC clock configuration. The third
method of exiting the HALT mode is by pulling the RESET
pin low.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the t
clock is derived by dividing the oscillator clock down by a
instruction cycle clock. The t
c
factor of 10. The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications. This Schmitt trigger
is not part of the oscillator closed loop. The startup timeout
from the IDLE timer enables the clock signals to be routed
to the rest of the chip.
If an RC clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDLY, mapped as configuration bit G7, controls whether the delay is to be introduced or not. The delay is included if CLKDLY is set, and
excluded if CLKDLY is reset. The CLKDLY bit is cleared on
reset.
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Page 14
Power Save Modes (Continued)
The device has two mask options associated with the HALT
mode. The first mask option enables the HALT mode feature, while the second mask option disables the HALT
mode. With the HALT mode enable mask option, the device
will enter and exit the HALT mode as described above. With
the HALT disable mask option, the device cannot be placed
in the HALT mode (writing a ‘‘1’’ to the HALT flag will have
no effect).
The WATCHDOG detector circuit is inhibited during the
HALT mode. However, the clock monitor circuit if enabled
remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch.
IDLE MODE
The device is placed in the IDLE mode by writing a ‘‘1’’ to
the IDLE flag (G6 data bit). In this mode, all activities, except
the associated on-board oscillator circuitry, the WATCHDOG logic, the clock monitor and the IDLE Timer T0, are
stopped.
As with the HALT mode, the device can be returned to normal operation with a reset, or with a Multi-Input Wakeup
from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the thirteenth
bit (representing 4.096 ms at internal clock frequency of
1 MHz, t
e
1 ms) of the IDLE Timer toggles.
c
This toggle condition of the thirteenth bit of the IDLE Timer
T0 is latched into the T0PND pending flag.
The user has the option of being interrupted with a transition
on the thirteenth bit of the IDLE Timer T0. The interrupt can
be enabled or disabled via the T0EN control bit. Setting the
T0EN flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer T0 interrupt enabled. In this case, when the T0PND bit gets set, the
device will first execute the Timer T0 interrupt service routine and then return to the instruction following the ‘‘Enter
Idle Mode’’ instruction.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled. In this case, the device
will resume normal operation with the instruction immediately following the ‘‘Enter IDLE Mode’’ instruction.
Note: It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions
are necessary to allow clock resynchronization following the HALT or
IDLE modes.
Multi-Input Wakeup
The Multi-Input Wakeup feature is ued to return (wakeup)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts.
Figure 10
shows the Multi-Input Wakeup logic.
FIGURE 10. Multi-Input Wake Up Logic
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TL/DD/9765– 17
Page 15
Multi-Input Wakeup (Continued)
The Multi-Input Wakeup feature utilizes the L Port. The user
selects which particular L port bit (or combination of L Port
bits) will cause the device to exit the HALT or IDLE modes.
The selection is done through the Reg: WKEN. The Reg:
WKEN is an 8-bit read/write register, which contains a control bit for every L port bit. Setting a particular WKEN bit
enables a Wakeup from the associated L port pin.
The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an 8bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.
An example may serve to clarify this procedure. Suppose
we wish to change the edge select from positive (low going
high) to negative (high going low) for L Port bit 5, where bit 5
has previously been enabled for an input interrupt. The program would be as follows:
RBIT 5, WKEN
SBIT 5, WKEDG
RBIT 5, WKPND
SBIT 5, WKEN
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup/Interrupt, a safety procedure should also be followed to avoid inherited
pseudo wakeup conditions. After the selected L port bits
have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired
edge selects, followed by the associated WKPND bits being
cleared.
This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset.
The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wakeup conditions,
the device will not enter the HALT mode if any Wakeup bit is
both enabled and pending. Consequently, the user has the
responsibility of clearing the pending flags before attempting to enter the HALT mode.
WKEN, WKPND and WKEDG are all read/write registers,
and are cleared at reset.
PORT L INTERRUPTS
Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into
the same service subroutine.
The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to
be individually enabled or disabled. The register WKEDG
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.
The GIE (Global Interrupt Enable) bit enables the interrupt
function.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If
he elects to disable the interrupt, then the device will restart
execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or
IDLE modes. In the other case, the device will first execute
the interrupt service routine and then revert to normal operation.
The Wakeup signal will not start the chip running immediately since crystal oscillators or ceramic resonators have a finite start up time. The IDLE Timer (T0) generates a fixed
delay to ensure that the oscillator has indeed stabilized before allowing the device to execute instructions. In this case,
upon detecting a valid Wakeup signal, only the oscillator
circuitry and the IDLE Timer T0 are enabled. The IDLE Timer is loaded with a value of 256 and is clocked from the t
instruction cycle clock. The tcclock is derived by dividing
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on-chip inverter ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large
amplitude to meet the Schmitt trigger specifications. This
Schmitt trigger is not part of the oscillator closed loop. The
startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip.
If the RC clock option is used, the fixed delay is under software control. A control flag, CLKDLY, in the G7 configuration bit allows the clock start up delay to be optionally inserted. Setting CLKDLY flag high will cause clock start up delay
to be inserted and resetting it will exclude the clock start up
delay. The CLKDLY flag is cleared during reset, so the clock
start up delay is not present following reset with the RC
clock options.
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Page 16
UART
The COP888CG contains a full-duplex software programmable UART. The UART
shift register, a receiver shift register and seven addressable registers, as follows: a transmit buffer register (TBUF),
a receiver buffer register (RBUF), a UART control and
status register (ENU), a UART receive control and status
register (ENUR), a UART interrupt and clock source register
(ENUI), a prescaler select register (PSR) and baud (BAUD)
register. The ENU register contains flags for transmit and
receive functions; this register also determines the length of
the data frame (7, 8 or 9 bits), the value of the ninth bit in
transmission, and parity selection bits. The ENUR register
flags framming, data overrun and parity errors while the
UART is receiving.
(Figure 11)
consists of a transmit
Other functions of the ENUR register include saving the
ninth bit received in the data frame, enabling or disabling the
UART’s attention mode of operation and providing additional receiver/transmitter status information via RCVG and
XMTG bits. The determination of an internal or external
clock source is done by the ENUI register, as well as selecting the number of stop bits and enabling or disabling transmit and receive interrupts. A control flag in this register can
also select the UART mode of operation: asynchronous or
synchronous.
FIGURE 11. UART Block Diagram
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TL/DD/9765– 18
Page 17
UART (Continued)
UART CONTROL AND STATUS REGISTERS
The operation of the UART is programmed through three
registers: ENU, ENUR and ENUI. The function of the individual bits in these registers is as follows:
ENU-UART Control and Status Register (Address at 0BA)
PEN PSEL1 XBIT9/ CHL1 CHL0 ERR RBFL TBMT
0RW 0RW 0RW 0RW 0RW 0R 0R 1R
Bit 7 Bit 0
ENUR-UART Receive Control and Status Register
(Address at 0BB)
DOE FE PE SPARE RBIT9 ATTN XMTG RCVG
0RD 0RD 0RD 0RW* 0R 0RW 0R 0R
Bit7 Bit0
ENUI-UART Interrupt and Clock Source Register
(Address at 0BC)
STP2 STP78 ETDX SSEL XRCLK XTCLK ERI ETI
0RW 0RW 0RW 0RW 0RW 0RW 0RW 0RW
Bit7 Bit0
*Bit is not used.
0 Bit is cleared on reset.
1 Bit is set to one on reset.
R Bit is read-only; it cannot be written by software.
RW Bit is read/write.
D Bit is cleared on read; when read by software as a one, it is cleared
automatically. Writing to the bit does not affect its state.
DESCRIPTION OF UART REGISTER BITS
ENUÐUART CONTROL AND STATUS REGISTER
TBMT: This bit is set when the UART transfers a byte of
data from the TBUF register into the TSFT register for transmission. It is automatically reset when software writes into
the TBUF register.
RBFL: This bit is set when the UART has received a complete character and has copied it into the RBUF register. It
is automatically reset when software reads the character
from RBUF.
ERR: This bit is a global UART error flag which gets set if
any or a combination of the errors (DOE, FE, PE) occur.
CHL1, CHL0: These bits select the character frame format.
Parity is not included and is generated/verified by hardware.
CHL1
CHL1
CHL1
CHL1
XBIT9/PSEL0: Programs the ninth bit for transmission
when the UART is operating with nine data bits per frame.
For seven or eight data bits per frame, this bit in conjunction
with PSEL1 selects parity.
PSEL1, PSEL0: Parity select bits.
PSEL1
PSEL1
PSEL0
e
0, CHL0e0 The frame contains eight data bits.
e
0, CHL0e1 The frame contains seven data
e
1, CHL0e0 The frame contains nine data bits.
e
1, CHL0e1 Loopback Mode selected. Trans-
bits.
mitter output internally looped
back to receiver input. Nine bit
framing format is used.
e
0, PSEL0e0 Odd Parity (if Parity enabled)
e
0, PSEL0e1 Even Parity (if Parity enabled)
e
PSEL1
PSEL1
1, PSEL0e0 Mark(1) (if Parity enabled)
e
1, PSEL0e1 Space(0) (if Parity enabled)
PEN: This bit enables/disables Parity (7- and 8-bit modes
only).
e
PEN
0 Parity disabled.
e
PEN
1 Parity enabled.
ENURÐUART RECEIVE CONTROL AND
STATUS REGISTER
RCVG: This bit is set high whenever a framing error occurs
and goes low when RDX goes high.
XMTG: This bit is set to indicate that the UART is transmitting. It gets reset at the end of the last frame (end of last
Stop bit).
ATTN: ATTENTION Mode is enabled while this bit is set.
This bit is cleared automatically on receiving a character
with data bit nine set.
RBIT9: Contains the ninth data bit received when the UART
is operating with nine data bits per frame.
SPARE: Reserved for future use.
PE: Flags a Parity Error.
e
PE
0 Indicates no Parity Error has been detected since
the last time the ENUR register was read.
e
PE
1 Indicates the occurrence of a Parity Error.
FE: Flags a Framing Error.
e
FE
0 Indicates no Framing Error has been detected
since the last time the ENUR register was read.
e
FE
1 Indicates the occurrence of a Framing Error.
DOE: Flags a Data Overrun Error.
e
DOE
0 Indicates no Data Overrun Error has been de-
tected since the last time the ENUR register
was read.
e
DOE
1 Indicates the occurrence of a Data Overrun Er-
ror.
ENUIÐUART INTERRUPT AND
CLOCK SOURCE REGISTER
ETI: This bit enables/disables interrupt from the transmitter
section.
e
ETI
0 Interrupt from the transmitter is disabled.
e
ETI
1 Interrupt from the transmitter is enabled.
ERI: This bit enables/disables interrupt from the receiver
section.
e
ERI
0 Interrupt from the receiver is disabled.
e
ERI
1 Interrupt from the receiver is enabled.
XTCLK: This bit selects the clock source for the transmittersection.
e
XTCLK
XTCLK
0 The clock source is selected through the
PSR and BAUD registers.
e
1 Signal on CKX (L1) pin is used as the clock.
XRCLK: This bit selects the clock source for the receiver
section.
e
XRCLK
XRCLK
SSEL: UART mode select.
SSEL
SSEL
0 The clock source is selected through the
PSR and BAUD registers.
e
1 Signal on CKX (L1) pin is used as the clock.
e
0 Asynchronous Mode.
e
1 Synchronous Mode.
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Page 18
UART (Continued)
ETDX: TDX (UART Transmit Pin) is the alternate function
assigned to Port L pin L2; it is selected by setting ETDX bit.
To simulate line break generation, software should reset
ETDX bit and output logic zero to TDX pin through Port L
data and configuration registers.
STP78: This bit is set to program the last Stop bit to be
7/8th of a bit in length.
STP2: This bit programs the number of Stop bits to be transmitted.
e
STP2
0 One Stop bit transmitted.
e
STP2
1 Two Stop bits transmitted.
Associated I/O Pins
Data is transmitted on the TDX pin and received on the RDX
pin. TDX is the alternate function assigned to Port L pin L2;
it is selected by setting ETDX (in the ENUI register) to one.
RDX is an inherent function of Port L pin L3, requiring no
setup.
The baud rate clock for the UART can be generated onchip, or can be taken from an external source. Port L pin L1
(CKX) is the external clock I/O pin. The CKX pin can be
either an input or an output, as determined by Port L Configuration and Data registers (Bit 1). As an input, it accepts a
clock signal which may be selected to drive the transmitter
and/or receiver. As an output, it presents the internal Baud
Rate Generator output.
UART Operation
The UART has two modes of operation: asynchronous
mode and synchronous mode.
ASYNCHRONOUS MODE
This mode is selected by resetting the SSEL (in the ENUI
register) bit to zero. The input frequency to the UART is 16
times the baud rate.
The TSFT and TBUF registers double-buffer data for transmission. While TSFT is shifting out the current character on
the TDX pin, the TBUF register may be loaded by software
with the next byte to be transmitted. When TSFT finishes
transmitting the current character the contents of TBUF are
transferred to the TSFT register and the Transmit Buffer
Empty Flag (TBMT in the ENU register) is set. The TBMT
flag is automatically reset by the UART when software loads
a new character into the TBUF register. There is also the
XMTG bit which is set to indicate that the UART is transmitting. This bit gets reset at the end of the last frame (end of
last Stop bit). TBUF is a read/write register.
The RSFT and RBUF registers double-buffer data being received. The UART receiver continually monitors the signal
on the RDX pin for a low level to detect the beginning of a
Start bit. Upon sensing this low level, it waits for half a bit
time and samples again. If the RDX pin is still low, the receiver considers this to be a valid Start bit, and the remaining bits in the character frame are each sampled a single
time, at the mid-bit position. Serial data input on the RDX pin
is shifted into the RSFT register. Upon receiving the complete character, the contents of the RSFT register are copied into the RBUF register and the Received Buffer Full Flag
(RBFL) is set. RBFL is automatically reset when software
reads the character from the RBUF register. RBUF is a read
only register. There is also the RCVG bit which is set high
when a framing error occurs and goes low once RDX goes
high. TBMT, XMTG, RBFL and RCVG are read only bits.
SYNCHRONOUS MODE
In this mode data is transferred synchronously with the
clock. Data is transmitted on the rising edge and received
on the falling edge of the synchronous clock.
This mode is selected by setting SSEL bit in the ENUI register. The input frequency to the UART is the same as the
baud rate.
When an external clock input is selected at the CKX pin,
data transmit and receive are performed synchronously with
this clock through TDX/RDX pins.
If data transmit and receive are selected with the CKX pin
as clock output, the device generates the synchronous
clock output at the CKX pin. The internal baud rate generator is used to produce the synchronous clock. Data transmit
and receive are performed synchronously with this clock.
FRAMING FORMATS
The UART supports several serial framing formats
12).
The format is selected using control bits in the ENU,
ENUR and ENUI registers.
The first format (1, 1a, 1b, 1c) for data transmission (CHL0
e
1, CHL1e0) consists of Start bit, seven Data bits (excluding parity) and 7/8, one or two Stop bits. In applications
using parity, the parity bit is generated and verified by hardware.
The second format (CHL0
Start bit, eight Data bits (excluding parity) and 7/8, one or
two Stop bits. Parity bit is generated and verified by hardware.
The third format for transmission (CHL0
consists of one Start bit, nine Data bits and 7/8, one or two
Stop bits. This format also supports the UART ‘‘ATTENTION’’ feature. When operating in this format, all eight bits
of TBUF and RBUF are used for data. The ninth data bit is
transmitted and received using two bits in the ENU and
ENUR registers, called XBIT9 and RBIT9. RBIT9 is a read
only bit. Parity is not generated or verified in this mode.
For any of the above framing formats, the last Stop bit can
be programmed to be 7/8th of a bit in length. If two Stop
bits are selected and the 7/8th bit is set (selected), the
second Stop bit will be 7/8th of a bit in length.
The parity is enabled/disabled by PEN bit located in the
ENU register. Parity is selected for 7- and 8-bit modes only.
If parity is enabled (PEN
performed by PSEL0 and PSEL1 bits located in the ENU
register.
Note that the XBIT9/PSEL0 bit located in the ENU register
serves two mutually exclusive functions. This bit programs
the ninth bit for transmission when the UART is operating
with nine data bits per frame. There is no parity selection in
this framing format. For other framing formats XBIT9 is not
needed and the bit is PSEL0 used in conjunction with
PSEL1 to select parity.
The frame formats for the receiver differ from the transmitter in the number of Stop bits required. The receiver only
requires one Stop bit in a frame, regardless of the setting of
the Stop bit selection bits in the control register. Note that
an implicit assumption is made for full duplex UART operation that the framing formats are the same for the transmitter and receiver.
e
0, CHL1e0) consists of one
e
e
1), the parity selection is then
(Figure
0, CHL1e1)
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Page 19
UART Operation (Continued)
FIGURE 12. Framing Formats
UART INTERRUPTS
The UART is capable of generating interrupts. Interrupts are
generated on Receive Buffer Full and Transmit Buffer Empty. Both interrupts have individual interrupt vectors. Two
bytes of program memory space are reserved for each interrupt vector. The two vectors are located at addresses 0xEC
to 0xEF Hex in the program memory space. The interrupts
can be individually enabled or disabled using Enable Transmit Interrupt (ETI) and Enable Receive Interrupt (ERI) bits in
the ENUI register.
The interrupt from the Transmitter is set pending, and remains pending, as long as both the TBMT and ETI bits are
set. To remove this interrupt, software must either clear the
ETI bit or write to the TBUF register (thus clearing the TBMT
bit).
The interrupt from the receiver is set pending, and remains
pending, as long as both the RBFL and ERI bits are set. To
remove this interrupt, software must either clear the ERI bit
or read from the RBUF register (thus clearing the RBFL bit).
Baud Clock Generation
The clock inputs to the transmitter and receiver sections of
the UART can be individually selected to come either from
an external source at the CKX pin (port L, pin L1) or from a
TL/DD/9765– 19
source selected in the PSR and BAUD registers. Internally,
the basic baud clock is created from the oscillator frequency
through a two-stage divider chain consisting of a 1–16 (increments of 0.5) prescaler and an 11-bit binary counter.
(Figure 13)
read/write registers shown in
Baud Rate Divisor spills over into the Prescaler Select Register (PSR). PSR is cleared upon reset.
As shown in Table I, a Prescaler Factor of 0 corresponds to
NO CLOCK. NO CLOCK condition is the UART power down
mode where the UART clock is turned off for power saving
purpose. The user must also turn the UART clock off when
a different baud rate is chosen.
The correspondences between the 5-bit Prescaler Select
and Prescaler factors are shown in Table I. Therer are many
ways to calculate the two divisor factors, but one particularly
effective method would be to achieve a 1.8432 MHz frequency coming out of the first stage. The 1.8432 MHz prescaler output is then used to drive the software programmable baud rate counter to create a x16 clock for the following
baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400,
3600, 4800, 7200, 9600, 19200 and 38400 (Table II). Other
baud rates may be created by using appropriate divisors.
The x16 clock is then divided by 16 to provide the rate for
the serial shift registers of the transmitter and receiver.
The divide factors are specified through two
Figure 14
. Note that the 11-bit
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Page 20
Baud Clock Generation (Continued)
FIGURE 13. UART BAUD Clock Generation
FIGURE 14. UART BAUD Clock Divisor Registers
TABLE I. Prescaler Factors
Prescaler Prescaler
Select Factor
00000 NO CLOCK
00001 1
00010 1.5
00011 2
00100 2.5
00101 3
00110 3.5
00111 4
01000 4.5
01001 5
01010 5.5
01011 6
01100 6.5
01101 7
01110 7.5
01111 8
10000 8.5
10001 9
10010 9.5
10011 10
10100 10.5
10101 11
10110 11.5
10111 12
11000 12.5
11001 13
11010 13.5
11011 14
11100 14.5
11101 15
11110 15.5
11111 16
TL/DD/9765– 20
TL/DD/9765– 21
TABLE II. Baud Rate Divisors
(1.8432 MHz Prescaler Output)
Baud Baud Rate
Rate Divisor
b
1 (N-1)
110 (110.03) 1046
134.5 (134.58) 855
150 767
300 383
600 191
1200 95
1800 63
2400 47
3600 31
4800 23
7200 15
9600 11
19200 5
38400 2
The entries in Table II assume a prescaler output
of 1.8432 MHz. In the asynchronous mode the
baud rate could be as high as 625k.
As an example, considering the Asynchronous Mode and a
CKI clock of 4.608 MHz, the prescaler factor selected is:
4.608/1.8432
e
2.5
The 2.5 entry is available in Table I. The 1.8432 MHz prescaler output is then used with proper Baud Rate Divisor
(Table II) to obtain different baud rates. For a baud rate of
19200 e.g., the entry in Table II is 5.
b1e
N
5(Nb1 is the value from Table II)
Ne6 (N is the Baud Rate Divisor)
Baud Ratee1.8432 MHz/(16c6)e19200
The divide by 16 is performed because in the asynchronous
mode, the input frequency to the UART is 16 times the baud
rate. The equation to calculate baud rates is given below.
The actual Baud Rate may be found from:
e
BR
Fc/(16cNcP)
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Page 21
Baud Clock Generation (Continued)
Where:
BR is the Baud Rate
Fc is the CKI frequency
N is the Baud Rate Divisor (Table II).
P is the Prescaler Divide Factor selected by the value in the
Prescaler Select Register (Table I)
Note: In the Synchronous Mode, the divisor 16 is replaced by two.
Example:
Asynchronous Mode:
Crystal Frequencye5 MHz
Desired baud rate
Using the above equation NcP can be calculated first.
NcPe(5c106)/(16c9600)e32.552
Now 32.552 is divided by each Prescaler Factor (Table II) to
obtain a value closest to an integer. This factor happens to
be 6.5 (P
The programmed value (from Table II) should be 4 (Nb1).
Using the above values calculated for N and P:
e
6.5).
Ne32.552/6.5e5.008 (Ne5)
e
(5c106)/(16c5c6.5)e9615.384
BR
% errore(9615.385b9600)/9600e0.16
e
9600
Effect of HALT/IDLE
The UART logic is reinitialized when either the HALT or
IDLE modes are entered. This reinitialization sets the TBMT
flag and resets all read only bits in the UART control and
status registers. Read/Write bits remain unchanged. The
Transmit Buffer (TBUF) is not affected, but the Transmit
Shift register (TSFT) bits are set to one. The receiver registers RBUF and RSFT are not affected.
The device will exit from the HALT/IDLE modes when the
Start bit of a character is detected at the RDX (L3) pin. This
feature is obtained by using the Multi-Input Wakeup scheme
provided on the device.
Before entering the HALT or IDLE modes the user program
must select the Wakeup source to be on the RDX pin. This
selection is done by setting bit 3 of WKEN (Wakeup Enable)
register. The Wakeup trigger condition is then selected to
be high to low transition. This is done via the WKEDG register (Bit 3 is one.)
If the device is halted and crystal oscillator is used, the
Wakeup signal will not start the chip running immediately
because of the finite start up time requirement of the crystal
oscillator. The idle timer (T0) generates a fixed (256 t
lay to ensure that the oscillator has indeed stabilized before
allowing the device to execute code. The user has to consider this delay when data transfer is expected immediately
after exiting the HALT mode.
) de-
c
Diagnostic
Bits CHARL0 and CHARL1 in the ENU register provide a
loopback feature for diagnostic testing of the UART. When
these bits are set to one, the following occur: The receiver
input pin (RDX) is internally connected to the transmitter
output pin (TDX); the output of the Transmitter Shift Register is ‘‘looped back’’ into the Receive Shift Register input. In
this mode, data that is transmitted is immediately received.
This feature allows the processor to verify the transmit and
receive data paths of the UART.
Note that the framing format for this mode is the nine bit
format; one Start bit, nine data bits, and 7/8, one or two
Stop bits. Parity is not generated or verified in this mode.
Attention Mode
The UART Receiver section supports an alternate mode of
operation, referred to as ATTENTION Mode. This mode of
operation is selected by the ATTN bit in the ENUR register.
The data format for transmission must also be selected as
having nine Data bits and either 7/8, one or two Stop bits.
The ATTENTION mode of operation is intended for use in
networking the device with other processors. Typically in
such environments the messages consists of device addresses, indicating which of several destinations should receive them, and the actual data. This Mode supports a
scheme in which addresses are flagged by having the ninth
bit of the data field set to a 1. If the ninth bit is reset to a
zero the byte is a Data byte.
While in ATTENTION mode, the UART monitors the communication flow, but ignores all characters until an address
character is received. Upon receiving an address character,
the UART signals that the character is ready by setting the
RBFL flag, which in turn interrupts the processor if UART
Receiver interrupts are enabled. The ATTN bit is also
cleared automatically at this point, so that data characters
as well as address characters are recognized. Software examines the contents of the RBUF and responds by deciding
either to accept the subsequent data stream (by leaving the
ATTN bit reset) or to wait until the next address character is
seen (by setting the ATTN bit again).
Operation of the UART Transmitter is not affected by selection of this Mode. The value of the ninth bit to be transmitted
is programmed by setting XBIT9 appropriately. The value of
the ninth bit received is obtained by reading RBIT9. Since
this bit is located in ENUR register where the error flags
reside, a bit operation on it will reset the error flags.
Comparators
The device contains two differential comparators, each with
a pair of inputs (positive and negative) and an output. Ports
I1–I3 and I4– I6 are used for the comparators. The following
is the Port I assignment:
I1 Comparator1 negative input
I2 Comparator1 positive input
I3 Comparator1 output
I4 Comparator2 negative input
I5 Comparator2 positive input
I6 Comparator2 output
A Comparator Select Register (CMPSL) is used to enable
the comparators, read the outputs of the comparators internally, and enable the outputs of the comparators to the pins.
Two control bits (enable and output enable) and one result
bit are associated with each comparator. The comparator
result bits (CMP1RD and CMP2RD) are read only bits which
will read as zero if the associated comparator is not enabled. The Comparator Select Register is cleared with
reset, resulting in the comparators being disabled. The comparators should also be disabled before entering either the
HALT or IDLE modes in order to save power. The configuration of the CMPSL register is as follows:
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Comparators (Continued)
CMPSL REGISTER (ADDRESS X’00B7)
The CMPSL register contains the following bits:
CMP1EN Enable comparator 1
CMP1RD Comparator 1 result (this is a read only bit,
which will read as 0 if the comparator is not
enabled)
CMP10E Selects pin I3 as comparator 1 output provided
that CMPIEN is set to enable the comparator
CMP2EN Enable comparator 2
CMP2RD Comparator 2 result (this is a read only bit,
which will read as 0 if the comparator is not
enabled)
CMP20E Selects pin I6 as comparator 2 output provided
that CMP2EN is set to enable the comparator
Unused CMP20E CMP2RD CMP2EN CMP10E CMP1RD CMP1EN Unused
Bit 7 Bit 0
Note that the two unused bits of CMPSL may be used as
software flags.
Comparator outputs have the same spec as Ports L and G
except that the rise and fall times are symmetrical.
Interrupts
The device supports a vectored interrupt scheme. It supports a total of fourteen interrupt sources. The following table lists all the possible device interrupt sources, their arbitration ranking and the memory locations reserved for the
interrupt vector for each source.
Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt
is active if its associated enable and pending bits are set. If
e
GIE
1 and an interrupt is active, then the processor will
be interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described
in the Software Trap sub-section.
The interruption process is accomplished with the INTR instruction (opcode 00), which is jammed inside the Instruction Register and replaces the opcode about to be executed. The following steps are performed for every interrupt:
1. The GIE (Global Interrupt Enable) bit is reset.
2. The address of the instruction about to be executed is
pushed into the stack.
3. The PC (Program Counter) branches to address 00FF.
This procedure takes 7 t
cycles to execute.
c
FIGURE 15. Interrupt Block Diagram
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TL/DD/9765– 22
Page 23
Interrupts (Continued)
Arbitration
Ranking
(1) Highest Software INTR Instruction 0yFE – 0yFF
(2) External Pin G0 Edge 0yFA– 0yFB
(3) Timer T0 Underflow 0yF8 – 0yF9
(4) Timer T1 T1A/Underflow 0yF6 – 0yF7
(5) Timer T1 T1B 0yF4–0yF5
(6) MICROWIRE/PLUS BUSY Goes Low 0yF2 –0yF3
(7) UART Receive 0yEE– 0yEF
(8) UART Transmit 0yEC–0yED
(9) Timer T2 T2A/Underflow 0yEA – 0yEB
(10) Timer T2 T2B 0yE8 –0yE9
(11) Timer T3 T3A/Underflow 0yE6 – 0yE7
(12) Timer T3 T3B 0yE4 –0yE5
(13) Port L/Wakeup Port L Edge 0yE2– 0yE3
(14) Lowest Default VIS Instr. Execution 0yE0– 0yE1
y is VIS page, yi0.
At this time, since GIEe0, other maskable interrupts are
disabled. The user is now free to do whatever context
switching is required by saving the context of the machine in
the stack with PUSH instructions. The user would then program a VIS (Vector Interrupt Select) instruction in order to
branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS. Note
that this is not necessarily the interrupt that caused the
branch to address location 00FF Hex prior to the context
switching.
Thus, if an interrupt with a higher rank than the one which
caused the interruption becomes active before the decision
of which interrupt to service is made by the VIS, then the
interrupt with the higher rank will override any lower ones
and will be acknowledged. The lower priority interrupt(s) are
still pending, however, and will cause another interrupt immediately following the completion of the interrupt service
routine associated with the higher priority interrupt just serviced. This lower priority interrupt will occur immediately following the RETI (Return from Interrupt) instruction at the
end of the interrupt service routine just completed.
Inside the interrupt service routine, the associated pending
bit has to be cleared by software. The RETI (Return from
Interrupt) instruction at the end of the interrupt service routine will set the GIE (Global Interrupt Enable) bit, allowing
the processor to be interrupted again if another interrupt is
active and pending.
The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank.
The addresses of the different interrupt service routines,
called vectors, are chosen by the user and stored in ROM in
Source Description Address
Reserved for Future Use 0yFC– 0yFD
Reserved for Future Use 0yF0– 0yF1
Vector
Hi-Low Byte
without Any Interrupts
a table starting at 01E0 (assuming that VIS is located between 00FF and 01DF). The vectors are 15-bit wide and
therefore occupy 2 ROM locations.
VIS and the vector table must be located in the same 256byte block (0y00 to 0yFF) except if VIS is located at the last
address of a block. In this case, the table must be in the
next block. The vector table cannot be inserted in the first
256-byte block (y
i
0).
The vector of the maskable interrupt with the lowest rank is
located at 0yE0 (Hi-Order byte) and 0yE1 (Lo-Order byte)
and so forth in increasing rank number. The vector of the
maskable interrupt with the highest rank is located at 0yFA
(Hi-Order byte) and 0yFB (Lo-Order byte).
The Software Trap has the highest rank and its vector is
located at 0yFE and 0yFF.
If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch to a vector
located at 0yE0 –0yE1.
WARNING; A Default VIS interrupt handler routine must be
present. As a minimum, this handler should confirm that the
GIE bit is cleared (this indicates that the interrupt sequence
has been taken), take care of any required housekeeping,
restore context and return. Some sort of Warm Restart procedure should be implemented. These events can occur
without any error on the part of the system designer or programmer.
Note: There is always the possibility of an interrupt occurring during an in-
struction which is attempting to reset the GIE bit or any other interrupt
enable bit. If this occurs when a single cycle instruction is being used
to reset the interrupt enable bit, the interrupt enable bit will be reset
but an interrupt may still occur. This is because interrupt processing is
started at the same time as the interrupt bit is being reset. To avoid
this scenario, the user should always use a two, three, or four cycle
instruction to reset interrupt enable bits.
Figure 15
shows the Interrupt block diagram.
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Page 24
Interrupts (Continued)
SOFTWARE TRAP
The Software Trap (ST) is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register. This may happen when the
PC is pointing beyond the available ROM address space or
when the stack is over-popped.
When an ST occurs, the user can re-initialize the stack
pointer and do a recovery procedure (similar to reset, but
not necessarily containing all of the same initialization procedures) before restarting.
The occurrence of an ST is latched into the ST pending bit.
The GIE bit is not affected and the ST pending bit (not
accessible by the user) is used to inhibit other interrupts
and to direct the program to the ST service routine with the
VIS instruction. The RPND instruction is used to clear the
software interrupt pending bit. This pending bit is also
cleared on reset.
The ST has the highest rank among all interrupts.
Nothing (except another ST) can interrupt an ST being
serviced.
WATCHDOG
The device contains a WATCHDOG and clock monitor. The
WATCHDOG is designed to detect the user program getting
stuck in infinite loops resulting in loss of program control or
‘‘runaway’’ programs. The Clock Monitor is used to detect
the absence of a clock or a very slow clock below a specified rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table III shows the WDSVR register.
The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register allow
the user to pick an upper limit of the service window.
Table IV shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5bit Key Data field. The key data is fixed at 01100. Bit 0 of the
WDSVR Register is the Clock Monitor Select bit.
TABLE III. WATCHDOG Service Register (WDSVR)
Window
Select Monitor
X X 01100 Y
7 6 54321 0
Key Data
Clock
TABLE IV. WATCHDOG Service Window Select
WDSVR WDSVR Service Window
Bit 7 Bit 6 (Lower-Upper Limits)
0 0 2k–8k tcCycles
0 1 2k– 16k t
1 0 2k– 32k t
1 1 2k– 64k t
Cycles
c
Cycles
c
Cycles
c
Clock Monitor
The Clock Monitor aboard the device can be selected or
deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1/t
clock input rate on CKI of greater or equal to 100 kHz.
) is greater or equal to 10 kHz. This equates to a
c
WATCHDOG Operation
The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select bits (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, including the case where the oscillator fails to start.
The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the WATCHDOG key data. Subsequent writes to the WDSVR register
will compare the value being written by the user to the
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register. Table V shows the sequence of events that can occur.
The user must service the WATCHDOG at least once before the upper limit of the service window expires. The
WATCHDOG may not be serviced more than once in every
lower limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window.
The first write to the WDSVR Register is also counted as a
WATCHDOG service.
The WATCHDOG has an output pin associated with it. This
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low. The WDOUT pin is in the high impedance state in the
inactive state. Upon triggering the WATCHDOG, the logic
will pull the WDOUT (G1) pin low for an additional 16 t
32 t
cycles after the signal level on WDOUT pin goes be-
c
low the lower Schmitt trigger threshold. After this delay, the
device will stop forcing the WDOUT output low.
c
–
http://www.national.com 24
Page 25
WATCHDOG Operation (Continued)
The WATCHDOG service window will restart when the
WDOUT pin goes high. It is recommended that the user tie
the WDOUT pin back to V
pull WDOUT high.
A WATCHDOG service while the WDOUT signal is active
will be ignored. The state of the WDOUT pin is not guaranteed on reset, but if it powers up low then the WATCHDOG
will time out and WDOUT will enter high impedance state.
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified value, after which the G1 output will enter the high impedance TRI-STATE mode following 16 t
cles. The Clock Monitor generates a continual Clock Monitor error if the oscillator fails to start, or fails to reach the
minimum specified frequency. The specification for the
Clock Monitor is as follows:
l
1/t
10 kHzÐNo clock rejection.
c
k
1/t
10 HzÐGuaranteed clock rejection.
c
through a resistor in order to
CC
–32 tcclock cy-
c
Watchdog and Clock Monitor
Summary
The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:
Both the WATCHDOG and CLOCK MONITOR detector
#
circuits are inhibited during RESET.
Following RESET, the WATCHDOG and CLOCK MONI-
#
TOR are both enabled, with the WATCHDOG having he
maximum service window selected.
The WATCHDOG service window and CLOCK MONI-
#
TOR enable/disable option can only be changed once,
during the initial WATCHDOG service following RESET.
The initial WATCHDOG service must match the key data
#
value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error.
Subsequent WATCHDOG services must match all three
#
data fields in WDSVR in order to avoid WATCHDOG errors.
The correct key data value cannot be read from the
#
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all 0’s.
The WATCHDOG detector circuit is inhibited during both
#
the HALT and IDLE modes.
The CLOCK MONITOR detector circuit is active during
#
both the HALT and IDLE modes. Consequently, the device inadvertently entering the HALT mode will be detected as a CLOCK MONITOR error (provided that the
CLOCK MONITOR enable option has been selected by
the program).
With the single-pin R/C oscillator mask option selected
#
and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left
off before entering the HALT mode.
With the crystal oscillator mask option selected, or with
#
the single-pin R/C oscillator mask option selected and
the CLKDLY bit set, the WATCHDOG service window will
be set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced
for at least 2048 instruction cycles following HALT, but
must be serviced within the selected window to avoid a
WATCHDOG error.
The IDLE timer T0 is not initialized with RESET.
#
The user can sync in to the IDLE counter cycle with an
#
IDLE counter (T0) interrupt or by monitoring the T0PND
flag. The T0PND flag is set whenever the thirteenth bit of
the IDLE counter toggles (every 4096 instruction cycles).
The user is responsible for resetting the T0PND flag.
A hardware WATCHDOG service occurs just as the de-
#
vice exits the IDLE mode. Consequently, the WATCHDOG should not be serviced for at least 2048 instruction
cycles following IDLE, but must be serviced within the
selected window to avoid a WATCHDOG error.
Following RESET, the initial WATCHDOG service (where
#
the service window and the CLOCK MONITOR enable/
disable must be selected) may be programmed anywhere within the maximum service window (65,536 instruction cycles) initialized by RESET. Note that this initial WATCHDOG service may be programmed within the
initial 2048 instruction cycles without causing a WATCHDOG error.
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Page 26
Detection of Illegal Conditions
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.
Reading of undefined ROM gets zeros. The opcode for software interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt,
thus signaling that an illegal condition has occurred.
The subroutine stack grows down for each call (jump to
subroutine), interrupt, or PUSH, and grows up for each return or POP. The stack pointer is initialized to RAM location
06F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will point to addresses
070 and 071 Hex (which are undefined RAM). Undefined
RAM from addresses 070 to 07F (Segment 0), 140 to 17F
(Segment 1), and all other segments (i.e., Segments 3 . . .
etc.) is read as all 1’s, which in turn will cause the program
to return to address 7FFF Hex. This is an undefined ROM
location and the instruction fetched (all 0’s) from this location will generate a software interrupt signaling an illegal
condition.
Thus, the chip can detect the following illegal conditions:
a. Executing from undefined ROM
b. Over ‘‘POP’’ing the stack by having more returns than
calls.
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that
following reset, but might not contain the same program
initialization procedures). The recovery program should reset the software interrupt pending bit using the RPND instruction.
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous communications interface. The MICROWIRE/PLUS capability enables
the device to interface with any of National Semiconductor’s
MICROWIRE peripherals (i.e. A/D converters, display driv-
2
ers, E
PROMs etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an 8-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK).
shows a block diagram of the MICROWIRE/PLUS logic.
FIGURE 16. MICROWIRE/PLUS Block Diagram
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE/
PLUS arrangement with the internal clock source is called
the Master mode of operation. Similarly, operating the
MICROWIRE/PLUS arrangement with an external shift
clock is called the Slave mode of operation.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In the
master mode, the SK clock rate is selected by the two bits,
SL0 and SL1, in the CNTRL register. Table VI details the
different clock rates that may be selected.
Figure 12
TL/DD/9765– 23
TABLE V. WATCHDOG Service Actions
Key Window Clock
Data Data Monitor
Match Match Match Valid Service: Restart Service Window
Don’t Care Mismatch Don’t Care Error: Generate WATCHDOG Output
Mismatch Don’t Care Don’t Care Error: Generate WATCHDOG Output
Don’t Care Don’t Care Mismatch Error: Generate WATCHDOG Output
TABLE VI. MICROWIRE/PLUS
Master Mode Clock Select
SL1 SL0 SK
002
014
1x8
http://www.national.com 26
c
t
c
c
t
c
c
t
c
Action
Where tcis the
instruction cycle clock
Page 27
MICROWIRE/PLUS (Continued)
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave.
how two devices, microcontrollers and several peripherals
may be interconnected using the MICROWIRE/PLUS arrangements.
Warning:
The SIO register should only be loaded when the SK clock
is low. Loading the SIO register while the SK clock is high
will result in undefined data in the SIO register. SK clock is
normally low when not shifting.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is
low.
MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuration register. Table VII summarizes the bit settings
required for Master mode of operation.
MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bit in the Port G configuration register. Table VII summarizes the settings required to enter
the Slave mode of operation.
Figure 13
shows
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated.
Alternate SK Phase Operation
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register.
In both the modes the SK is normally low. In the normal
mode data is shifted in on the rising edge of the SK clock
and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock. In the alternate SK phase operation, data is shifted in on the falling edge of the SK clock and shifted out on
the rising edge of the SK clock.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.
TABLE VII
This table assumes that the control flag MSEL is set.
G4 (SO) G5 (SK) G4 G5
Config. Bit Config. Bit Fun. Fun.
1 1 SO Int. MICROWIRE/PLUS
0 1 TRI- Int. MICROWIRE/PLUS
STATE SK Master
1 0 SO Ext. MICROWIRE/PLUS
0 0 TRI- Ext. MICROWIRE/PLUS
STATE SK Slave
Operation
SK Master
SK Slave
FIGURE 17. MICROWIRE/PLUS Application
TL/DD/9765– 24
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Page 28
Memory Map
All RAM, ports and registers (except A and PC) are mapped into data memory address space.
Address
S/ADD REG
Contents
0000 to 006F On-Chip RAM bytes (112 bytes)
0070 to 007F Unused RAM Address Space (Reads
As All Ones)
xx80 to xxAF Unused RAM Address Space (Reads
Undefined Data)
xxB0 Timer T3 Lower Byte
XXB1 Timer T3 Upper Byte
xxB2 Timer T3 Autoload Register T3RA
Lower Byte
xxB3 Timer T3 Autoload Register T3RA
Upper Byte
xxB4 Timer T3 Autoload Register T3RB
Lower Byte
xxB5 Timer T3 Autoload Register T3RB
Upper Byte
xxB6 Timer T3 Control Register
xxB7 Comparator Select Register (CMPSL)
xxB8 UART Transmit Buffer (TBUF)
xxB9 UART Receive Buffer (RBUF)
xxBA UART Control and Status Register
(ENU)
xxBB UART Receive Control and Status
Register (ENUR)
xxBC UART Interrupt and Clock Source
Register (ENUI)
xxBD UART Baud Register (BAUD)
xxBE UART Prescale Select Register (PSR)
xxBF Reserved for UART
xxC0 Timer T2 Lower Byte
xxC1 Timer T2 Upper Byte
xxC2 Timer T2 Autoload Register T2RA
Lower Byte
xxC3 Timer T2 Autoload Register T2RA
Upper Byte
xxC4 Timer T2 Autoload Register T2RB
Lower Byte
xxC5 Timer T2 Autoload Register T2RB
Upper Byte
xxC6 Timer T2 Control Register
xxC7 WATCHDOG Service Register
(Reg:WDSVR)
xxC8 MIWU Edge Select Register
(Reg:WKEDG)
xxC9 MIWU Enable Register (Reg:WKEN)
xxCA MIWU Pending Register
(Reg:WKPND)
xxCB Reserved
xxCC Reserved
xxCD to xxCF Reserved
Address
S/ADD REG
xxD0 Port L Data Register
xxD1 Port L Configuration Register
xxD2 Port L Input Pins (Read Only)
xxD3 Reserved for Port L
xxD4 Port G Data Register
xxD5 Port G Configuration Register
xxD6 Port G Input Pins (Read Only)
xxD7 Port I Input Pins (Read Only)
xxD8 Port C Data Register
xxD9 Port C Configuration Register
xxDA Port C Input Pins (Read Only)
xxDB Reserved for Port C
xxDC Port D
xxDD to DF Reserved for Port D
xxE0 to xxE5 Reserved for EE Control Registers
xxE6 Timer T1 Autoload Register T1RB
Lower Byte
xxE7 Timer T1 Autoload Register T1RB
Upper Byte
xxE8 ICNTRL Register
xxE9 MICROWIRE/PLUS Shift Register
xxEA Timer T1 Lower Byte
xxEB Timer T1 Upper Byte
xxEC Timer T1 Autoload Register T1RA
Lower Byte
xxED Timer T1 Autoload Register T1RA
Upper Byte
xxEE CNTRL Control Register
xxEF PSW Register
xxF0 to FB On-Chip RAM Mapped as Registers
xxFC X Register
xxFD SP Register
xxFE B Register
xxFF S Register
0100–013F On-Chip 64 RAM Bytes
Reading memory locations 0070H –007FH (Segment 0) will return all ones.
Reading unused memory locations 0080H –00AFH (Segment 0) will return
undefined data. Reading unused memory locations 0140– 017F (Segment 1)
will return all ones. Reading memory locations from other Segments (i.e.,
Segment 2, Segment 3, . .. etc.) will return all ones.
Contents
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Page 29
Addressing Modes
There are ten addressing modes, six for operand addressing and four for transfer of control.
OPERAND ADDRESSING MODES
Register Indirect
This is the ‘‘normal’’ addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post increment or
decrement of pointer)
This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that
automatically post increments or decrements the B or X register after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
Immediate
The instruction contains an 8-bit immediate field as the operand.
Short Immediate
This addressing mode is used with the Load B Immediate
instruction. The instruction contains a 4-bit immediate field
as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from
a 1-byte relative jump (JP
instruction). There are no ‘‘pages’’ when using JP, since all
15 bits of PC are used.
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory segment.
Absolute Long
This mode is used with the JMPL and JSRL instructions,
with the instruction field of 15 bits replacing the entire 15
bits of the program counter (PC). This allows jumping to any
location in the current 4k program memory space.
a
b
1 is implemented by a NOP
31 toa32 to allow
Indirect
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruction.
Note: The VIS is a special case of the Indirect Transfer of Control address-
ing mode, where the double byte vector associated with the interrupt
is transferred from adjacent addresses in the program memory into
the program counter (PC) in order to jump to the associated interrupt
service routine.
Instruction Set
Register and Symbol Definition
Registers
A 8-Bit Accumulator Register
B 8-Bit Address Register
X 8-Bit Address Register
SP 8-Bit Stack Pointer Register
PC 15-Bit Program Counter Register
PU Upper 7 Bits of PC
PL Lower 8 Bits of PC
C 1 Bit of PSW Register for Carry
HC 1 Bit of PSW Register for Half Carry
GIE 1 Bit of PSW Register for Global
VU Interrupt Vector Upper Byte
VL Interrupt Vector Lower Byte
[B]
[X]
MD Direct Addressed Memory
Mem Direct Addressed Memory or[B
Meml Direct Addressed Memory or[B]or
Imm 8-Bit Immediate Data
Reg Register Memory: Addresses F0 to FF
Bit Bit Number (0 to 7)
w
Ý
Interrupt Enable
Symbols
Memory Indirectly Addressed by B
Register
Memory Indirectly Addressed by X
Register
]
Immediate Data
(Includes B, X and SP)
Loaded with
Exchanged with
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Page 30
Instruction Set (Continued)
INSTRUCTION SET
ADD A,Meml ADD AwAaMeml
ADC A,Meml ADD with Carry A
SUBC A,Meml Subtract with Carry A
AND A,Meml Logical AND A
ANDSZ A,Imm Logical AND Immed., Skip if Zero Skip next if (A and Imm)
OR A,Meml Logical OR A
XOR A,Meml Logical EXclusive OR AwA xor Meml
IFEQ MD,Imm IF EQual Compare MD and Imm, Do next if MD
IFEQ A,Meml IF EQual Compare A and Meml, Do next if A
IFNE A,Meml IF Not Equal Compare A and Meml, Do next if A
IFGT A,Meml IF Greater Than Compare A and Meml, Do next if A
IFBNE
DRSZ Reg Decrement Reg., Skip if Zero Reg
SBIT
RBIT
IFBIT
RPND Reset PeNDing Flag Reset Software Interrupt Pending Flag
X A,Mem EXchange A with Memory AÝMem
XA,
LD A,Meml LoaD A with Memory A
LD A,[X
LD B,Imm LoaD B with Immed. B
LD Mem,Imm LoaD Memory Immed MemwImm
LD Reg,Imm LoaD Register Memory Immed. Reg
XA,
XA,
LD A,[B
LD A,[X
LD
CLR A CLeaR A Aw0
INC A INCrement A AwAa1
DEC A DECrementA A
LAID Load A InDirect from ROM A
DCOR A Decimal CORrect A A
RRC A Rotate A Right thru C C
RLC A Rotate A Left thru C C
SWAP A SWAP nibbles of A A7...A4
SC Set C C
RC Reset C Cw0, HCw0
IFC IF C IF C is true, do next instruction
IFNC IF Not C If C is not true, do next instruction
POP A POP the stack into A SP
PUSH A PUSH A onto the stack
VIS Vector to Interrupt Service Routine PU
JMPL Addr. Jump absolute Long PC
JMP Addr. Jump absolute PC9...0
JP Disp. Jump relative short PCwPCar(risb31 toa32, except 1)
JSRL Addr. Jump SubRoutine Long
JSR Addr Jump SubRoutine
JID Jump InDirect PL
RET RETurn from subroutine SP
RETSK RETurn and SKip SP
RETI RETurn from Interrupt SP
INTR Generate an Interrupt
NOP No OPeration PC
Ý
Ý
,Mem Set BIT 1 to bit, Mem (bite0 to 7 immediate)
Ý
,Mem Reset BIT 0 to bit, Mem
Ý
,Mem IF BIT If bit in A or Mem is true do next instruction
[
]
X
]
[
g
B
[
g
X
g
g
[
]
g
B
,Imm LoaD Memory[B]Immed.
If B Not Equal Do next if lower 4 bits of BiImm
EXchange A with Memory[X
LoaD A with Memory[X
]
EXchange A with Memory[B
]
EXchange A with Memory[X
]
LoaD A with Memory[B
]
LoaD A with Memory[X
]
]
]
]
]
]
w
AaMemlaC, CwCarry
HC
w
Half Carry
w
AbMemIaC, CwCarry
HC
w
Half Carry
w
A and Meml
w
A or Meml
w
Regb1, Skip if Rege0
[X]
A
Ý
w
Meml
[X]
A
w
w
Imm
w
Imm
[B]
A
A
A
A
[B]
,(B
Ý
Ý
w
w
w
w
w
w
xA7x
wA7w
w
[X]
,(X
w
[B]
,(B
w
[X]
,(X
w
Imm, (BwBg1)
Ab1
ROM (PU,A)
BCD correction of A (follows ADC, SUBC)
...xA0xC
...wA0wC
Ý
w
1, HCw1
w
SPa1, A
[SP]
w
A, SPwSPb1
[VU]
,PL
w
w
ii (iie15 bits, 0 to 32k)
w
i(ie12 bits)
[SP]
w
PL,[SPb1
[SP]
w
PL,[SPb1
w
ROM (PU,A)
a
2, PL
w
a
2, PL
w
a
2, PL
w
w
w
PL,[SPb1
PCa1
[SP]
Bg1)
g
1)
Bg1)
Xg1)
A3...A0
[SP]
w
[VL]
w
]
w
]
w
[SP]
,PU
[SP]
,PU
[SP]
,PU
]
w
e
0
PU,SPb2, PCwii
PU,SPb2,PC9...0wi
b
[
SP
w
b
[
SP
w
b
[
SP
w
PU, SPb2, PCw0FF
e
Imm
e
Meml
i
Meml
l
Meml
]
1
]
1
1],GIEw1
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Page 31
Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction
opcode.
See the BYTES and CYCLES per INSTRUCTION table for details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
[B]
Direct Immed.
ADD 1/1 3/4 2/2
ADC 1/1 3/4 2/2
SUBC 1/1 3/4 2/2
AND 1/1 3/4 2/2
OR 1/1 3/4 2/2
XOR 1/1 3/4 2/2
IFEQ 1/1 3/4 2/2
IFNE 1/1 3/4 2/2
IFGT 1/1 3/4 2/2
IFBNE 1/1
DRSZ 1/3
SBIT 1/1 3/4
RBIT 1/1 3/4
IFBIT 1/1 3/4
RPND 1/1
Memory Transfer Instructions
Register
Indirect Auto Incr. & Decr.
[B][
][
X
XA,* 1/1 1/3 2/3 1/2 1/3
LD A,* 1/1 1/3 2/3 2/2 1/2 1/3
LD B, Imm 1/1 (IF B
LD B, Imm 2/2 (IF Bl15)
LD Mem, Imm 2/2 3/3 2/2
LD Reg, Imm 2/3
IFEQ MD, Imm 3/3
l
e
*
Memory location addressed by B or X or directly.
Direct Immed.
Instructions UsingA&C
CLRA 1/1
INCA 1/1
DECA 1/1
LAID 1/3
DCOR 1/1
RRCA 1/1
RLCA 1/1
SWAPA 1/1
SC 1/1
RC 1/1
IFC 1/1
IFNC 1/1
PUSHA 1/3
POPA 1/3
ANDSZ 2/2
Register Indirect
a
b
a,Xb
][
B
,B
X
Transfer of Control
Instructions
JMPL 3/4
JMP 2/3
JP 1/3
JSRL 3/5
JSR 2/5
JID 1/3
VIS 1/5
RET 1/5
RETSK 1/5
RETI 1/5
INTR 1/7
NOP 1/1
]
k
16)
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Page 32
Opcode Table
Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis
FE D C B A 9 8
JPb15 JPb31 LD 0F0,Ýi DRSZ 0F0 RRCA RC ADC A,Ýi ADC A,[B
JPb14 JPb30 LD 0F1,Ýi DRSZ 0F1 * SC SUBC A,Ýi SUB A,[B
a
JPb13 JPb29 LD 0F2,Ýi DRSZ 0F2 X A,[X
JPb12 JPb28 LD 0F3,Ýi DRSZ 0F3 X A,[X
]
b
]
JPb11 JPb27 LD 0F4,Ýi DRSZ 0F4 VIS LAID ADD A,Ýi ADD A,[B
JPb10 JPb26 LD 0F5,Ýi DRSZ 0F5 RPND JID AND A,Ýi AND A,[B
JPb9JP
JPb8JP
JPb7JP
JPb6JP
JPb5JP
JPb4JP
JPb3JP
JPb2JP
JPb1JP
JPb0JP
b
25 LD 0F6,Ýi DRSZ 0F6 X A,[X
b
24 LD 0F7,Ýi DRSZ 0F7 **OR A,ÝiORA,
b
23 LD 0F8,Ýi DRSZ 0F8 NOP RLCA LD A,Ýi IFC 8
b
22 LD 0F9,Ýi DRSZ 0F9 IFNE IFEQ IFNE IFNC 9
b
21 LD 0FA,Ýi DRSZ 0FA LD A,[X
b
20 LD 0FB,Ýi DRSZ 0FB LD A,[X
b
19 LD 0FC,Ýi DRSZ 0FC LD Md,Ýi JMPL X A,Md POPA C
b
18 LD 0FD,Ýi DRSZ 0FD DIR JSRL LD A,Md RETSK D
b
17 LD 0FE,Ýi DRSZ 0FE LD A,[X
b
16 LD 0FF,Ýi DRSZ 0FF **LD B,Ýi RETI F
A,[B
]
]
a
]
b
]
]
a
]
XA,[B
b
]
XA,[B
]
XA,[B
Ý
iA,
Md,
a
LD A,[B
LD A,[B
LD A,[B
]
b
]
]
Ý
IFEQ A,
IFGT A,
i IFEQ A,[B]2
Ý
i IFGT A,[B]3
XOR A,Ýi XOR A,[B
[
]
B
Ý
i
a
]
Ý
LD[B
,
i INCA A
b
]
Ý
LD[B
,
i DECA B
LD[B],Ýi RET E
]
]
]
]
]
0
1
4
5
6
7
http://www.national.com 32
Page 33
Opcode Table (Continued)
Upper Nibble Along X-Axis
Lower Nibble Along Y-Axis
76 5 4 3 2 1 0
IFBIT ANDSZ LD B,Ý0F IFBNE 0 JSR JMP JPa17 INTR 0
]
0,[B
IFBIT * LD B,Ý0E IFBNE 1 JSR JMP JPa18 JPa21
]
1,[B
IFBIT * LD B,Ý0D IFBNE 2 JSR JMP JPa19 JPa32
]
2,[B
IFBIT * LD B,Ý0C IFBNE 3 JSR JMP JPa20 JPa43
]
3,[B
IFBIT CLRA LD B,Ý0B IFBNE 4 JSR JMP JPa21 JPa54
]
4,[B
IFBIT SWAPA LD B,Ý0A IFBNE 5 JSR JMP JPa22 JPa65
]
5,[B
IFBIT DCORA LD B,Ý09 IFBNE 6 JSR JMP JPa23 JPa76
]
6,[B
IFBIT PUSHA LD B,Ý08 IFBNE 7 JSR JMP JPa24 JPa87
]
7,[B
SBIT RBIT LD B,Ý07 IFBNE 8 JSR JMP JPa25 JPa98
]
0,[B
SBIT RBIT LD B,Ý06 IFBNE 9 JSR JMP JPa26 JPa10 9
]
1,[B
SBIT RBIT LD B,Ý05 IFBNE 0A JSR JMP JPa27 JPa11 A
]
2,[B
SBIT RBIT LD B,Ý04 IFBNE 0B JSR JMP JPa28 JPa12 B
]
3,[B
SBIT RBIT LD B,Ý03 IFBNE 0C JSR JMP JPa29 JPa13 C
]
4,[B
SBIT RBIT LD B,Ý02 IFBNE 0D JSR JMP JPa30 JPa14 D
]
5,[B
SBIT RBIT LD B,Ý01 IFBNE 0E JSR JMP JPa31 JPa15 E
]
6,[B
SBIT RBIT LD B,Ý00 IFBNE 0F JSR JMP JPa32 JPa16 F
]
7,[B
Where,
Note: The opcode 60 Hex is also the opcode for IFBIT
Ý
i x000 –x0FF x000– x0FF
A,
]
0,[B
]
1,[B
]
2,[B
]
3,[B
]
4,[B
]
5,[B
]
6,[B
]
7,[B
i is the immediate data
Md is a directly addressed memory location
* is an unused opcode
x100–x1FF x100 –x1FF
x200–x2FF x200 –x2FF
x300–x3FF x300 –x3FF
x400–x4FF x400 –x4FF
x500–x5FF x500 –x5FF
x600–x6FF x600 –x6FF
x700–x7FF x700 –x7FF
x800–x8FF x800 –x8FF
x900–x9FF x900 –x9FF
xA00–xAFF xA00 – xAFF
xB00–xBFF xB00 – xBFF
xC00–xCFF xC00 –xCFF
xD00–xDFF xD00–xDFF
xE00–xEFF xE00–xEFF
xF00–xFFF xF00 – xFFF
Ý
i,A
Mask Options
The mask programmable options are shown below. The options are programmed at the same time as the ROM pattern
submission.
OPTION 1: CLOCK CONFIGURATION
4 1 Crystal Oscillator (CKI/10)
G7 (CKO) is clock generator
output to crystal/resonator
CKI is the clock input
4 2 Single-pin RC controlled
oscillator (CKI/10)
G7 is available as a HALT
restart and/or general purpose
input
OPTION 2: HALT
4 1 Enable HALT mode
4 2 Disable HALT mode
OPTION 3: BONDING OPTIONS
4 1 44-Pin PLCC
4 2 40-Pin DIP
4 3 N/A
4 4 28-Pin DIP
4 5 28-Pin SO
http://www.national.com33
Page 34
Development Support
SUMMARY
iceMASTERTM: IM-COP8/400ÐFull feature in-circuit em-
#
ulation for all COP8 products. A full set of COP8 Basic
and Feature Family device and package specific probes
are available.
COP8 Debug Module: Moderate cost in-circuit emulation
#
and development programming unit.
COP8 Evaluation and Programming Unit: EPU-
#
COP888GGÐlow cost in-circuit simulation and development programming unit.
Assembler: COP8-DEV-IBMA. A DOS installable cross
#
development Assembler, Linker, Librarian and Utility
Software Development Tool Kit.
C Compiler: COP8C. A DOS installable cross develop-
#
ment Software Tool Kit.
OTP/EPROM Programmer Support: Covering needs
#
from engineering prototype, pilot production to full production environments.
IceMASTER (IM) IN-CIRCUIT EMULATION
The iceMASTER IM-COP8/400 is a full feature, PC based,
in-circuit emulation tool development and marketed by
MetaLink Corporation to support the whole COP8 family of
products. National is a resale vendor for these products.
See
Figure 18
The iceMASTER IM-COP8/400 with its device specific
COP8 Probe provides a rich feature set for developing, testing and maintaining product:
Real-time in-circuit emulation; full 2.4V –5.5V operation
#
range, full DC-10 MHz clock. Chip options are programmable or jumper selectable.
Direct connection to application board by package com-
#
patible socket or surface assembly.
Full 32 kbyte of loadable programming space that over-
#
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated on
the probe as necessary.
Full 4k frame synchronous trace memory. Address, in-
#
struction, and 8 unspecified, circuit connectable trace
lines. Display can be HLL source (e.g., C source), assembly or mixed.
for configuration.
A full 64k hardware configurable break, trace on, trace
#
off control, and pass count increment events.
Tool set integrated interactive symbolic debuggerÐsup-
#
ports both assembler (COFF) and C Compiler (.COD)
linked object formats.
Real time performance profiling analysis; selectable
#
bucket defintion.
Watch windows, content updated automatically at each
#
execution break.
Instruction by instruction memory/register changes dis-
#
played on source window when in single step operation.
Single base unit and debugger software reconfigurable to
#
support the entire COP8 family; only the probe personality needs to change. Debugger software is processor customized, and reconfigured from a master model file.
Processor specific symbolic display of registers and bit
#
level assignments, configured from master model file.
Halt/Idle mode notification.
#
On-Line HELP customized to specific processor using
#
master model file.
Includes a copy of COP8-DEV-IBMA assembler and link-
#
er SDK.
IM Order Information
Base Unit
IM-COP8/400-1 iceMASTER Base Unit,
IM-COP8/400-2 iceMASTER Base Unit,
iceMASTER Probe
MHW-884EG28DWPC 28 DIP
MHW-888EG40DWPC 40 DIP
MHW-888EG44PWPC 44 PLCC
Adapter for SO Package
MHW-SOIC28 28 SO
110V Power Supply
220V Power Supply
FIGURE 18. COP8 iceMASTER Environment
http://www.national.com 34
TL/DD/9765– 26
Page 35
Development Support (Continued)
iceMASTER DEBUG MODULE (DM)
The iceMASTER Debug Module is a PC based, combination
in-circuit emulation tool and COP8 based OTP/EPROM programming tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products. National is a resale vendor for these products.
See
Figure 19
The iceMASTER Debug Module is a moderate cost development tool. It has the capability of in-circuit emulation for a
specific COP8 microcontroller and in addition serves as a
programming tool for COP8 OTP and EPROM product families. Summary of features is as follows:
Real-time in-circuit emulation; full operating voltage
#
range operation, full DC-10 MHz clock.
All processor I/O pins can be cabled to an application
#
development board with package compatible cable to
socket and surface mount assembly.
Full 32 kbyte of loadable programming space that over-
#
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated as
necessary.
100 frames of synchronous trace memory. The display
#
can be HLL source (C source), assembly or mixed. The
most recent history prior to a break is available in the
trace memory.
Configured break points; uses INTR instruction which is
#
modestly intrusive.
Software-only supported features are selectable.
#
Tool set integrated interactive symbolic debuggerÐsup-
#
ports both assembler (COFF) and C Compiler (.COD)
SDK linked object formats.
Instruction by instruction memory/register changes dis-
#
played when in single step operation.
for configuration.
Debugger software is processor customized, and recon-
#
figured from a master model file.
Processor specific symbolic display of registers and bit
#
level assignments, configured from master model file.
Halt/Idle mode notification.
#
Programming menu supports full product line of program-
#
mable OTP and EPROM COP8 products. Program data
is taken directly from the overlay RAM.
Programming of 44 PLCC and 68 PLCC parts requires
#
external programming adapters.
Includes wallmount power supply.
#
On-board VPPgenerator from 5V input or connection to
#
external supply supported. Requires V
ment per the family programming specification (correct
level is provided on an on-screen pop-down display).
On-line HELP customized to specific processor using
#
master model file.
Includes a copy of COP8-DEV-IBMA assembler and link-
#
er SDK.
Debug Module Unit
COP8-DM/888GG
Cable Adapters, Kits for COP888
DM-COP8/28D 28 DIP
DM-COP8/40D 40 DIP
DM-COP8/44P 44 PLCC
Adapter for SO Package
MHW-SOIC28 28 SO
DM Order Information
level adjust-
PP
FIGURE 19. COP8-DM Environment
TL/DD/9765– 27
http://www.national.com35
Page 36
Development Support (Continued)
iceMASTER EVALUATION PROGRAMMING UNIT (EPU)
The iceMASTER EPU-COP888GG is a PC based, in-circuit
simulation tool to support the feature family COP8 products.
See Figure 20
The simulation capability is a very low cost means of evaluating the general COP8 architecture. In addition, the EPU
has programming capability, with added adapters, for programming the whole COP8 product family of OTP and EPROM products. The product includes the following features:
Non-real-time in-circuit simulation. Program overlay
#
memory is PC resident; instructions are downloaded over
RS-232 as executed. Approximate performance is
20 kHz.
Includes a 40-pin DIP cable adapter. Other target pack-
#
ages are not supported. All processor I/O pins are cabled to the application development environment.
Full 32 kbyte of loadable programming space that over-
#
lays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated as
necessary.
On-chip timer and watch-dog execution are not well syn-
#
chronized to the instruction simulation.
100 frames of synchronous trace memory. The display
#
can be HLL source (e.g., C source), assembly or mixed.
The most recent history prior to a break is available in the
trace memory.
Up to eight software configured break points; uses INTR
#
instruction which is modestly intrusive.
Common look-feel debugger software across all Meta-
#
Link productsÐonly supported features are selectable.
for configuration.
Tool set integrated interactive symbolic debuggerÐsup-
#
ports both assembler (COFF) and C Compiler (.COD)
SDK linked object formats.
Instruction by instruction memory/register changes dis-
#
played when in single step operation.
Processor specific symbolic display of registers and bit
#
level assignments, configured from master model file.
Halt/Idle mode notification. Restart requires special han-
#
dling.
Programming menu supports full product line of program-
#
mable OTP and EPROM COP8 products. Only a 40 ZIF
socket is available on the EPU unit. Adapters are available for other part package configurations.
Integral wall mount power supply provides 5V and devel-
#
ops the required V
Includes a copy of COP8-DEV-IBMA assembler, linker
#
SDK.
Evaluation Programming Unit
EPU-COP888GG Evaluation Programming Unit
General Programming Adapters
COP8-PGMA-DS 28 and 20 DIP and SOIC
COP8-PGMA-DS44P 28 and 20 DIP and SOIC plus
to program parts.
PP
EPU Order Information
with debugger and
programmer control software
with 40 ZIF programming
socket.
adapter.
44 PLCC adapter.
FIGURE 20. EPU-COP8 Tool Environment
http://www.national.com 36
TL/DD/9765– 28
Page 37
Development Support (Continued)
COP8 ASSEMBLER/LINKER SOFTWARE DEVELOPMENT TOOL KIT
National Semiconductor offers a relocatable COP8 macro
cross assembler, linker, librarian and utility software development tool kit. Features are summarized as follows:
Basic and Feature Family instruction set by ‘‘device’’
#
type.
Nested macro capability.
#
Extensive set of assembler directives.
#
Supported on PC/DOS platform.
#
Generates National standard COFF output files.
#
Integrated Linker and Librarian.
#
Integrated utilities to generate ROM code file outputs.
#
DUMPCOFF utility.
#
This product is integrated as a part of MetaLink tools as a
development kit, fully supported by the MetaLink debugger.
It may be ordered separately or it is bundled with the MetaLink products at no additional cost.
Assembler SDK
COP8-DEV-IBMA Assembler SDK on installable
Order Information
3.5
PC/DOS Floppy Disk Drive
×
format. Periodic upgrades and
most recent version is available
on National’s BBS and Internet.
Approved List
Manufacturer
BP (800) 225-2102
Microsystems (713) 688-4600
Data I/O (800) 426-1045
HI–LO (510) 623-8860 Call Asia
ICE (800) 624-8949
Technology (919) 430-7915 Fax: 0-1226-370-434
MetaLink (800) 638-2423
Systems (408) 263-6667
General Fax:
Needhams (916) 924-8037
North
America
Fax: (713) 688-0920
(206) 881-6444 North America
Fax: (206) 882-1043
(602) 926-0797 Fax:a49-80 9123 86
Fax: (602) 693-0681
Fax: (916) 924-8065
COP8 C COMPILER
A C Compiler is developed and marketed by Byte Craft Limited. The COP8C compiler is a fully integrated development
tool specifically designed to support the compact embedded configuration of the COP8 family of products.
Features are summarized as follows:
ANSI C with some restrictions and extensions that opti-
#
mize development for the COP8 embedded application.
BITS data type extension. Register declarationÝpragma
#
with direct bit level definitions.
C language support for interrupt routines.
#
Expert system, rule based code generation and optimiza-
#
tion.
Performs consistency checks against the architectural
#
definitions of the target COP8 device.
Generates program memory code.
#
Supports linking of compiled object or COP8 assembled
#
object formats.
Global optimization of linked code.
#
Symbolic debug load format fully source level supported
#
by the MetaLink debugger.
SINGLE CHIP OTP/EMULATOR SUPPORT
The COP8 family is supported by single chip OTP emulators. For detailed information refer to the emulator specific
datasheet and the emulator selection table below:
Europe Asia
a
49-8152-4183
a
49-8856-932616
a
44-0734-440011 Call
a
44-1226-767404
a
49-80 9156 96-0
a
41-1-9450300
a
852-234-16611
a
852-2710-8121
a
886-2-764-0215
a
Fax:
886-2-756-6403
a
852-737-1800
a
886-2-917-3005
a
886-2-911-1283
http://www.national.com37
Page 38
Development Support (Continued)
OTP Emulator Ordering Information
Device Number
COP87L84EGN-XE Crystal 28 DIP COP884CG
COP87L84EGM-XE Crystal 28 SO COP884CG
COP87L88EGN-XE Crystal 40 DIP COP888CG
COP87L88EGV-XE Crystal 44 PLCC COP888CG
INDUSTRY WIDE OTP/EPROM PROGRAMMING
SUPPORT
Programming support, in addition to the MetaLink development tools, is provided by a full range of independent approved vendors to meet the needs from the engineering
laboratory to full production.
AVAILABLE LITERATURE
For more information, please see the COP8 Basic Family
User’s Manual, Literature Number 620895, COP8 Feature
Family User’s Manual, Literature Number 620897 and National’s Family of 8-bit Microcontrollers COP8 Selection
Guide, Literature Number 630009.
DIAL-A-HELPER SERVICE
Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Information System that may be accessed as a Bulletin Board
System (BBS) via data modem, as an FTP site on the Internet via standard FTP client application or as an FTP site on
the Internet using a standard Internet browser such as Netscape or Mosaic.
The Dial-A-Helper system provides access to an automated
information storage and retrieval system. The system capabilities include a MESSAGE SECTION (electronic mail,
when accessed as a BBS) for communication to and from
the Microcontroller Applications Group and a FILE SECTION which consists of several file areas where valuable
application software and utilities could be found.
DIAL-A-HELPER BBS via a Standard Modem
Modem: CANADA/U.S.: (800) NSC-MICRO
EUROPE: (
Baud: 14.4k
Set-up: Length: 8-Bit
Operation: 24 Hours, 7 Days
Clock
Option
Package Emulates
(800) 672-6427
a
49) 0-8141-351332
Parity: None
Stop Bit: 1
DIAL-A-HELPER via FTP
ftp nscmicro.nsc.com
user: anonymous
password: username
@
yourhost.site.domain
DIAL-A-HELPER via a WorldWide Web Browser
ftp://nscmicro.nsc.com
National Semiconductor on the WorldWide Web
See us on the WorldWide Web at: http://www.national.com
CUSTOMER RESPONSE CENTER
Complete product information and technical support is available from National’s customer response centers.
CANADA/U.S.: Tel: (800) 272-9959
email: support@tevm2.nsc.com
EUROPE: email: europe.support@nsc.com
Deutsch Tel:
English Tel:
a
49 (0) 180-530 85 85
a
49 (0) 180-532 78 32
Fran3ais Tel:a49 (0) 180-532 93 58
Italiano Tel:
JAPAN: Tel:
a
49 (0) 180-534 16 80
a
81-043-299-2309
S.E. ASIA: Beijing Tel: (a86) 10-6856-8601
Shanghai Tel: (a86) 21
Hong Kong Tel: (a852) 2737-1600
Korea Tel: (a82) 2-3771-6909
Malaysia Tel: (a60-4) 644-9061
Singapore Tel: (a65) 255-2226
Taiwan Tel:
a
886-2-521-3288
AUSTRALIA: Tel: (a61) 3-9558-9999
INDIA: Tel: (a91) 80-559-9467
http://www.national.com 38
Page 39
http://www.national.com39
Page 40
Physical Dimensions inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package (N)
Order Number COP884CG-XXX/WM
NS Package Number M28B
http://www.national.com 40
Page 41
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number COP884CG-XXX/N
NS Package Number N28B
Molded Dual-In-Line Package (N)
Order Number COP888CG-XXX/N
NS Package Number N40A
http://www.national.com41
Page 42
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Plastic Leaded Chip Carrier (V)
Order Number COP888CG-XXX/V
NS Package Number V44A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
COP884CG/COP888CG 8-Bit Microcontroller with UART and Three Multi-Function Timers
Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax:
Arlington, TX 76017 Email: europe.support@nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel:
Fax: 1(800) 737-7018 English Tel:
http://www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Fran3ais Tel:
Italiano Tel:a49 (0) 180-534 16 80 Fax: (852) 2736-9960
a
49 (0) 180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2308
a
49 (0) 180-530 85 85 Tsimshatsui, Kowloon
a
49 (0) 180-532 78 32 Hong Kong
a
49 (0) 180-532 93 58 Tel: (852) 2737-1600
Page 43
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
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