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COP87L88CFV-XE
Datasheet (NSC)
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Datasheet COP87L88CFV-XE, COP87L88CFN-XE, COP87L84CFN-XE Datasheet (NSC)

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Page 1
COP87L88CF 8-Bit CMOS OTP Microcontrollers with 16k Memory and A/D Converter
General Description
The COP87L88CF OTP (One Time Programmable) micro­controllers are highly integrated COP8
™
Feature core de­vices with 16k memory and advanced features including an A/D converter. These multi-chip CMOS devices are suited for applications requiring a full featured controller with an 8-bit A/D converter, and as pre-production devices for a masked ROM design. Lower cost pin and software compat­ible 16k ROM versions are available (COP888CF) as well as a range of COP8 software and hardware development tools.
Family features include an 8-bit memory mapped architec­ture, 10 MHz CKI (-XE=crystal oscallator) with 1 µs instruc­tion cycle, two multi-function 16-bit timer/counters, MICROWIRE/PLUS
™
serial I/O, one 8-bit/8-channel A/D converter with prescaler and both differential and single ended modes, two power saving HALT/IDLE modes, idle timer, MIWU, high current outputs, software selectable I/O options, WATCHDOG
™
timer and Clock Monitor, 2.7V to
5.5V operation and 28/40/44 pin packages. Devices included in this datasheet are:
Device Memory (bytes) RAM (bytes) I/O Pins Packages Temperature
COP87L84CF 16k OTP EPROM 128 24 28 DIP/SOIC -40 to +85˚C COP87L88CF 16k OTP EPROM 128 36/40 40 DIP, 44 PLCC -40 to +85˚C
Key Features
n A/D converter (8-bit, 8-channel, with prescaler and both
differential and single ended modes)
n Two 16-bit timers, each with two 16-bit registers
supporting: — Processor Independent PWM mode — External Event counter mode — Input Capture mode
n 16 kbytes on-board OTP EPROM with security feature n 128 bytes on-board RAM
Additional Peripheral Features
n Idle Timer n Multi-Input Wake Up (MIWU) with optional interrupts (8) n WATCHDOG and Clock Monitor logic n MICROWIRE/PLUS serial I/O
I/O Features
n Software selectable I/O options (TRI-STATE™Output,
Push-Pull Output, Weak Pull-Up Input, High Impedance Input)
n High current outputs n Packages:
— 44 PLCC with 38 I/O pins — 40 DIP with 34 I/O pins — 28 DIP/SO with 22 I/O pins
n Schmitt trigger inputs on Port G
CPU/Instruction Set Feature
n 1 µs instruction cycle time n Ten multi-source vectored interrupts servicing
— External interrupt with selectable edge — Idle Timer T0 — Two Timers (Each with 2 interrupts) — MICROWIRE/PLUS — Multi-Input Wake Up — Software Trap — Default VIS (default interrupt)
n Versatile and easy to use instruction set n 8-bit Stack Pointer (SP)—stack in RAM n Two 8-bit Register Indirect Data Memory Pointers (B, X)
Fully Static CMOS
n Two power saving modes: HALT and IDLE n Single supply operation: 2.7V to 5.5V n Temperature ranges: -40˚C to +85˚C
Development Support
n Emulation device for the COP888CF/COP884CF n Real time emulation and full program debug offered by
MetaLink Development System
COP8™is a trademark of National Semiconductor Corporation. MICROWIRE
™
is a trademark of National Semiconductor Corporation.
MICROWIRE/PLUS
™
is a trademark of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
WATCHDOG
™
is a trademark of National Semiconductor Corporation.
iceMASTER
™
is a trademark of MetaLink Corporation.
September 1999
COP87L88CF 8-Bit CMOS OTP Microcontrollers with 16k Memory and A/D Converter
© 1999 National Semiconductor Corporation DS101134 www.national.com
Page 2
Block Diagram
DS101134-1
FIGURE 1. Block Diagram
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Page 3
Connection Diagrams
Plastic Chip Carrier
DS101134-2
Top View
Order Number COP87L88CFV-XE
See NS Plastic Chip Package Number V44A
Dual-In-Line Package
DS101134-37
Top View
Order Number COP87L84CFN-XE or
COP87L84CFM-XE
See NS Package Number N28B or M28B
Dual-In-Line Package
DS101134-4
Top View
Order Number COP87L84CFN-XE,
See NS Molded Package Number N40A
Note: -X=Crystal Oscillator
-E=Halt Mode Enable
FIGURE 2. Connection Diagrams
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Page 4
Connection Diagrams (Continued)
Pinouts for 28-, 40-, and 44-Pin Packages
Port Type Alt. Fun Alt. Fun 28-Pin Pack. 40-Pin Pack. 44-Pin Pack.
L0 I/O MIWU 11 17 — L1 I/O MIWU 12 18 — L2 I/O MIWU 13 19 19 L3 I/O MIWU 14 20 20 L4 I/O MIWU T2A 15 21 25 L5 I/O MIWU T2B 16 22 26 L6 I/O MIWU 17 23 27 L7 I/O MIWU 18 24 28 G0 I/O INT 25 35 39 G1 WDOUT 26 36 40 G2 I/O T1B 27 37 41 G3 I/O T1A 28 38 42 G4 I/O SO 1 3 3 G5 I/O SK 2 4 4 G6 I SI 3 5 5 G7 I/CKO HALT Restart 4 6 6 I0 I ACH0 7 9 9 I1 I ACH1 8 10 10 I2 I ACH2 11 11 I3 I ACH3 12 12 I4 I ACH4 13 13 I5 I ACH5 14 14 I6 I ACH6 15 I7 I ACH7 16 D0 O 19 25 29 D1 O 20 26 30 D2 O 21 27 31 D3 O 22 28 32 D4 O 29 33 D5 O 30 34 D6 O 31 35 D7 O 32 36 C0 I/O 39 43 C1 I/O 40 44 C2 I/O 1 1 C3 I/O 2 2 C4 I/O 21 C5 I/O 22 C6 I/O 23 C7 I/O 24 V
REF
+V
REF
10 16 18 AGND AGND 9 15 17 V
CC
688 GND 23 33 37 CKI 5 7 7 RESET
24 34 38
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Page 5
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (V
CC
)7V
Voltage at Any Pin −0.3V to V
CC
+ 0.3V
Total Current into V
CC
Pin (Source) 100 mA Total Current out of GND Pin (Sink) 110 mA Storage Temperature Range −65˚C to +140˚C
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Operating Voltage 2.7 5.5 V Power Supply Ripple (Note 2) Peak-to-Peak 0.1 V
CC
V
Supply Current (Note 3)
CKI=10 MHz V
CC
=
5.5V, t
c
=
1
µs
16.5 mA
CKI=4 MHz V
CC
=
4V, t
c
=
2.5
µs
6.5 mA
HALT Current (Note 4) V
CC
=
5.5V, CKI=0
MHz
12 µA
IDLE Current
CKI=10 MHz V
CC
=
5.5V, t
c
=
1
µs
3.5 mA
CKI=1 MHz V
CC
=
4V, t
c
=
10 µs 0.7 mA Input Levels RESET
Logic High 0.8 V
CC
V
Logic Low 0.2 V
CC
V
CKI (External and Crystal Osc. Modes)
Logic High 0.7 V
CC
V
Logic Low 0.2 V
CC
V
All Other Inputs
Logic High 0.7 V
CC
V
Logic Low 0.2 V
CC
V
Hi-Z Input Leakage V
CC
=
5.5V −2 +2 µA
Input Pullup Current V
CC
=
5.5V 40 250 µA
G and L Port Input Hysteresis 0.05 V
CC
0.35 V
CC
V Output Current Levels D Outputs
Source V
CC
=
4.5V, V
OH
=
3.3V
0.4 mA
Sink V
CC
=
4.5V, V
OL
=
1V
10 mA
All Others
Source (Weak Pull-Up Mode) V
CC
=
4.5V, V
OH
=
2.7V
10 100 µA
Source (Push-Pull Mode) V
CC
=
4.5V, V
OH
=
3.3V
0.4 mA
Sink (Push-Pull Mode) V
CC
=
4.5V, V
OL
=
0.4V
1.6 mA
TRI-STATE Leakage V
CC
=
5.5V −2 +2 µA Allowable Sink/Source Current per Pin
D Outputs (Sink) 15 mA
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Page 6
DC Electrical Characteristics (Continued)
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
All others 3mA
Maximum Input Current without Latchup (Note 9)
T
A
=
25˚C
±
100 mA
RAM Retention Voltage, V
r
500 ns Rise 2 V
and Fall Time (Min) Input Capacitance 7pF Load Capacitance on D2 1000 pF
Note 2: Rate of voltage change must be less then 0.5 V/ms. Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 4: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V
CC
, L and G0–G5 configured as
outputs and set high. The D port set to zero. The A/D is disabled. V
REF
is tied to AGND (effectively shorting the Reference resistor). The clock monitor is disabled.
Note 5: The user must guarantee that D2 pin does not source more than 10 ma during RESET. If D2 sources more than 10 mA during reset, the device will go into programming mode.
AC Electrical Characteristics
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (t
c
) Crystal, Resonator 1 DC µs R/C Oscillator 3DCµs
Inputs
t
SETUP
4V ≤ VCC≤ 6V 200 ns
t
HOLD
4V ≤ VCC≤ 6V 60 ns
Output Propagation Delay (Note 6) R
L
=
2.2k, C
L
=
100 pF
t
PD1,tPD0
SO, SK 4V ≤ VCC≤ 6V 0.7 µs All Others 4V ≤ V
CC
≤ 6V 1 µs
MICROWIRE
™
Setup Time (t
UWS
)20ns
MICROWIRE Hold Time (t
UWH
)56ns
MICROWIRE Output Propagation Delay (t
UPD
) 220 ns
Input Pulse Width
Interrupt Input High Time 1 t
c
Interrupt Input Low Time 1 t
c
Timer Input High Time 1 t
c
Timer Input Low Time 1 t
c
Reset Pulse Width 1 µs
Note 6: The output propagation delay is referenced to end of the instruction cycle where the output change occurs.
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Page 7
A/D Converter Specifications
V
CC
=
5V
±
10%(VSS− 0.050V) ≤ Any Input ≤ (VCC+ 0.050V)
Parameter Conditions Min Typ Max Units
Resolution 8 Bits Reference Voltage Input AGND=0V 3 V
CC
V
Absolute Accuracy V
REF
=
V
CC
±
2 LSB
Non-Linearity V
REF
=
V
CC
Deviation from the
±
1
⁄
2
LSB
Best Straight Line
Differential Non-Linearity V
REF
=
V
CC
±
1
⁄
2
LSB Input Reference Resistance 1.6 4.8 kΩ Common Mode Input Range (Note 10) AGND V
REF
V
DC Common Mode Error
±
1
⁄
4
LSB Off Channel Leakage Current 1 µA On Channel Leakage Current 1 µA A/D Clock Frequency (Note 8) 0.1 1.67 MHz Conversion Time (Note 7) 12 A/D Clock
Cycles
Note 7: Conversion Time includes sample and hold time. Note 8: See Prescaler description. Note 9: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than V
CC
and the pins will have sink current to VCCwhen biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC). The effective resis­tance to V
CC
is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 10: For V
IN
(−)≥VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input. The diodes will forward conduct for analog
input voltages below ground or above the V
CC
supply.Be careful, during testing at low VCClevels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode.This means that as long as the analog V
IN
does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDCto 5 VDCinput
voltage range will therefore require a minimum supply voltage of 4.950 V
DC
over temperature variations, initial tolerance and loading. The voltage on any analog input
should be −0.3V to V
CC
+0.3V.
DS101134-26
FIGURE 3. MICROWIRE/PLUS Timing
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Page 8
Typical Performance Characteristics (−40˚C to +85˚C)
Halt— I
DD
vs V
CC
DS101134-29
Idle— I
DD
(Crystal Clock Option)
DS101134-30
Dynamic— I
DD
(Crystal Clock Option)
DS101134-31
Port L/C/G Weak Pull-Up Source Current
DS101134-32
Port L/C/G Push-Pull Source Current
DS101134-33
Port L/C/G Push-Pull Sink Current
DS101134-34
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Page 9
Typical Performance Characteristics (−40˚C to +85˚C) (Continued)
Pin Descriptions
VCCand GND are the power supply pins. V
REF
and AGND are the reference voltage pins for the
on-board A/D converter. CKI is the clock input. This can come from an R/Cgenerated
oscillator, or a crystal oscillator (in conjunction with CKO). See Oscillator Description section.
RESET is the master reset input. See Reset Description sec­tion.
The device contains three bidirectional 8-bit I/O ports (C, G and L), where each individual bit may be independently con­figured as an input (Schmitt trigger inputs on ports G and L), output or TRI-STATE under program control. Three data memory address locations are allocated for each of these I/O ports. Each I/O port has two associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATAregister.A memory mapped address is also re­served for the input pins of each I/O port. (See the memory map for the various addresses associated with the I/O ports.)
Figure 4
shows the I/O port configurations. The DATA and CONFIGURATION registers allow for each port bit to be in­dividually configured undersoftware control as shown below:
CONFIGURA-
TION
DATA
Port Set-Up
Register Register
0 0 Hi-Z Input
(TRI-STATE Output) 0 1 Input with Weak Pull-Up 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output
PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers on the inputs.
Port L supports Multi-Input Wakeup(MIWU) on all eightpins. L4 and L5 are used for the timer input functions T2A and T2B. L0 and L1 are not available on the 44-pinversion of the device, since they are replaced by V
REF
and AGND. L0 and L1 are not terminated on the 44-pin version. Consequently, reading L0 or L1 asinputs willreturn unreliabledata with the 44-pin package, so this data should be masked out with user software when the L port is read for input data. It is recom­mended that the pins be configured as outputs.
Port L has the following alternate features:
L7 MIWU L6 MIWU L5 MIWU or T2B L4 MIWU or T2A L3 MIWU L2 MIWU L1 MIWU L0 MIWU
Port D Source Current
DS101134-35
Port D Sink Current
DS101134-36
DS101134-6
FIGURE 4. I/O Port Configurations
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Page 10
Pin Descriptions (Continued)
Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input pin (G6), and two dedicated output pins (G1 and G7). Pins G0 and G2–G6 all have Schmitt Triggers on their inputs. Pin G1 serves as the dedicated WDOUT WATCHDOG output, while pin G7 is either input or output depending on the oscil­lator mask option selected. With the crystal oscillator option selected, G7 serves as the dedicated output pin for the CKO clock output. With the single-pin R/C oscillator mask option selected, G7 serves as a general purpose input pin, but is also used to bring the device outof HALT mode with a low to high transition on G7. There are two registers associated with the G Port, a data register and a configuration register. Therefore, each of the 5 I/O bits (G0, G2–G5) can be indi­vidually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO clock output pin or general purpose input (R/C clock configu­ration), the associated bits in the data and configuration reg­isters for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits will re­turn zeros.
Note that the chip will be placed in the HALTmode by writing a “1” to bit 7 of the Port G Data Register. Similarly the chip will be placed in the IDLE mode by writinga “1” to bit6 of the Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register en­ables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set high, enables the clock start up delay after HALT when the R/C clock configuration is used.
Config Reg. Data Reg.
G7 CLKDLY HALT
G6 Alternate SK IDLE Port G has the following alternate features: G6 SI (MICROWIRE Serial Data Input) G5 SK (MICROWIRE Serial Clock) G4 SO (MICROWIRE Serial Data Output) G3 T1A (Timer T1 I/O) G2 T1B (Timer T1 Capture Input) G0 INTR (External Interrupt Input) Port G has the following dedicated functions: G7 CKO Oscillator dedicated output or general purpose
input
G1 WDOUT WATCHDOG and/or Clock Monitor dedicated
output.
Port I is an 8-bit Hi-Z input port, and also provides the analog inputs to the A/D converter.The 28-pin devicedoes not have a full complement of Port I pins. The unavailable pins arenot terminated (i.e. they are floating). A read operation from these unterminated pins will return unpredictable values. The user should ensure that the software takes this into ac­count by either masking out these inputs, or else restricting the accesses to bit operations only. If unterminated, Port I pins will draw power only when addressed.
Port D is an 8-bit output port that is preset high when RESET goes low. The user can tie two or more D port outputs (ex­cept D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the ex-
ternal loads on this pin must ensure that the output voltages stay above 0.8 V
CC
to prevent the chip from entering special modes. Also
keep the external loading on D2 to less than 1000pF.
Functional Description
The architecture of the device is modified Harvard architec­ture. With the Harvard architecture, the control store pro­gram memory (ROM) is separated from the data store memory (RAM). Both ROM and RAM have their own sepa­rate addressing space with separate address buses. The ar­chitecture, though based on Harvard architecture, permits transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (t
c
) cycle time. There are five CPU registers: A is the 8-bit Accumulator Register PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/ interrupt stack (in RAM). The SP is initialized to RAM ad­dress 06F with reset.
All the CPU registers are memory mapped with the excep­tion of the Accumulator (A) and the Program Counter (PC).
PROGRAM MEMORY
Program memory consists of 4096 bytes of OTP EPROM. These bytes may hold program instructions or constant data (data tables for the LAID instruction, jump vectors forthe JID instruction, and interrupt vectors for the VIS instruction).The program memory is addressed by the 15-bit program counter (PC). All interrupts vector to program memory loca­tion 0FF Hex.
The device can be configured to inhibit external reads of the program memory. This is done by programming the Security Byte.
SECURITY FEATURE
The program memory array has an associate Security Byte that is located outside of the program address range. This byte can be addressed only from programming mode by a programmer tool.
Security is an optional feature and can only be asserted after the memory array has been programmed and verified. A se­cured part will read all 00(hex) by a programmer. The part will fail Blank Check and will fail Verify operations. A Read operation will fill the programmer’s memory with 00(hex). The Security Byte itself is always readable with value of 00(hex) if unsecure and FF(hex) if secure.
DATA MEMORY
The data memory address space includes the on-chip RAM and data registers, the I/O registers (Configuration, Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, and the various registers, and counters associated
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Page 11
Functional Description (Continued)
with the timers (with the exception of the IDLE timer). Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers.
The device has 128 bytes of RAM. Sixteen bytes of RAM are mapped as “registers” at addresses 0F0 to 0FF Hex. These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory pointer registers X, SP,and B are memory mapped into this space at address locations 0FC to 0FE Hex respectively, with the other registers (other than reserved register 0FF) being available for general us­age.
The instruction set permits any bit in memoryto be set,reset or tested. All I/O and registers (except A and PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested. The accumula­tor (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
Reset
The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, and with both the WATCHDOG service window bits set and the Clock Monitor bit set. The WATCHDOG and Clock Monitor detector circuits are inhibited during reset. The WATCHDOG service window bits are initialized to the maximum WATCHDOGser­vice window of 64k t
c
clock cycles. The Clock Monitor bit is initialized high, and will cause a Clock Monitor error following reset if the clock hasnot reachedthe minimumspecified fre-
quency at the termination of reset. A Clock Monitor error will cause an active low erroroutput on pin G1.This erroroutput will continue until 16–32 t
c
clock cycles following the clock frequency reaching the minimum specified value, at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in
Figure 5
should be used to ensure that the RESET pin is held low until the power sup­ply to the chip stabilizes.
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin which can be between DC and 10 MHz. The CKO output clock is on pin G7 (crystal configuration). The CKI input fre­quency is divided down by 10 to produce the instruction cycle clock (1/t
c
).
Figure 6
shows the Crystal and R/C diagrams.
CRYSTAL OSCILLATOR
CKI and CKO can beconnected tomake aclosed loopcrys­tal (or resonator) controlled oscillator.
Table 1
shows the component values required for various
standard crystal values.
R/C OSCILLATOR
Table 2
shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
DS101134-7
RC>5 x Power Supply Rise Time
FIGURE 5. Recommended Reset Circuit
DS101134-8
DS101134-9
FIGURE 6. Crystal and R/C Oscillator Diagrams
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Page 12
Oscillator Circuits (Continued)
TABLE 1. Crystal Oscillator Configuration, T
A
=
25˚C
R1 R2 C1 C2 CKI
Freq
Conditions
(kΩ)(MΩ) (pF) (pF) (MHz)
0 1 30 30–36 10 V
CC
=
5V
0 1 30 30–36 4 V
CC
=
5V
0 1 200 100–150 0.455 V
CC
=
5V
TABLE 2. R/C Oscillator Configuration, T
A
=
25˚C
R C CKI Freq Instr.
Cycle
Conditions
(kΩ) (pF) (MHz) (µs)
3.3 82 2.2 to 2.7 3.7 to 4.6 V
CC
=
5V
5.6 100 1.1 to 1.3 7.4 to 9.0 V
CC
=
5V
6.8 100 0.9 to 1.1 8.8 to 10.8 V
CC
=
5V
Note: 3k ≤ R ≤ 200k
50 pF ≤ C ≤ 200 pF
Control Registers
CNTRL Register (Address X'00EE)
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0
Bit 7 Bit 0
The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits:
T1C3 Timer T1 mode control bit T1C2 Timer T1 mode control bit T1C1 Timer T1 mode control bit T1C0 Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt Pending Flag in timer mode 3
MSEL Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
IEDG External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
PSW Register (Address X'00EF)
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 7 Bit 0
The PSW register contains the following select bits:
HC Half Carry Flag C Carry Flag T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
RA in mode 1, T1 Underflow in Mode 2, T1A capture edge in mode 3)
T1ENA Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge EXPND External interrupt pending BUSY MICROWIRE/PLUS busy shifting flag EXEN Enable external interrupt GIE Global interrupt enable (enables interrupts)
The Half-Carry flag is also affected by all the instructions that affect the Carry flag. The SC (Set Carry) and R/C (Reset Carry) instructions will respectively set or clear both the carry flags. In addition to the SC and R/C instructions, ADC, SUBC, RRC and RLC instructions affect the Carry and Half Carry flags.
ICNTRL Register (Address X'00E8)
Reserved LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB Bit 7 Bit 0
The ICNTRL register contains the following bits:
Reserved This bit is reserved and must be zero LPEN L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt) T0PND Timer T0 Interrupt pending T0EN Timer T0 Interrupt Enable (Bit 12 toggle) µWPND MICROWIRE/PLUS interrupt pending µWEN Enable MICROWIRE/PLUS interrupt T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-
ture edge T1ENB Timer T1 Interrupt Enable for T1B Input cap-
ture edge
T2CNTRL Register (Address X'00C6)
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB Bit 7 Bit 0
The T2CNTRL control register contains the following bits:
T2C3 Timer T2 mode control bit T2C2 Timer T2 mode control bit T2C1 Timer T2 mode control bit T2C0 Timer T2 Start/Stop control in timer
modes 1 and 2, T2 Underflow Interrupt Pend-
ing Flag in timer mode 3 T2PNDA Timer T2 Interrupt Pending Flag (Autoreload
RA in mode 1, T2 Underflow in mode 2, T2A
capture edge in mode 3) T2ENA Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-
ture edge T2ENB Timer T2 Interrupt Enable for Timer Underflow
or T2B Input capture edge
Timers
The device contains a very versatile set of timers (T0, T1, T2). All timers and associated autoreload/capture registers power up containing random data.
Figure 7
shows a block diagram for the timers.
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining real time and low power with the IDLE mode. This IDLE mode support is furnished by the IDLE timer T0, which is a 16-bit timer. The TimerT0 runs continuously at the fixed rate of the instruction cycle clock, t
c
. The user cannot read or
write to the IDLE Timer T0, which is a count down timer. The Timer T0 supports the following functions:
Exit out of the Idle Mode (See Idle Mode description) WATCHDOG logic (See WATCHDOG description) Start up delay out of the HALT mode
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Timers (Continued)
c
=
1 µs).A control flag T0EN allows the in­terrupt from the thirteenth bit of Timer T0 to be enabled or disabled. Setting T0EN will enable the interrupt, while reset­ting it will disable the interrupt.
TIMER T1 AND TIMER T2
The device has a set of two powerful timer/counter blocks, T1 and T2. The associated features and functioning of a timer block are described by referring to the timer block Tx. Since the two timer blocks, T1and T2, areidentical, allcom­ments are equally applicable to either timer block.
Each timer block consists of a 16-bit timer, Tx, and two sup­porting 16-bit autoreload/capture registers, RxA and RxB. Each timer block has two pins associated with it, TxA and TxB. The pin TxA supports I/O required by the timer block, while the pin TxB is an input to the timer block.The powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead. The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and Input Cap­ture mode.
The control bits TxC3, TxC2, and TxC1 allow selection of the different modes of operation.
Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the COP888CF to generate a PWM signal with very minimal user intervention. The user only has to define the parameters of the PWM sig­nal (ON time and OFF time). Once begun, the timer block will continuously generate the PWM signal completely indepen­dent of the microcontroller. The user software services the timer block only when the PWM parameters require updat­ing.
In this mode the timer Tx counts down at a fixed rate of t
c
. Upon every underflow the timer is alternately reloaded with the contents of supporting registers, RxA and RxB. The very first underflow of the timer causes the timer to reload from the register RxA. Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register RxB.
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the timer for PWM mode operation.
Figure 8
shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxAoutput pin. The underflows can also be programmed to generate in­terrupts.
Underflows from the timer are alternately latched into two pending flags, TxPNDA and TxPNDB. The user must reset these pending flags under software control. Two control en­able flags, TxENA and TxENB, allow the interrupts from the timer underflow to be enabled or disabled. Setting the timer enable flag TxENA will cause an interrupt when a timer un­derflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be re­loaded into the timer. Resetting the timer enable flags will disable the associated interrupts.
Either or both of the timer underflow interrupts may be en­abled. This gives the user the flexibility of interrupting once per PWM period on either the rising or falling edge of the PWM output. Alternatively, the user may choose to interrupt on both edges of the PWM output.
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent PWM mode described above. The main difference is that the timer,Tx, is clocked by the input signal fromthe TxA pin. The Tx timer control bits,TxC3, TxC2 and TxC1 allow the timer to be clocked either on a positive or negative edge from the TxA pin. Underflows from the timer are latched into the TxP­NDA pending flag. Setting the TxENAcontrol flag will cause an interrupt when the timer underflows.
Figure 9
shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxApin is being
used as the counter input clock.
DS101134-11
FIGURE 7. Timers
DS101134-13
FIGURE 8. Timer in PWM Mode
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Timers (Continued)
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or time external events by placing the timer block, Tx, in the in­put capture mode.
In this mode, the timer Tx is constantlyrunning at thefixed t
c
rate. The two registers, RxA and RxB, act as capture regis­ters. Each register acts in conjunction with a pin. The register RxAacts in conjunction with the TxApin and the register RxB acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a trigger event occurs on its corresponding pin. Control bits, TxC3, TxC2 and TxC1, allow the trigger events to be speci­fied either as a positive or a negative edge. The trigger con­dition for each input pin can be specified independently.
Underflows from the timer can also be programmed to gen­erate interrupts. Underflows are latched into the timer TxC0 pending flag (the TxC0 control bit serves as the timer under­flow interrupt pending flag in the Input Capture mode). Con­sequently, the TxC0 control bit should be reset when enter­ing the Input Capture mode. The timer underflow interrupt is enabled with the TxENA control flag. When a TxA interrupt occurs in the Input Capture mode, the user must check both the TxPNDA and TxC0 pending flags in order to determine whether a TxA input capture or a timer underflow (or both) caused the interrupt.
Figure 10
shows a block diagram of the timer in Input Cap-
ture mode.
TIMER CONTROL FLAGS
The control bits and their functions are summarized below.
TxC3 Timer mode control TxC2 Timer mode control TxC1 Timer mode control TxC0 Timer Start/Stop controlin Modes 1and 2 (Pro-
cessor Independent PWM and External Event Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture) TxPNDA Timer Interrupt Pending Flag TxENA Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled TxPNDB Timer Interrupt Pending Flag TxENB Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
DS101134-14
FIGURE 9. Timer in External Event Counter Mode
DS101134-15
FIGURE 10. Timer in Input Capture Mode
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Timers (Continued)
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
Mode TxC3 TxC2 TxC1 Description
Interrupt A
Source
Interrupt B
Source
Timer
Counts On
1
1 0 1 PWM: TxA Toggle Autoreload RA Autoreload RB t
C
1 0 0 PWM: No TxA
Toggle
Autoreload RA Autoreload RB
t
C
2
0 0 0 External Event
Counter
Timer Underflow
Pos. TxB Edge Pos. TxA
Edge
0 0 1 External Event
Counter
Timer Underflow
Pos. TxB Edge Pos. TxA
Edge
3
0 1 0 Captures: Pos. TxA Edge Pos. TxB Edge t
C
TxA Pos. Edge or Timer TxB Pos. Edge Underflow
1 1 0 Captures: Pos. TxA Neg. TxB t
C
TxA Pos. Edge Edge or Timer Edge TxB Neg. Edge Underflow
0 1 1 Captures: Neg. TxA Neg. TxB t
C
TxA Neg. Edge Edge or Timer Edge TxB Neg. Edge Underflow
1 1 1 Captures: Neg. TxA Neg. TxB t
C
TxA Neg. Edge Edge or Timer Edge TxB Neg. Edge Underflow
Power Save Modes
The device offers the user two power save modes of opera­tion: HALT and IDLE. In the HALT mode, all microcontroller activities are stopped. In the IDLE mode, the on-board oscil­lator circuitry and timer T0 are active but all other microcon­troller activities are stopped. In either mode, all on-board RAM, registers, I/O states, and timers (with the exception of T0) are unaltered.
HALT MODE
The device is placed in the HALTmode by writing a “1” to the HALT flag (G7 data bit). All microcontroller activities, includ­ing the clock, timers, and A/D converter, are stopped. The WATCHDOG logic is disabled during the HALT mode. How­ever, the clock monitor circuitry if enabled remains active and will cause the WATCHDOG output pin (WDOUT) to go low. If the HALTmode is usedand theuser does not want to activate the WDOUT pin, the Clock Monitor should be dis­abled after the device comes out of reset (resetting the Clock Monitor control bit with the first write to the WDSVR register). In the HALTmode, the powerrequirements ofthe device are minimal and the applied voltage (V
CC
) may be decreased to
V
r(Vr
=
2.0V) without altering the state of the machine.
The device supports three different ways of exiting the HALT mode. The first method of exiting the HALT mode is with the Multi-Input Wakeup feature on the L port. The second method is with a low to high transition on the CKO (G7) pin. This method precludes the use of the crystal clock configura­tion (since CKO becomes a dedicated output), and so may be used with an RC clock configuration. The third method of exiting the HALT mode is by pulling the RESET pin low.
Since a crystal or ceramic resonator may be selected as the oscillator, the Wakeup signal is not allowed to start the chip running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full ampli­tude and frequency stability. The IDLE timer is used to gen­erate a fixed delay to ensure that the oscillator has indeed stabilized before allowing instruction execution. In this case, upon detecting a valid Wakeup signal, only the oscillator cir­cuitry is enabled. The IDLE timer is loaded with a value of 256 and is clocked with the t
c
instruction cycle clock. The t
c
clock is derived by dividing the oscillator clock down by a fac­tor of 10. The Schmitt trigger following the CKI inverter on the chip ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specifications. This Schmitt trigger is not part of the oscillator closed loop. The startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip.
If an RC clock option is being used, the fixed delay is intro­duced optionally. A control bit, CLKDLY,mapped as configu­ration bit G7, controls whether the delay is to be introduced or not. The delay is included if CLKDLY is set, and excluded if CLKDLY is reset. The CLKDLY bit is cleared on reset.
The device has two mask options associated with the HALT mode. The first mask option enables the HALTmode feature, while the second mask option disables the HALT mode. With the HALT mode enable mask option, the device will enter and exit the HALT mode as describedabove. With the HALT disable mask option, the device cannot be placed in the HALT mode (writing a “1” to the HALT flag will have no ef­fect).
The WATCHDOG detector circuit is inhibited during the HALTmode. However, the clock monitor circuit if enabled re­mains active during HALT mode in order to ensure a clock monitor error if the device inadvertently enters the HALT mode as a result of a runaway program or power glitch.
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Power Save Modes (Continued)
IDLE MODE
The device is placed in theIDLE modeby writinga “1” to the IDLE flag (G6 data bit). In this mode, all activity, except the associated on-board oscillator circuitry, the WATCHDOG logic, the clock monitor and the IDLE Timer T0, is stopped.
As with the HALT mode, the device can be returned to nor­mal operation with a reset, or with a Multi-Input Wakeup from the L Port. Alternately, the microcontroller resumes normal operation from the IDLE mode when the thirteenth bit (repre­senting 4.096 ms at internal clock frequency of 1 MHz, t
c
=
1 µs) of the IDLE Timer toggles.
This toggle condition of the thirteenth bit of the IDLE Timer T0 is latched into the T0PND pending flag.
The user has the option of being interrupted with atransition on the thirteenth bit of the IDLE Timer T0. The interrupt can be enabled or disabled via the T0EN control bit. Setting the T0EN flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer T0 inter­rupt enabled. In this case, when the T0PND bit gets set, the device will first execute the Timer T0 interrupt serviceroutine and then return to the instruction following the “Enter Idle Mode” instruction.
Note: It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions are necessary to allow clock resynchronization following the HALT or IDLE modes.
Multi-Input Wakeup
The Multi-Input Wakeup feature is used to return (wakeup) the device from either the HALT or IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature may also be used to generate up to 8 edge selectable external interrupts.
Figure 11
shows the Multi-Input Wakeup logic.
The Multi-Input Wakeupfeature utilizes the L Port. The user selects which particular L port bit (or combination of L Port bits) will cause the device to exit the HALT or IDLE modes. The selection is done through the Reg: WKEN. The Reg: WKEN is an 8-bit read/write register, which contains a con­trol bit for every L port bit. Setting a particular WKEN bit en­ables a Wakeup from the associated L port pin.
negative edge on that particular L Port pin. Resetting the bit selects the trigger condition to be a positive edge. Changing an edge select entails several steps in order to avoid a pseudo Wakeup condition as a result of the edge change. First, the associated WKEN bit should be reset, followed by the edge select change in WKEDG. Next, the associated WKPND bit should be cleared, followed by the associated WKEN bit being re-enabled.
An example may serve to clarify this procedure. Suppose we wish to change the edge select from positive (low going high) to negative (high going low) for L Port bit 5, where bit 5 has previously been enabled for an input interrupt. The program would be as follows:
RBIT 5, WKEN ; Disable MIWU SBIT 5, WKEDG ; Change edge polarity RBIT 5, WKPND ; Reset pending flag SBIT 5, WKEN ; Enable MIWU
If the L port bits have been used as outputs and then changed to inputs with Multi-Input Wakeup/Interrupt, a safety procedure should also be followed to avoid inherited pseudo wakeup conditions. After the selected L port bits have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired edge selects, followed by the associated WKPND bits being cleared.
This same procedure should be used following reset, since the L port inputs are left floating as a result of reset.
The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a pending register called WKPND. The respective bits of the WKPND register will be set on the occurrence of the selected trigger edge on the cor­responding Port L pin. The user has the responsibility of clearing these pending flags. Since WKPND is a pending register for the occurrence of selected wakeup conditions, the device will not enter the HALT mode if any Wakeup bit is both enabled and pending. Consequently, the user has the responsibility of clearing the pending flags before attempting to enter the HALT mode.
The WKEN, WKPND and WKEDG are all read/write regis­ters, and are cleared at reset.
PORT L INTERRUPTS
Port L provides the user with an additional eight fully select­able, edge sensitive interrupts which are all vectored into the same service subroutine.
The interrupt from Port L shares logic with the wake up cir­cuitry.The register WKENallows interruptsfrom Port L to be individually enabled or disabled. The register WKEDG speci­fies the trigger condition to be either a positive or a negative edge. Finally, the register WKPND latches in the pending trigger conditions.
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Multi-Input Wakeup (Continued)
Since Port L is also used for waking the device out of the HALTor IDLE modes, the user can elect to exit the HALT or IDLE modes either with or without the interrupt enabled. If he elects to disable the interrupt, then the device will restart ex­ecution from the instruction immediately following the in­struction that placed themicrocontroller in the HALTor IDLE modes. In the other case, the device will first execute the in­terrupt service routine and then revert to normal operation.
The Wakeup signal will not start the chip running immedi­ately since crystal oscillators or ceramic resonators have a fi­nite start up time. The IDLE Timer (T0) generatesa fixedde­lay to ensure that the oscillator has indeed stabilized before allowing the device to execute instructions. In this case, upon detecting a valid Wakeup signal, only the oscillator cir­cuitry and the IDLE Timer T0 are enabled. The IDLE Timer is loaded with a value of256 andis clockedfrom the t
c
instruc-
tion cycle clock. The t
c
clock is derived by dividing down the oscillator clock by a factor of 10. A Schmitt trigger following the CKI on-chip inverter ensures that the IDLE timer is clocked only when the oscillator has a sufficiently large am­plitude to meet the Schmitt trigger specifications. This Schmitt trigger is not part of the oscillator closed loop. The startup timeout from the IDLE timer enables the clock signals to be routed to the rest of the chip.
If the RC clock option is used, the fixed delay is under soft­ware control. A control flag, CLKDLY, in the G7 configuration bit allows the clock start up delay to be optionally inserted. Setting CLKDLY flag high will cause clock start up delay to be inserted and resetting it willexclude the clockstart upde­lay. The CLKDLY flag is cleared during reset, so the clock start up delay is not present following reset with the RC clock options.
A/D Converter
The device contains an 8-channel, multiplexed input, suc­cessive approximation, A/D converter. Two dedicated pins, V
REF
and AGND are provided for voltage reference.
OPERATING MODES
The A/D converter supports ratiometric measurements. It supports both Single Ended and Differential modes of opera­tion.
Four specific analog channel selection modes are sup­ported. These are as follows:
Allow any specific channel to be selected at one time. The A/D converter performs the specific conversion requested and stops.
Allow any specific channel to be scanned continuously. In other words, the user will specify the channel and the A/D converter will keep on scanning it continuously.The user can come in at any arbitrary time and immediately read the result of the last conversion. The user does nothave to waitfor the current conversion to be completed.
Allow any differential channel pair to be selected at one time. The A/D converter performs the specific differential conver­sion requested and stops.
Allow any differential channel pair to be scanned continu­ously. In other words, the user will specify the differential channel pair and the A/D converter will keep on scanning it continuously.The user cancome in at any arbitrary time and immediately read the result of the last differentialconversion. The user does not have to wait for the current conversion to be completed.
TheA/D converter issupported by two memory mappedreg­isters, the result register and the mode control register. When the device is reset, the control register is cleared and the A/D is powered down. The A/D result register has un­known data following reset.
DS101134-16
FIGURE 11. Multi-Input Wake Up Logic
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A/D Converter (Continued)
A/D Control Register
Acontrol register, Reg: ENAD, contains 3 bits for channel se­lection, 3 bits for prescalerselection, and2 bitsfor mode se­lection. An A/D conversion isinitiated bywriting to the ENAD control register. The result of the conversion is available to the user from the A/D result register, Reg: ADRSLT.
Reg: ENAD
CHANNEL
SELECT
MODE
SELECT
PRESCALER
SELECT
Bits 7, 6, 5 Bits 4,3 Bits 2, 1, 0
CHANNEL SELECT
This 3-bit field selects one of eight channels to be the V
IN+
.
The mode selection determines the V
IN−
input.
Single Ended mode:
Bit 7 Bit 6 Bit 5 Channel No.
000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
Differential mode:
Bit 7 Bit 6 Bit 5 Channel Pairs (+. −)
000 0,1 001 1,0 010 2,3 011 3,2 100 4,5 101 5,4 110 6,7 111 7,6
MODE SELECT
This 2-bit field is used to select the mode of operation (single conversion, continuous conversions, differential, single ended) as shown in the following table.
Bit 4 Bit 3 Mode
0 0 Single Ended mode, single conversion 0 1 Single Ended mode, continuous scan
of a single channel into the result
register 1 0 Differential mode, single conversion 1 1 Differential mode, continuous scan of
a channel pair into the result register
PRESCALER SELECT
This 3-bit field is used to select one of the seven prescaler clocks for the A/D converter. The prescaler also allows the A/D clock inhibit power saving mode to be selected. The fol­lowing table shows the various prescaler options.
Bit 2 Bit 1 Bit 0 Clock Select
0 0 0 Inhibit A/D clock 0 0 1 Divide by 1 0 1 0 Divide by 2 0 1 1 Divide by 4 1 0 0 Divide by 6 1 0 1 Divide by 12 1 1 0 Divide by 8 1 1 1 Divide by 16
ADC Operation
The A/D converter interface works as follows. Writing to the A/D control register ENAD initiates anA/D conversion unless the prescaler value is set to 0, in which case the ADC clock is stopped and the ADC is powered down. The conversion sequence starts at the beginning of the write to ENAD opera­tion powering up the ADC. At the first falling edge ofthe con­verter clock following the write operation (not counting the falling edge if it occurs at the same time as the write opera­tion ends), the sample signal turns on for two clock cycles. TheADC is selected in the middle of thesample period. If the ADC is in single conversion mode, the conversion complete signal from theADC will generate a power down for the A/D converter. If the ADC is in continuous mode, the conversion complete signal will restart the conversion sequence by de­selecting the ADC for one converter clock cycle before start­ing the next sample. The ADC 8-bit result is loaded into the A/D result register (ADRSLT) except during LOAD clock high, which prevents transient data (resulting from the ADC writing a new result over an old one) being read from ADRSLT.
Inadvertant changes to the ENAD registerduring conversion are prevented by the control logic of the A/D. Any attempt to write any bit of the ENAD Register except ADBSY, while ADBSY is a one, is ignored. ADBSY must be cleared either by completion of an A/D conversion or by the user before the prescaler, conversion mode or channel select values can be changed.After stopping thecurrent conversion, theuser can load different values for the prescaler, conversion mode or channel select and start a new conversionin one instruction.
It is important for the user to realize that, when used indiffer­ential mode, only the positive input to the A/D converter is sampled and held. The negative input is constantly con­nected and should be heldstable forthe durationof thecon­version. Failure to maintain a stable negative input will result in incorrect conversion.
PRESCALER The A/D Converter (ADC) contains a prescaler option which
The A/D converter takes 12 ADC clock cycles to complete a conversion. Thus the minimum ADC conversion time for the device is 7.2 µs when a prescaler of 6 has been selected. These 12 ADC clock cycles necessary for a conversion con-
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A/D Converter (Continued)
sist of 1 cycle at the beginning for reset, 2 cycles for sam­pling, 8 cycles for converting, and 1 cycle for loading the re­sult into the A/D result register (ADRSLT). This A/D result register is a read-only register. The device cannot write into ADRSLT.
The prescaler also allows an A/D clock inhibit option, which saves power by powering down the A/D when it is not in use.
Note: The A/D converter is also powered down when the device is in either
the HALT or IDLE modes. If theADC is running when the device enters the HALT or IDLE modes, the ADC will power down during the HALTor IDLE, and then will reinitialize the conversion when the device comes out of the HALT or IDLE modes.
Analog Input and Source Resistance Considerations
Figure 12
shows the A/D pin model in single ended mode. The differential mode has similiar A/D pin model. The leads to the analog inputs should be kept as short as possible. Both noise and digital clock coupling to an A/D input can cause conversion errors. The clock lead should be kept away from the analog input line to reduce coupling. The A/D channel input pins do not have any internal output driver cir­cuitry connected to them because this circuitry would load the analog input signals due to output buffer leakage current.
Source impedances greater than 1 kΩ on the analog input lines will adverselyaffect internal RC charging time during in­put sampling. As shown in
Figure 12
, the analog switch to the DAC array is closed only during the 2 A/D cycle sample time. Large source impedances on the analog inputs may re­sult in the DAC array not being charged to the correct volt­age levels, causing scale errors.
If large source resistance is necessary, the recommended solution is to slow down theA/D clock speed in proportion to the source resistance. The A/D converter may be operated at the maximum speed for R
S
less than 1 kΩ. For RSgreater than 1 kΩ, A/D clock speed needs to be reduced. For ex­ample, with R
S
=
2kΩ, the A/D converter may be operated at half the maximum speed. A/D converter clock speed may be slowed down by either increasing the A/D prescaler divide-by or decreasing the CKI clock frequency. The A/D clock speed may be reduced to its minimum frequency of 100 kHz.
Interrupts
INTRODUCTION
Each device supports nine vectored interrupts. Interrupt sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L Wakeup, Software Trap, MICROWIRE/PLUS, and External Input.
All interrupts force a branch to location 00FF Hexin program memory. The VIS instruction may be used to vector to the appropriate service routine from location 00FF Hex.
The Software trap has the highest priority while the default VIS has the lowest priority.
Each of the 9 maskable inputs has a fixedarbitration ranking and vector.
Figure 13
shows the Interrupt Block Diagram.
DS101134-28
*The analog switch is closed only during the sample time.
FIGURE 12. A/D Pin Model (Single Ended Mode)
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Interrupts (Continued)
MASKABLE INTERRUPTS
All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit.The pending bit is set to 1 when the interrupt condition occurs. The state of the interrupt enable bit, com­bined with the GIE bit determines whether an active pending flag actually triggers an interrupt. All of the maskable inter­rupt pending and enable bits are contained in mapped con­trol registers, and thus can be controlled by the software.
Amaskable interrupt condition triggers an interrupt under the following conditions:
1. The enable bit associated with that interrupt is set.
2. The GIE bit is set.
3. The device is not processing a non-maskable interrupt. (If a non-maskable interrupt is being serviced, a maskable interrupt must wait until that service routine is completed.)
An interrupt is triggered only when all of theseconditions are met at the beginning of an instruction. If different maskable interrupts meet these conditions simultaneously, the highest priority interrupt will be serviced first, and the other pending interrupts must wait.
Upon Reset, all pending bits, individual enable bits, and the GIE bit are reset to zero. Thus, a maskable interrupt condi­tion cannot trigger an interrupt until the program enables it by setting both the GIE bit and the individual enable bit. When enabling an interrupt, the user should consider whether or not a previously activated (set) pending bit should be ac­knowledged. If, at the time an interrupt is enabled, any pre­vious occurrences of the interrupt should be ignored, the as­sociated pending bit must be reset to zero prior to enabling the interrupt. Otherwise, the interrupt may be simply en­abled; if the pending bit is already set, it will immediatelytrig­ger an interrupt. A maskable interrupt is active if its associ­ated enable and pending bits are set.
edged until the start of the next normally executed instruction is to be skipped, the skip is performedbefore the pendingin­terrupt is acknowledged.
At the start of interrupt acknowledgment, the following ac­tions occur:
1. The GIE bit is automatically reset to zero, preventing any subsequent maskable interrupt from interrupting the cur­rent service routine. This feature prevents one maskable interrupt from interrupting another one being serviced.
2. The address of the instruction about to be executed is pushed onto the stack.
3. The program counter (PC) is loaded with 00FF Hex, causing a jump to that program memory location.
The device requires seven instruction cycles to perform the actions listed above.
If the user wishes to allow nested interrupts, the interrupts service routine may set the GIE bit to 1 by writing to the PSW register,and thus allow other maskable interrupts to interrupt the current service routine. If nested interrupts are allowed, caution must be exercised. The user must write the program in such a way as to prevent stack overflow, loss of saved context information, and other unwanted conditions.
Within a specific interrupt service routine, the associated pending bit should be cleared. This is typically done as early as possible in the service routine in order to avoid missing the next occurrence of the same type of interrupt event. Thus, if the same event occurs a second time, even while the first occurrence is still being serviced, the second occur­rence will be serviced immediately upon return from the cur­rent interrupt routine.
An interrupt service routine typically ends with an RETI in­struction. This instruction sets the GIE bit back to 1, pops the
DS101134-18
FIGURE 13. Interrupt Block Diagram
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Interrupts (Continued)
address stored on the stack, and restores that address to the program counter. Program execution then proceeds with the next instruction that would have been executed had there been no interrupt. If there are any valid interrupts pending, the highest-priority interrupt is serviced immediately upon re­turn from the previous interrupt.
VIS INSTRUCTION
The general interrupt service routine, which starts at address 00FF Hex, must be capable of handling all types of inter­rupts. The VIS instruction, together with an interrupt vector table, directs the device to the specific interrupt handling rou­tine based on the cause of the interrupt.
VIS is a single-byte instruction, typically used at the verybe­ginning of the general interrupt service routine at address 00FF Hex, or shortly afterthat point,just afterthe codeused for context switching. The VIS instruction determines which enabled and pending interrupt has the highest priority, and causes an indirect jump to the address corresponding to that interrupt source. The jump addresses (vectors) for all pos­sible interrupts sources are stored in a vector table.
The vector table may be as long as 32 bytes (maximum of 16 vectors) and resides at the top of the 256-byte block contain­ing the VIS instruction. However, if the VIS instruction is at the very top of a 256-byte block (such as at 00FF Hex), the vector table resides at the top of the next 256-byte block. Thus, if the VIS instruction is located somewhere between 00FF and 01DF Hex (the usual case), the vector table is lo­cated between addresses 01E0 and 01FF Hex. If the VIS in­struction is located between 01FF and 02DF Hex, then the vector table is located between addresses 02E0 and 02FF Hex, and so on.
Each vector is 15 bits long and points to the beginning of a specific interrupt service routine somewhere in the 32 kbyte memory space. Each vector occupies two bytes of the vector table, with the higher-order byte at the lower address. The vectors are arranged in order of interrupt priority. The vector of the maskable interrupt with the lowest rank is located to 0yE0 (higher-order byte) and 0yE1 (lower-order byte). The next priority interrupt is located at 0yE2 and 0yE3, and so forth in increasing rank. The Software Trap has the highest rank and its vector is always located at 0yFE and 0yFF. The number of interrupts which can become active defines the size of the table.
Table3
shows the types of interrupts, the interrupt arbitration ranking, and the locations of the corresponding vectors in the vector table.
The vector table should be filled by the user with the memory locations of the specific interrupt service routines. For ex­ample, if the Software Trap routine is located at 0310 Hex, then the vector location 0yFE and -0yFF should contain the data 03 and 10 Hex, respectively. When a Software Trap in­terrupt occurs and the VIS instruction is executed, the pro­gram jumps to the address specified in the vector table.
The interrupt sources in the vectortable are listedin orderof rank, from highest to lowest priority. If two or more enabled and pending interrupts are detected at the same time, the one with the highest priority is serviced first. Upon return from the interrupt service routine, the next highest-level pending interrupt is serviced.
If the VIS instruction is executed, but no interrupts are en­abled and pending, the lowest-priority interrupt vector is used, and a jump is made to the corresponding address in the vector table. This is an unusual occurrence, and may be the result of an error. It can legitimately result from a change in the enable bits or pending flags prior to the execution of the VIS instruction, such as executing a single cycle instruc­tion which clears an enable flag at the same time that the pending flag is set. It can also result, however,from inadvert­ent execution of the VIS command outside of the context of an interrupt.
This technique can save up to fifty instruction cycles (t
c
), or more, (50µs at 10 MHz oscillator) of latency for pending in­terrupts with a penalty of fewer than ten instruction cycles if no further interrupts are pending.
To ensure reliable operation, the user should always use the VIS instruction to determine the source of an interrupt. Al­though it is possible to poll the pending bits to detect the source of an interrupt, this practice is not recommended. The use of polling allows the standard arbitration ranking to be al­tered, but the reliability of the interrupt system is compro­mised. The polling routine must individually test the enable and pending bits of each maskable interrupt. If a Software Trap interrupt should occur, it will be serviced last, even though it should have thehighest priority. Under certain con­ditions, a Software Trap could be triggered but not serviced, resulting in an inadvertent “locking out” of all maskable inter­rupts by the Software Trap pending flag. Problems such as this can be avoided by using VIS instruction.
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Interrupts (Continued)
TABLE 3. Interrupt Vector Table
Arbitration
Source Description
Vector Address
Ranking Hi-Low Byte
(1) Highest Software INTR Instruction 0yFE–0yFF
Reserved for Future Use 0yFC–0yFD (2) External Pin G0 Edge 0yFA–0yFB (3) Timer T0 Underflow 0yF8–0yF9 (4) Timer T1 T1A/Underflow 0yF6–0yF7 (5) Timer T1 T1B 0yF4–0yF5 (6) MICROWIRE/PLUS BUSY Goes Low 0yF2–0yF3
Reserved for Future Use 0yF0–0yF1
Reserved for UART 0yEE–0yEF
Reserved for UART 0yEC–0yED (7) Timer T2 T2A/Underflow 0yEA–0yEB (8) Timer T2 T2B 0yE8–0yE9
Reserved for Future Use 0yE6–0yE7
Reserved for Future Use 0yE4–0yE5 (9) Port L/Wakeup Port L Edge 0yE2–0yE3 (10) Lowest Default VIS Instr. Execution without
Any Interrupts
0yE0–0yE1
Note 11: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last ad­dress of a block. In this case, the table must be in the next block.
VIS Execution
When the VIS instruction is executed it activates the arbitra­tion logic. The arbitration logic generates an even number between E0 and FE (E0, E2, E4, E6 etc...) depending on which active interrupt has the highest arbitration ranking at the time of the 1st cycle of VIS is executed. For example, if the software trap interrupt is active, FE is generated. If the external interrupt is active and the software trap interrupt is not, then FAis generated and so forth. If the only active inter­rupt is software trap, than E0 is generated. This number re­places the lower byte of the PC. The upper byte of the PC re­mains unchanged. The new PC is therefore pointing to the
vector of the active interrupt with the highest arbitration rank­ing. This vector is read from program memory and placed into the PC which is now pointed to the 1st instruction of the service routine of the active interrupt with the highest arbitra­tion ranking.
Figure 14
illustrates the different steps performed by the VIS
instruction.
Figure 15
shows a flowchart for the VIS instruc-
tion. The non-maskable interrupt pending flag is cleared by the
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Interrupts (Continued)
DS101134-29
FIGURE 14. VIS Operation
DS101134-30
FIGURE 15. VIS Flowchart
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Interrupts (Continued)
Programming Example: External Interrupt
PSW =00EF CNTRL =00EE RBIT 0,PORTGC RBIT 0,PORTGD ; G0 pin configured Hi-Z SBIT IEDG, CNTRL ; Ext interrupt polarity; falling edge SBIT EXEN, PSW ; Enable the external interrupt SBIT GIE, PSW ; Set the GIE bit
WAIT: JP WAIT ; Wait for external interrupt
. . . .=0FF ; The interrupt causes a VIS ; branch to address 0FF
; The VIS causes a branch to
;interrupt vector table . . . .=01FA ; Vector table (within 256 byte .ADDRW SERVICE ; of VIS inst.) containing the ext
; interrupt service routine . .
INT_EXIT:
RETI . .
SERVICE: RBIT EXPND, PSW ; Interrupt Service Routine
; Reset ext interrupt pend. bit . . . JP INT_EXIT ; Return, set the GIE bit
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Interrupts (Continued)
NON-MASKABLE INTERRUPT
Pending Flag
There is a pending flag bit associated with the non-maskable interrupt, called STPND. This pending flag is not memory­mapped and cannot be accessed directly by the software.
The pending flag is reset to zero when a device Reset oc­curs. When the non-maskable interrupt occurs, the associ­ated pending bit is set to 1. The interrupt service routine should contain an RPND instruction to reset the pending flag to zero. The RPND instruction always resets the STPND flag.
Software Trap
The Software Trap is a special kind of non-maskable inter­rupt which occurs when the INTR instruction (used to ac­knowledge interrupts) is fetched from program memory and placed in the instruction register. This can happen in a vari­ety of ways, usually because of anerror condition.Some ex­amples of causes are listed below.
If the program counter incorrectly points to a memory loca­tion beyond the available program memory space, the non­existent or unused memory location returns zeroes which is interpreted as the INTR instruction.
If the stack is popped beyond the allowed limit (address 06F Hex), a 7FFF will be loaded into the PC, if this last location in program memory is unprogrammed or unavailable, a Soft­ware Trap will be triggered.
A Software Trap can be triggered by a temporary hardware condition such as a brownout or power supply glitch.
The Software Trap has the highest priority of all interrupts. When a Software Trap occurs, the STPND bit is set. The GIE bit is not affected and the pending bit (not accessible by the user) is used to inhibit other interrupts and to direct the pro­gram to the ST service routine with the VIS instruction. Noth­ing can interrupt a Software Trap service routine except for another Software Trap. The STPND can be reset only bythe RPND instruction or a chip Reset.
The Software Trap indicates an unusual or unknown error condition. Generally, returning to normal execution at the point where the Software Trap occurred cannot be done re­liably. Therefore, the Software Trap service routine should reinitialize the stack pointer and perform a recovery proce­dure that restarts the software at some known point, similar to a device Reset, but not necessarily performing all the same functions as a device Reset. The routine mustalso ex­ecute the RPND instruction to reset the STPND flag. Other­wise, all other interrupts will be locked out. To the extent pos­sible, the interrupt routine should record or indicate the context of the device so that the cause of the Software Trap can be determined.
If the user wishes to return to normal execution from the point at which the Software Trap was triggered, the user must first execute RPND, followed by RETSK rather than RETI or RET. This is because the return address stored on the stack is the address of the INTR instruction that triggered the interrupt. The program must skip that instruction in order to proceed with the next one. Otherwise, an infinite loop of Software Traps and returns will occur.
Programming a return to normal execution requires careful consideration. If the Software Trap routine is interrupted by another Software Trap, the RPND instruction in the service routine for the second Software Trap will reset the STPND
flag; upon return to the first Software Trap routine, the STPND flag will have the wrong state. This will allow maskable interrupts to be acknowledged during the servicing of the first Software Trap. To avoid problems such as this, the user program should contain the Software Trap routine to perform a recovery procedure rather than a return to normal execution.
Under normal conditions, the STPND flag is reset by a RPND instruction in the Software Trap service routine. If a programming error or hardware condition (brownout, power supply glitch, etc.) sets the STPND flag without providing a way for it to be cleared, allother interrupts willbe locked out. To alleviate this condition, the user can use extra RPND in­structions in the main program and in the WATCHDOG ser­vice routine (if present). There is no harm in executing extra RPND instructions in these parts of the program.
PORT L INTERRUPTS
Port L provides the user with an additional eight fully select­able, edge sensitive interrupts which are all vectored into the same service subroutine.
The interrupt from Port L shares logic with the wake up cir­cuitry.The register WKENallows interruptsfrom Port L to be individually enabled or disabled. The register WKEDG speci­fies the trigger condition to be either a positive or a negative edge. Finally, the register WKPND latches in the pending trigger conditions.
The GIE (Global Interrupt Enable) bit enables the interrupt function.
A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will enable inter­rupts and vice versa. A separate global pending flag is not needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the HALTor IDLE modes, the user can elect to exit the HALT or IDLE modes either with or without the interrupt enabled. If he elects to disable the interrupt, then the device will restart ex­ecution from the instruction immediately following the in­struction that placed themicrocontroller in the HALTor IDLE modes. In the other case, the device will first execute the in­terrupt service routine and then revert to normal operation. (See HALT MODE for clock option wakeup information.)
INTERRUPT SUMMARY
2. Maskable interrupts, triggered by an on-chip peripheral block or an external device connected tothe device. Un­der ordinary conditions, a maskable interrupt will not in­terrupt any other interrupt routine in progress. A maskable interrupt routine in progress can be inter­rupted by the non-maskable interrupt request. A maskable interrupt routine should end with an RETI in­struction or, prior to restoring context, should return to execute the VIS instruction. This is particularly useful when exiting long interrupt service routiness if the time between interrupts is short. In this case the RETI instruc­tion would only be executed when the default VIS rou­tine is reached.
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WATCHDOG
The device contains a WATCHDOG and clock monitor. The WATCHDOG is designed to detect the user program getting stuck in infinite loops resulting in loss of program control or “runaway” programs. The Clock Monitor is used to detect the absence of a clock or a very slow clock below a specified rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks: WD UPPER and WD LOWER. WD UPPER establishes the upper limit on the service window and WD LOWER defines the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named WDSVR which is memory mapped in the RAM. This value is com­posed of three fields, consisting of a 2-bit Window Select, a 5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table 4
shows the WDSVR register.
TABLE 4. WATCHDOG Service Register (WDSVR)
Window
Select
Key Data
Clock
Monitor
XX01100 Y 7654321 0
The lower limit of the service window is fixed at 2048instruc­tion cycles. Bits 7 and 6 of the WDSVR register allow the user to pick an upper limit of the service window.
Table 5
shows the four possible combinations of lower and upper limits for the WATCHDOG service window. This flex­ibility in choosing the WATCHDOG service window prevents any undue burden on the user software.
TABLE 5. WATCHDOG Service Window Select
WDSVR WDSVR Clock Service Window
Bit 7 Bit 6 Monitor (Lower-Upper Limits)
0 0 x 2048–8k t
C
Cycles
0 1 x 2048–16k t
C
Cycles
1 0 x 2048–32k t
C
Cycles
1 1 x 2048–64k t
C
Cycles x x 0 Clock Monitor Disabled x x 1 Clock Monitor Enabled
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5-bit Key Data field. The key data is fixed at 01100. Bit 0 of the WDSVR Register is the Clock Monitor Select bit.
Clock Monitor
The Clock Monitor aboard the device can be selected or de­selected under program control. The Clock Monitor is guar­anteed not to reject the clock if the instruction cycleclock (1/ t
c
) is greater or equal to 10 kHz.This equates to a clock input
rate on CKI of greater or equal to 100 kHz.
WATCHDOG Operation
The WATCHDOG and Clock Monitor are disabled during re­set. The device comes out of reset with the WATCHDOG armed, the WATCHDOG Window Select (bits 6, 7 of the WDSVR Register) set, and the Clock Monitor bit (bit 0 of the WDSVR Register) enabled. Thus, a Clock Monitor error will occur after coming out of reset, if the instruction cycle clock frequency has not reached a minimum specified value, in­cluding the case where the oscillator fails to start.
The WDSVR register can be written to only once after reset and the key data (bits 5 through 1 of the WDSVR Register) must match to be a valid write. This write to the WDSVR reg­ister involves two irrevocable choices: (i) the selection of the WATCHDOG service window (ii) enabling or disabling of the Clock Monitor. Hence, the first write to WDSVR Register in­volves selecting or deselecting the Clock Monitor, select the WATCHDOG service window and match the WATCHDOG key data. Subsequent writes to the WDSVR register will compare the value being written by the user to the WATCH­DOG service window value and the key data (bits 7 through
1) in the WDSVR Register.
Table 6
shows the sequence of
events that can occur. The user must service the WATCHDOGat leastonce before
the upper limit of the service window expires. The WATCH­DOG may not be serviced more than once in every lower limit of the service window. The user may service the WATCHDOG as many times as wished in the time period be­tween the lower and upper limits of the service window.The first write to the WDSVR Register is also counted as a WATCHDOG service.
The WATCHDOG has an output pin associated with it. This is the WDOUT pin, on pin 1 of the port G. WDOUT is active low.The WDOUT pin is in the high impedance state in the in­active state. Upon triggering the WATCHDOG, the logic will pull the WDOUT (G1) pin low for an additional 16 t
c
–32 t
c
cycles after the signal level on WDOUT pin goes below the lower Schmitt trigger threshold. After this delay, the device will stop forcing the WDOUT output low.
The WATCHDOG service window will restart when the WD­OUT pin goes high. It is recommended that the user tie the WDOUT pin back to V
CC
through a resistor in order to pull
WDOUT high. AWATCHDOGservice while the WDOUT signal is active will
c
–32 tcclock cycles. The Clock Monitor generates a continual Clock Monitorerror if the oscillator fails to start, or fails to reach the minimum specified frequency. The specification for the Clock Monitor is as follows:
1/t
c
>
10 kHz —No clock rejection.
1/t
c
<
10 Hz —Guaranteed clock rejection.
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WATCHDOG Operation (Continued)
TABLE 6. WATCHDOG Service Actions
Key Window Clock Action
Data Data Monitor
Match Match Match Valid Service: Restart Service Window
Don’t Care Mismatch Don’t Care Error: Generate WATCHDOG Output
Mismatch Don’t Care Don’t Care Error: Generate WATCHDOG Output
Don’t Care Don’t Care Mismatch Error: Generate WATCHDOG Output
WATCHDOG AND CLOCK MONITOR SUMMARY
The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted:
•
Both the WATCHDOG and Clock Monitor detector circuits are inhibited during RESET.
•
Following RESET, the WATCHDOG and CLOCK MONI­TOR are both enabled, with the WATCHDOG having the maximum service window selected.
•
The WATCHDOG service window and Clock Monitor enable/disable option can only be changed once, during the initial WATCHDOG service following RESET.
•
The initial WATCHDOG service must match the key data value in the WATCHDOG Service register WDSVR in or­der to avoid a WATCHDOG error.
•
Subsequent WATCHDOG services must match all three data fields in WDSVR in order to avoid WATCHDOG er­rors.
•
The correct key data value cannot be read from the WATCHDOG Service register WDSVR. Any attempt to read this key data value of 01100 from WDSVR will read as key data value of all 0’s.
•
The WATCHDOG detector circuit is inhibited during both the HALT and IDLE modes.
•
The Clock Monitor detector circuit is active during both the HALT and IDLE modes. Consequently, the device in­advertently entering the HALT mode will be detectedas a Clock Monitor error (provided that the Clock Monitor en­able option has been selected by the program).
•
With the single-pin R/C oscillator mask option selected and the CLKDLY bit reset, the WATCHDOG service win­dow will resume following HALT mode from where it left off before entering the HALT mode.
•
With the crystal oscillator mask option selected, or with the single-pin R/C oscillator mask option selected and the CLKDLY bit set, the WATCHDOG service window will be set to its selected value from WDSVR following HALT. Consequently, the WATCHDOG should not be serviced for at least 2048 instruction cycles following HALT, but must be serviced within the selected window to avoid a WATCHDOG error.
•
The IDLE timer T0 is not initialized with RESET.
•
The user can sync in to the IDLE counter cycle with an IDLE counter (T0) interrupt or by monitoring the T0PND flag. The T0PND flag is set whenever the thirteenth bit of the IDLE counter toggles (every 4096 instruction cycles). The user is responsible for resetting the T0PND flag.
•
A hardware WATCHDOG service occurs just as the de­vice exits the IDLE mode. Consequently, the WATCH­DOG should not be serviced for at least 2048 instruction cycles following IDLE, but must be servicedwithin these­lected window to avoid a WATCHDOG error.
•
Following RESET, the initial WATCHDOG service (where the service window and the CLOCK MONITOR enable/ disable must be selected) may be programmed anywhere within the maximum service window (65,536 instruction cycles) initialized by RESET. Note that this initial WATCH­DOG service may be programmed within the initial 2048 instruction cycles without causing a WATCHDOG error.
Detection of Illegal Conditions
Reading of undefined ROM gets zeros. The opcode for soft­ware interrupt is zero. If the program fetches instructions from undefined ROM, this will force a software interrupt, thus signaling that an illegal condition has occurred.
The subroutine stack grows downfor eachcall (jumpto sub­routine), interrupt, or PUSH, and grows up for each returnor POP. The stack pointer is initialized to RAM location 06F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will point to addresses 070 and 071 Hex (which are undefined RAM). Undefined RAM from ad­dresses 070 to 07F Hex is read as all 1’s, which in turn will cause the program to return to address 7FFF Hex. This isan undefined ROM location and the instruction fetched (all 0’s) from this location will generate a software interrupt signaling an illegal condition.
Thus, the chip can detect the following illegal conditions:
1. Executing from undefined ROM
2. Over “POP”ing the stack by having more returns than calls.
When the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery procedure before restart­ing (this recovery program is probably similar to that follow­ing reset, but might not contain the same program initializa­tion procedures).
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous communications interface. The MICROWIRE/PLUS capability enables the de­vice to interface with any of National Semiconductor’s MI­CROWIRE peripherals (i.e. A/D converters, display drivers, E
2
PROMs etc.) and with other microcontrollers which sup­port the MICROWIRE interface. It consists of an 8-bit serial shift register (SIO) with serial data input (SI), serial data out­put (SO) and serial shiftclock (SK).
Figure 16
shows a block
diagram of the MICROWIRE/PLUS logic.
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MICROWIRE/PLUS (Continued)
The CNTRL register is used to configure and control the MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS, the MSEL bit in the CNTRL register is set to one. In themas­ter mode the SK clock rate is selected by the two bits, SL0 and SL1, in the CNTRL register.
Table7
details the different
clock rates that may be selected.
TABLE 7. MICROWIRE/PLUS
Master Mode Clock Selection
SL1 SL0 SK
0 0 2xt
c
0 1 4xt
c
1 x 8xt
c
Where tcis the instruction cycle clock
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software to allow less than 8 bits to shift. If enabled, an interrupt is generated when eight data bits have been shifted. The device may enter the MICROWIRE/PLUS mode either as a Master or as a Slave.
Figure 17
shows how two COP888CF microcontrollers and several peripherals may be interconnected using the MICROWIRE/PLUS ar­rangements.
Warning:
The SIO register should only be loaded when the SK clockis low. Loading the SIO register while the SK clock is high will result in undefined data in the SIO register. SK clock is nor­mally low when not shifting.
Setting the BUSY flag when the input SK clock is high in the MICROWIRE/PLUS slave mode may cause the current SK clock for the SIO shift register to be narrow. For safety, the BUSY flag should only be set when the input SK clock is low.
MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the shift clock (SK) is generated internally. The MICROWIRE Master always initiates all data exchanges. The MSEL bit in the CNTRL register must be set to enable the SO and SK functions onto the G Port.The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration register.
Table 8
summarizes the bit settings
required for Master mode of operation.
DS101134-20
FIGURE 16. MICROWIRE/PLUS Block Diagram
DS101134-21
FIGURE 17. MICROWIRE/PLUS Application
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MICROWIRE/PLUS (Continued)
MICROWIRE/PLUS Slave Mode Operation
Table 8
summarizes the settings required to enter the
Slave mode of operation.
TABLE 8. MICROWIRE/PLUS Mode Settings
This table assumes that the control flag MSEL is set.
G4 (SO) G5 (SK) G4 G5 Operation
Config. Bit Config. Bit Fun. Fun.
1 1 SO Int. MICROWIRE/PLUS
SK Master
0 1 TRI- Int. MICROWIRE/PLUS
STATE SK Master
1 0 SO Ext. MICROWIRE/PLUS
SK Slave
0 0 TRI- Ext. MICROWIRE/PLUS
STATE SK Slave
The user must set the BUSY flag immediately upon entering the Slave mode. This will ensure that all data bitssent by the Master will be shifted properly. After eight clock pulses the BUSY flag will be cleared and the sequence may be re­peated.
Alternate SK Phase Operation
The device allows either the normal SK clock or analternate phase SK clock to shift datain andout ofthe SIO register. In both the modes the SK is normally low. In the normal mode data is shifted in on the rising edge of the SK clock and the data is shifted out on the falling edge of the SK clock. The SIO register is shifted on each fallingedge of theSK clock in the normal mode. In the alternate SK phase mode the SIO register is shifted on the rising edge of the SK clock.
A control flag, SKSEL, allows either the normal SK clock or the alternate SK clock to be selected. Resetting SKSEL causes the MICROWIRE/PLUS logic to be clocked from the normal SK signal. Setting the SKSEL flag selects the alter­nate SK clock. The SKSELis mapped intothe G6 configura­tion bit. The SKSEL flag will power up in the reset condition, selecting the normal SK signal.
Memory Map
All RAM, ports and registers (except A and PC) are mapped into data memory address space
Address Contents
00 to 6F On-Chip RAM bytes 70 to BF Unused RAM Address Space C0 Timer T2 Lower Byte C1 Timer T2 Upper Byte C2 Timer T2 Autoload Register T2RA Lower Byte C3 Timer T2 Autoload Register T2RA Upper Byte C4 Timer T2 Autoload Register T2RB Lower Byte C5 Timer T2 Autoload Register T2RB Upper Byte C6 Timer T2 Control Register C7 WATCHDOG Service Register (Reg:WDSVR) C8 MIWU Edge Select Register (Reg:WKEDG) C9 MIWU Enable Register (Reg:WKEN) CA MIWU Pending Register (Reg:WKPND) CB A/D Converter Control Register (Reg:ENAD) CC A/D Converter Result Register (Reg: ADRSLT) CD to CF Reserved D0 Port L Data Register D1 Port L Configuration Register D2 Port L Input Pins (Read Only) D3 Reserved for Port L D4 Port G Data Register D5 Port G Configuration Register D6 Port G Input Pins (Read Only) D7 Port I Input Pins (Read Only) D8 Port C Data Register D9 Port C Configuration Register DA Port C Input Pins (Read Only) DB Reserved for Port C DC Port D Data Register DD to DF Reserved for Port D E0 to E5 Reserved E6 Timer T1 Autoload Register T1RB Lower Byte E7 Timer T1 Autoload Register T1RB Upper Byte E8 ICNTRL Register E9 MICROWIRE Shift Register EA Timer T1 Lower Byte EB Timer T1 Upper Byte EC Timer T1 Autoload Register T1RA Lower Byte ED Timer T1 Autoload Register T1RA Upper Byte EE CNTRL Control Register EF PSW Register F0 to FB On-Chip RAM Mapped as Registers FC X Register FD SP Register FE B Register FF Reserved
Note: Reading memory locations 70-7F Hex will return all ones. Reading other unused memory locations will return undefined data.
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Addressing Modes
The device has ten addressing modes, six for operand ad­dressing and four for transfer of control.
OPERAND ADDRESSING MODES Register Indirect
This is the “normal” addressing mode. The operand is the data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post increment or decrement of pointer)
This addressing mode is used with the LD and X instruc­tions. The operand is the data memory addressed by the B pointer or X pointer. This is a register indirect mode that au­tomatically post increments or decrements the B or X regis­ter after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly points to the data memory for the operand.
Immediate
The instruction contains an 8-bit immediate field as the oper­and.
Short Immediate
This addressing mode is used with the Load BImmediate in­struction. The instruction contains a 4-bit immediate field as the operand.
Indirect
TRANSFER OF CONTROL ADDRESSING MODES
Relative
Absolute
This mode is used with the JMP and JSR instructions, with the instruction field of 12 bits replacing the lower 12 bits of the program counter (PC). This allows jumping to any loca­tion in the current 4k program memory segment.
Absolute Long
Indirect
This mode is used with the JID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a location in the program memory. The contents of this program memory location serve as a partial address (lower 8 bits of PC) for the jump to the next instruc­tion.
Note: The VIS is a special case of the Indirect Transfer of Control addressing
mode, where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter (PC) in order to jump to the associated interrupt ser­vice routine.
Instruction Set
Register and Symbol Definition
Registers
A 8-Bit Accumulator Register B 8-Bit Address Register X 8-Bit Address Register SP 8-Bit Stack Pointer Register PC 15-Bit Program Counter Register PU Upper 7 Bits of PC PL Lower 8 Bits of PC C 1-Bit of PSW Register for Carry HC 1-Bit of PSW Register for Half Carry GIE 1-Bit of PSW Register for Global Interrupt
Enable VU Interrupt Vector Upper Byte VL Interrupt Vector Lower Byte
Symbols
[B] Memory Indirectly Addressed by B Register [X] Memory Indirectly Addressed by X Register MD Direct Addressed Memory Mem Direct Addressed Memory or [B] Meml Direct Addressed Memory or [B] or Immediate
Data Imm 8-Bit Immediate Data
Registers
Symbols
Reg Register Memory: Addresses F0 to FF
(Includes B, X and SP)
Bit Bit Number (0 to 7)
←
Loaded with
↔
Exchanged with
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Page 31
Instruction Set (Continued)
INSTRUCTION SET
ADD A,Meml ADD A←A + Meml ADC A,Meml ADD with Carry A←A+Meml+C,C←Carry
HC←Half Carry
SUBC A,Meml Subtract with Carry A←AMeml+C,C←Carry
HC←Half Carry AND A,Meml Logical AND A←A and Meml ANDSZ A,Imm Logical AND Immed., Skip if Zero Skip next if (A and Imm)=0 OR A,Meml Logical OR A←A or Meml XOR A,Meml Logical EXclusive OR A←A xor Meml IFEQ MD,Imm IF EQual Compare MD and Imm, Do next if MD=Imm IFEQ A,Meml IF EQual Compare A and Meml, Do next if A=Meml IFNE A,Meml IF Not Equal Compare A and Meml, Do next if A
≠
Meml
IFGT A,Meml IF Greater Than Compare A and Meml, Do next if A
>
Meml
IFBNE
#
If B Not Equal Do next if lower 4 bits of B≠Imm DRSZ Reg Decrement Reg., Skip if Zero Reg←Reg− 1, Skip if Reg=0 SBIT
#
,Mem Set BIT 1 to bit, Mem (bit=0 to 7 immediate)
RBIT
#
,Mem Reset BIT 0 to bit, Mem
IFBIT
#
,Mem IF BIT If bit in A or Mem is true do next instruction RPND Reset PeNDing Flag Reset Software Interrupt Pending Flag X A,Mem EXchange A with Memory A
↔
Mem
X A,[X] EXchange A with Memory [X] A
↔
[X] LD A,Meml LoaD A with Memory A←Meml LD A,[X] LoaD A with Memory [X] A←[X] LD B,Imm LoaD B with Immed. B←Imm LD Mem,Imm LoaD Memory Immed Mem←Imm LD Reg,Imm LoaD Register Memory Immed. Reg←Imm XA,[B
±
] EXchange A with Memory [B] A↔[B], (B←B±1)
XA,[X
±
] EXchange A with Memory [X] A↔[X], (X
←
±
1)
LD A, [B
±
] LoaD A with Memory [B] A←[B], (B←B±1)
LD A, [X
±
] LoaD A with Memory [X] A←[X], (X←X±1)
LD [B
±
],Imm LoaD Memory [B] Immed. [B]←Imm, (B←B±1) CLR A CLeaR A A←0 INC A INCrement A A←A+1 DEC A DECrementA A←A−1 LAID Load A InDirect from ROM A←ROM (PU,A) DCOR A Decimal CORrect A A←BCD correction of A (follows ADC, SUBC) RRC A Rotate A Right thru C C→A7→…→A0→C RLC A Rotate A Left thru C C←A7←…←A0←C SWAP A SWAP nibbles of A A7…A4
↔
A3…A0 SC Set C C←1, HC←1 RC Reset C C←0, HC←0 IFC IF C IF C is true, do next instruction IFNC IF Not C If C is not true, do next instruction POP A POP the stack into A SP←SP+1,A←[SP] PUSH A PUSH A onto the stack [SP]←A, SP←SP−1 VIS Vector to Interrupt Service Routine PU←[VU], PL←[VL] JMPL Addr. Jump absolute Long PC←ii (ii=15 bits, 0 to 32k) JMP Addr. Jump absolute PC9…0←i(i=12 bits) JP Disp. Jump relative short PC←PC+r(ris−31to+32, except 1)
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Page 32
Instruction Set (Continued)
JSRL Addr. Jump SubRoutine Long [SP]←PL, [SP−1]←PU,SP−2, PC←ii JSR Addr Jump SubRoutine [SP]←PL, [SP−1]←PU,SP−2, PC9…0←i JID Jump InDirect PL←ROM (PU,A) RET RETurn from subroutine SP + 2, PL←[SP], PU←[SP−1] RETSK RETurn and SKip SP + 2, PL←[SP],PU←[SP−1] RETI RETurn from Interrupt SP + 2, PL←[SP],PU←[SP−1],GIE←1 INTR Generate an Interrupt [SP]←PL, [SP−1]←PU, SP−2, PC←0FF NOP No OPeration PC←PC+1
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Page 33
Instruction Execution Time
Most instructions are single byte (with immediate addressing mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute. Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
[B] Direct Immed.
ADD 1/1 3/4 2/2 ADC 1/1 3/4 2/2 SUBC 1/1 3/4 2/2 AND 1/1 3/4 2/2 OR 1/1 3/4 2/2 XOR 1/1 3/4 2/2 IFEQ 1/1 3/4 2/2 IFNE 1/1 3/4 2/2 IFGT 1/1 3/4 2/2 IFBNE 1/1 DRSZ 1/3 SBIT 1/1 3/4 RBIT 1/1 3/4 IFBIT 1/1 3/4
RPND 1/1
Instructions Using A & C
CLRA 1/1
INCA 1/1
DECA 1/1
LAID 1/3
DCOR 1/1
RRCA 1/1
RLCA 1/1
SWAPA 1/1
SC 1/1
RC 1/1
IFC 1/1
IFNC 1/1
PUSHA 1/3
POPA 1/3
ANDSZ 2/2
Transfer of Control Instructions
JMPL 3/4
JMP 2/3
JP 1/3
JSRL 3/5
JSR 2/5
JID 1/3
VIS 1/5
RET 1/5
RETSK 1/5
RETI 1/5
INTR 1/7
NOP 1/1
Memory Transfer Instructions
Register Direct Immed. Register Indirect
Indirect Auto Incr. & Decr.
[B] [X] [B+, B−] [X+, X−]
X A, (Note 12) 1/1 1/3 2/3 1/2 1/3 LD A, (Note 12) 1/1 1/3 2/3 2/2 1/2 1/3 LD B, Imm 1/1 (IF B
<
16)
LD B, Imm 2/2 (IF B
>
15) LD Mem, Imm 2/2 3/3 2/2 LD Reg, Imm 2/3 IFEQ MD, Imm 3/3
Note 12: Memory location addressed by B or X or directly.
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Page 34
Instruction Execution Time (Continued)
OPCODE TABLE
Upper Nibble
F E D C BA9 876 5 4 3 2 10
Lower Nibble
JP−15 JP−31 LD 0F0, #i DRSZ
0F0
RRCA RC ADC
A,#i
ADC
A,[B]
IFBIT
0,[B]
ANDSZ
A, #i
LD
B,#0F
IFBNE 0 JSR
x000–x0FF
JMP
x000–x0FF
JP+17 INTR 0
JP−14 JP−30 LD 0F1, #i DRSZ
0F1
* SC SUBC
A, #i
SUBC
A,[B]
IFBIT
1,[B]
*LD
B,#0E
IFBNE 1 JSR
x100–x1FF
JMP
x100–x1FF
JP+18 JP+2 1
JP−13 JP−29 LD 0F2, #i DRSZ
0F2
X
A,[X+]
X
A,[B+]
IFEQ
A,#i
IFEQ
A,[B]
IFBIT
2,[B]
*LD
B,#0D
IFBNE 2 JSR
x200–x2FF
JMP
x200–x2FF
JP+19 JP+3 2
JP−12 JP−28 LD 0F3, #i DRSZ
0F3
X
A,[X−]
X
A,[B−]
IFGT
A,#i
IFGT
A,[B]
IFBIT
3,[B]
*LD
B,#0C
IFBNE 3 JSR
x300–x3FF
JMP
x300–x3FF
JP+20 JP+4 3
JP−11 JP−27 LD 0F4, #i DRSZ
0F4
VIS LAID ADD
A,#i
ADD
A,[B]
IFBIT
4,[B]
CLRA LD
B,#0B
IFBNE 4 JSR
x400–x4FF
JMP
x400–x4FF
JP+21 JP+5 4
JP−10 JP−26 LD 0F5, #i DRSZ
0F5
RPND JID AND
A,#i
AND
A,[B]
IFBIT
5,[B]
SWAPA LD
B,#0A
IFBNE 5 JSR
x500–x5FF
JMP
x500–x5FF
JP+22 JP+6 5
JP−9 JP−25 LD 0F6, #i DRSZ
0F6
X A,[X] X
A,[B]
XOR
A,#i
XOR
A,[B]
IFBIT
6,[B]
DCORA LD
B,#09
IFBNE 6 JSR
x600–x6FF
JMP
x600–x6FF
JP+23 JP+7 6
JP−8 JP−24 LD 0F7, #i DRSZ
0F7
* * OR A,#i OR
A,[B]
IFBIT
7,[B]
PUSHA LD
B,#08
IFBNE 7 JSR
x700–x7FF
JMP
x700–x7FF
JP+24 JP+8 7
JP−7 JP−23 LD 0F8, #i DRSZ
0F8
NOP RLCA LD A,#i IFC SBIT
0,[B]
RBIT
0,[B]
LD
B,#07
IFBNE 8 JSR
x800–x8FF
JMP
x800–x8FF
JP+25 JP+9 8
JP−6 JP−22 LD 0F9, #i DRSZ
0F9
IFNE
A,[B]
IFEQ
Md,#i
IFNE
A,#i
IFNC SBIT
1,[B]
RBIT
1,[B]
LD
B,#06
IFBNE 9 JSR
x900–x9FF
JMP
x900–x9FF
JP+26 JP+10 9
JP−5 JP−21 LD 0FA, #i DRSZ
0FA
LD
A,[X+]
LD
A,[B+]
LD
[B+],#i
INCA SBIT
2,[B]
RBIT
2,[B]
LD
B,#05
IFBNE 0A JSR
xA00–xAFF
JMP
xA00–xAFF
JP+27 JP+11 A
JP−4 JP−20 LD 0FB, #i DRSZ
0FB
LD
A,[X−]
LD
A,[B−]
LD
[B−],#i
DECA SBIT
3,[B]
RBIT
3,[B]
LD
B,#04
IFBNE 0B JSR
xB00–xBFF
JMP
xB00–xBFF
JP+28 JP+12 B
JP−3 JP−19 LD 0FC, #i DRSZ
0FC
LD
Md,#i
JMPL X A,Md POPA SBIT
4,[B]
RBIT
4,[B]
LD
B,#03
IFBNE 0C JSR
xC00–xCFF
JMP
xC00–xCFF
JP+29 JP+13 C
JP−2 JP−18 LD 0FD, #i DRSZ
0FD
DIR JSRL LD
A,Md
RETSK SBIT
5,[B]
RBIT
5,[B]
LD
B,#02
IFBNE 0D JSR
xD00–xDFF
JMP
xD00–xDFF
JP+30 JP+14 D
JP−1 JP−17 LD 0FE, #i DRSZ
0FE
LD
A,[X]
LD
A,[B]
LD
[B],#i
RET SBIT
6,[B]
RBIT
6,[B]
LD
B,#01
IFBNE 0E JSR
xE00–xEFF
JMP
xE00–xEFF
JP+31 JP+15 E
JP−0 JP−16 LD 0FF, #i DRSZ
0FF
* * LD B,#i RETI SBIT
7,[B]
RBIT
7,[B]
LD
B,#00
IFBNE 0F JSR
xF00–xFFF
JMP
xF00–xFFF
JP+32 JP+16 F
Where,
i is the immediate data
Md is a directly addressed memory location
* is an unused opcode
The opcode 60 Hex is also the opcode for IFBIT #i,A
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Page 35
Development Tools Support
OVERVIEW
National is engaged with an international community ofinde­pendent 3rd party vendors who provide hardware and soft­ware development tool support. Through National’s interac­tion and guidance, these tools cooperate to form a choice of solutions that fits each developer’s needs.
SUMMARY OF TOOLS COP8 Evaluation Tools
•
COP8–NSEVAL: Free Software Evaluation package for Windows. A fully integrated evaluation environment for COP8, including versions of WCOP8 IDE (IntegratedDe­velopment Environment), COP8-NSASM, COP8-MLSIM, COP8C, DriveWay
™
COP8, Manuals, and other COP8
information.
•
COP8–MLSIM: Free Instruction Level Simulator tool for Windows. For testing and debugging software instruc­tions only (No I/O or interrupt support).
•
COP8–EPU: Very Low cost COP8 Evaluation & Pro­gramming Unit. Windows based evaluation and hardware-simulation tool, with COP8device programmer and erasable samples. Includes COP8-NSDEV, Drive­way COP8 Demo, MetaLink Debugger, I/O cables and power supply.
•
COP8–EVAL-ICUxx: Very Low cost evaluation and de­sign test board for COP8ACC and COP8SGx Families, from ICU. Real-time environment with add-on A/D, D/A, and EEPROM. Includes software routines and reference designs.
•
Manuals,Applications Notes, Literature: Availablefree from our web site at: www.national.com/cop8.
COP8 Integrated Software/Hardware Design Develop­ment Kits
•
COP8-EPU: Very Low cost Evaluation & Programming Unit. Windows based development and hardware­simulation tool for COPSx/xG families,with COP8device programmer and samples. Includes COP8-NSDEV, Driveway COP8 Demo, MetaLink Debugger, cables and power supply.
•
COP8-DM: Moderate cost Debug Module from MetaLink. A Windows based, real-time in-circuit emulation tool with COP8 device programmer. Includes COP8-NSDEV, DriveWay COP8 Demo, MetaLink Debugger, power sup­ply, emulation cables and adapters.
COP8 Development Languages and Environments
•
COP8-NSASM: Free COP8 Assembler v5 for Win32. Macro assembler, linker, and librarian for COP8 software development. Supports all COP8 devices. (DOS/Win16 v4.10.2 available with limited support). (Compatible with WCOP8 IDE, COP8C, and DriveWay COP8).
•
COP8-NSDEV: Very low cost Software Development Package for Windows. An integrated development envi­ronment for COP8, including WCOP8 IDE, COP8­NSASM, COP8-MLSIM.
•
COP8C: Moderately priced C Cross-Compiler and Code Development System from Byte Craft (no code limit). In-
cludes BCLIDE (Byte Craft Limited Integrated Develop­ment Environment) for Win32, editor, optimizing C Cross­Compiler, macro cross assembler, BC-Linker, and MetaLink tools support. (DOS/SUN versions available; Compiler is installable under WCOP8 IDE; Compatible with DriveWay COP8).
•
EWCOP8-KS: Very Low cost ANSI C-Compiler and Em­bedded Workbench from IAR (Kickstart version: COP8Sx/Fx only with 2k code limit; No FP). A fully inte­grated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, Liberian, C-Spy simulator/debugger, PLUS MetaLink EPU/DM emulator support.
•
EWCOP8-AS: Moderately priced COP8 Assembler and Embedded Workbenchfrom IAR (no code limit). Afully in­tegrated Win32 IDE, macro assembler, editor, linker, li­brarian, and C-Spy high-level simulator/debugger with I/O and interrupts support. (Upgradeable with optional C-Compiler and/or MetaLink Debugger/Emulator sup­port).
•
EWCOP8-BL: Moderately priced ANSI C-Compiler and Embedded Workbench from IAR (Baseline version: All COP8 devices; 4k code limit; no FP). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker,librarian, and C-Spy high-level simulator/debugger. (Upgradeable; CWCOP8-M MetaLink tools interface sup­port optional).
•
EWCOP8: Full featured ANSI C-Compiler and Embed­ded Workbench for Windows from IAR (no code limit). A fully integrated Win32 IDE, ANSI C-Compiler, macro as­sembler, editor, linker, librarian, and C-Spy high-level simulator/debugger. (CWCOP8-M MetaLink tools inter­face support optional).
•
EWCOP8-M: Full featuredANSI C-Compiler and Embed­ded Workbench for Windows from IAR (no code limit). A fully integrated Win32 IDE, ANSI C-Compiler, macro as­sembler, editor, linker, librarian, C-Spy high-level simulator/debugger, PLUS MetaLink debugger/hardware interface (CWCOP8-M).
COP8 Productivity Enhancement Tools
•
WCOP8 IDE: Very Low cost IDE (Integrated Develop­ment Environment) from KKD. Supports COP8C, COP8­NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink debugger under a common Windows Project Manage­ment environment. Code development, debug, and emu­lation tools can be launched from the project window framework.
•
DriveWay-COP8: Low cost COP8 Peripherals Code Generation tool from Aisys Corporation. Automatically generates tested and documented Cor Assembly source code modules containing I/O drivers and interrupt han­dlers for each on-chip peripheral. Application specific code can be inserted for customization using the inte­grated editor. (Compatible with COP8-NSASM, COP8C, and WCOP8 IDE.)
•
COP8-UTILS: Free set of COP8 assembly code ex­amples, device drivers, and utilitiesto speed up code de­velopment.
•
COP8-MLSIM: Free Instruction Level Simulator tool for Windows. For testing and debugging software instruc­tions only (No I/O or interrupt support).
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Page 36
Development Tools Support
(Continued)
COP8 Real-Time Emulation Tools
•
COP8-DM: MetaLink Debug Module. A moderately priced real-time in-circuit emulation tool, with COP8 de­vice programmer. Includes COP8-NSDEV, DriveWay COP8 Demo, MetaLink Debugger, power supply, emula­tion cables and adapters.
•
IM-COP8: MetaLink iceMASTER®. A full featured, real- time in-circuit emulator for COP8 devices. Includes Met­aLink Windows Debugger, and power supply. Package­specific probes and surface mount adaptors are ordered separately.
COP8 Device Programmer Support
•
MetaLink’s EPU and Debug Module include development device programming capability for COP8 devices.
•
Third-party programmers and automatic handling equip­ment cover needs from engineering prototype and pilot production, to full production environments.
•
Factory programming available for high-volume require­ments.
TOOLS ORDERING NUMBERS FOR THE COP87L88CF FAMILY DEVICES
Vendor Tools Order Number Cost Notes
National COP8-NSEVAL COP8-NSEVAL Free Web site download
COP8-NSASM COP8-NSASM Free Included in EPU and DM. Web site download COP8-MLSIM COP8-MLSIM Free Included in EPU and DM. Web site download COP8-NSDEV COP8-NSDEV VL Included in EPU and DM. Order CD from website COP8-EPU Not available for this device COP8-DM Contact MetaLink Development
Devices
COP87L84CF COP87L88CF
VL 16k OTP devices. No windowed devices
IM-COP8 Contact MetaLink
MetaLink COP8-EPU Not available for this device
COP8-DM DM4-COP8-888CF (10
MHz), plus PS-10, plus DM-COP8/xxx (ie. 28D)
M Included p/s (PS-10), target cable of choice (DIP or
PLCC; i.e. DM-COP8/28D), 16/20/28/40 DIP/SO and 44 PLCC programming sockets. Add target adapter (if needed)
DM Target Adapters
MHW-CONV39 L DM target converters for 28SO
IM-COP8 IM-COP8-AD-464 (-220)
(10 MHz maximum)
H Base unit 10 MHz; -220 = 220V; add probe card
(required) and target adapter (if needed); included software and manuals
IM Probe Card PC-884CF28DW-AD-10 M 10 MHz 28 DIP probe card; 2.5V to 6.0V
PC-888CF40DW-AD-10 M 10 MHz 40 DIP probe card; 2.5V to 6.0V PC-888CF44PW-AD-10 M 10 MHz 44 PLCC probe card; 2.5V to 6.0V
IM Probe Target Adapter
MHW-SOIC28 L 28 pin SOIC adapter for probe card
ICU COP8-EVAL Not available for this device
KKD WCOP8-IDE WCOP8-IDE VL Included in EPU and DM
IAR EWCOP8-xx See summary above L - H Included all software and manuals
Byte
Craft
COP8C COP8C M Included all software and manuals
Aisys DriveWay COP8 DriveWay COP8 L Included all software and manuals
OTP Programmers Contact vendors L - H For approved programmer listings and vendor
information, go to our OTP support page at: www.national.com/cop8
Cost: Free; VL =
<
$100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k
www.national.com 36
Page 37
Development Tools Support (Continued)
WHERE TO GET TOOLS
Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors.
Vendor Home Office Electronic Sites Other Main Offices
Aisys U.S.A.: Santa Clara, CA www.aisysinc.com Distributors
1-408-327-8820 info
@
aisysinc.com
fax: 1-408-327-8830
Byte Craft U.S.A. www.bytecraft.com Distributors
1-519-888-6911 info
@
bytecraft.com
fax: 1-519-746-6751
IAR Sweden: Uppsala www.iar.se U.S.A.: San Francisco
+46 18 16 78 00 info
@
iar.se 1-415-765-5500
fax: +46 18 16 78 38 info
@
iar.com fax: 1-415-765-5503
info
@
iarsys.co.uk U.K.: London
info
@
iar.de +44 171 924 33 34
fax: +44 171 924 53 41 Germany: Munich +49 89 470 6022 fax: +49 89 470 956
ICU Sweden: Polygonvaegen www.icu.se Switzeland: Hoehe
+46 8 630 11 20 support
@
icu.se +41 34 497 28 20
fax: +46 8 630 11 70 support
@
icu.ch fax: +41 34 497 28 21 KKD Denmark: www.kkd.dk MetaLink U.S.A.: Chandler, AZ www.metaice.com Germany: Kirchseeon
1-800-638-2423 sales
@
metaice.com 80-91-5696-0
fax: 1-602-926-1198 support
@
metaice.com fax: 80-91-2386
bbs: 1-602-962-0013 islanger
@
metalink.de
www.metalink.de Distributors Worldwide
National U.S.A.: Santa Clara, CA www.national.com/cop8 Europe: +49 (0) 180 530 8585
1-800-272-9959 support
@
nsc.com fax: +49 (0) 180 530 8586
fax: 1-800-737-7018 europe.support
@
nsc.com Distributors Worldwide
The following companies have approved COP8 program­mers in a variety of configurations. Contact your local office or distributor. You can link to their web sites and get the lat­est listing of approved programmers from National’s COP8 OTP Support page at: www.national.com/cop8.
Advantech; Advin; BP Microsystems; Data I/O; Hi-Lo Sys­tems; ICE Technology; Lloyd Research; Logical Devices; MQP; Needhams; Phyton; SMS; Stag Programmers; Sys­tem General; Tribal Microsystems; Xeltek.
Customer Support
Complete product information and technical support is avail­able from National’s customer response centers, and from our on-line COP8 customer support sites.
www.national.com37
Page 38
Physical Dimensions inches (millimeters) unless otherwise noted
Molded SO Wide Body Package (M)
Order Number COP87L84CFM-XE
NS Package Number M28B
Molded Dual-In-Line Package (N)
Order Number COP87L84CFN-XE
NS Package Number N28B
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Page 39
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number COP87L88CFN-XE
NS Package Number N40A
Plastic Leaded Chip Carrier (V)
Order Number COP87L88CFV-XE
NS Package Number V44A
www.national.com39
Page 40
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
National Semiconductor Corporation
Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected]
National Semiconductor Europe
Fax: +49 (0) 1 80-530 85 86
Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80
National Semiconductor Asia Pacific Customer Response Group
Tel: 65-2544466 Fax: 65-2504466 Email: [email protected]
National Semiconductor Japan Ltd.
Tel: 81-3-5639-7560 Fax: 81-3-5639-7507
www.national.com
COP87L88CF 8-Bit CMOS OTP Microcontrollers with 16k Memory and A/D Converter
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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