Datasheet CN-0279 Datasheet (ANALOG DEVICES)

Circuit Note

6 GHz Ultrahigh Dynamic Range Differential
Amplifier

Rev. 0

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0.1µF

0.1µF

0.1µF

33pF

36nH

0.1µF

ADL5565

G = 12dB

2.5pF

XFMR

1:2 Z

TC2-1T

INPUT

Z = 50Ω

Z

I

= 100Ω

INTERNAL

INPUT Z

AD9642

14-BIT

205MSPS

ADC

620nH

5Ω

5Ω

187Ω40Ω217Ω

+3.3V

+1.8V

DRVDD

+1.8V
AVDD

5.6dB LOSS 0.2dB LOSS

5.8dB LOSS

11.8dB GAI N

FS = 1.75V

p-p DIFF

620nH

0.5dB LOSS

ANALOG

INPUT

+1.5dBm FS

AT 127MHz

OVERALL

GAIN = 5.5dB

100Ω

100Ω

0.1µF

5Ω

5Ω

15Ω

15Ω

2.85kΩ

1.2pF

1.2pF

33pF

VCM

36nH

VIP2

VIN2

VIP1

VIN1

10823-001

Circuits from the Lab™ reference circuits are engineered and
tested for quick and easy system integration to help solve today’s
analog, mixed-signal, and RF design challenges. For more
information and/or support, visit www.analog.com/CN0279.

High IF Sampling Receiver Front End with Band-Pass Filter

EVALUATION AND DESIGN SUPPORT

Design and Integration Files

Schematics, Layout Files, Bill of Materials

CIRCUIT FUNCTION AND BENEFITS

The circuit, shown in Figure 1, is a narrow, band-pass receiver
front end based on the ADL5565 ultralow noise differential
amplifier driver and the AD9642 14-bit, 250 MSPS analog-to­digital converter (ADC).

The third-order, Butterworth antialiasing filter is optimized based
on the performance and interface requirements of the amplifier
and ADC. The total insertion loss due to the filter network and
other components is only 5.8 dB.

The overall circuit has a bandwidth of 18 MHz with a pass-band
flatness of 3 dB. The signal-to-noise ratio (SNR) and spurious­free dynamic range (SFDR) measured with a 127 MHz analog
input are 71.7 dBFS and 92 dBc, respectively. The sampling
frequency is 205 MSPS, thereby positioning the IF input signal
in the second Nyquist zone between 102.5 MHz and 205 MHz.

CN-0279

Devices Connected/Referenced

AD9642 14-Bit, 250 MSPS Analog-to-Digital Converter

ADL5565

CIRCUIT DESCRIPTION

The circuit accepts a single-ended input and converts it to
differential input using a wide bandwidth (3 GHz) Mini-Circuits
TC2-1T 1:2 transformer. The 6 GHz ADL5565 differential
amplifier has a differential input impedance of 200 Ω when
operating at a gain of 6 dB, and 100 Ω when operating at a
gain of 12 dB. A gain option of 15.5 dB is also available.

The ADL5565 is an ideal driver for the AD9642, and the fully
differential architecture through the band-pass filter and into
the ADC provides good high frequency common-mode rejection,
as well as minimizes second-order distortion products. The

ADL5565 provides a gain of 6 dB or 12 dB, depending on the input

connection. In the circuit, a gain of 12 dB was used to compensate
for the insertion loss of the filter network and transformer
(approximately 5.8 dB), providing an overall signal gain of 5.5 dB.

Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices

each circuit, and their function and performance have been tested and verified in a lab environment at

be liable for direct, indirect, special, inciden

Figure 1. 14-Bit, 250 MSPS Wideband Receiver Front End (Simplified Schematic: All Connections and Decoupling Not Shown)

Gains, Losses, and Signal Levels Measured Values for an Input Frequency of 127 MHz

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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CN-0279 Circuit Note

39.8pF

(2.53pF)

0.987pF

(2.53pF)

0.987pF

39.5nH 39.8pF

100Ω

200Ω

(620nH)

1.59µH

(620nH)

1.59µH

100Ω

+

–

39.5nH

10443-002

–40

–35

–30

–25

–20

–15

–10

–5

0

AMPLITUDE (dBFS)

ANALOG I NP UT FREQUENCY (MHz)

50 250200150100 300

10823-003

50

55

60

65

70

75

80

85

90

95

118 120 122 124 126 128 130 132 134 136

SNR (dBFS) , SFDR (dBc)

ANALOG I NP UT FREQUENCY (MHz)

SNR (dBFS)

SFDR (dBc)

10823-004

An input signal of 1.5 dBm produces a full-scale 1.75 V p-p
differential signal at the ADC input.

The antialiasing filter is a third-order, Butterworth filter designed
with a standard filter design program. A Butterworth filter was
chosen because of its pass-band flatness. A third-order filter
yields an ac noise bandwidth ratio of 1.05 and can be designed
with the aid of several free filter programs such as Nuhertz
Technologies Filter Free, or the quite universal circuit simulator
(Qucs) free simulation.

To achieve best performance, load the ADL5565 with a net
differential load of 200 Ω. The 15 Ω series resistors isolate the
filter capacitance from the amplifier output, and the 100 Ω resistors
in parallel with the downstream impedance yield a net load
impedance of 217 Ω when added to the 30 Ω series resistance.

The 5 Ω resistors in series with the ADC inputs isolate internal
switching transients from the filter and the amplifier.

The 2.85 kΩ input impedance was determined using the down­loadable spreadsheet on the AD9642 webpage. Simply use the
parallel track mode values at the center of the IF frequency of
interest. The spreadsheet shows both the real and imaginary values.

The third-order, Butterworth filter was designed with a source
impedance (differential) of 200 Ω, a load impedance (differential)
of 200 Ω, a center frequency of 127 MHz, and a 3 dB bandwidth
of 20 MHz. The calculated values from a standard filter design
program are shown in Figure 1. Because of the high values of
series inductance required, the 1.59 µH inductors were decreased
to 620 nH, and the 0.987 pF capacitors increased proportionally
to 2.53 pF, thereby maintaining the same resonant frequency of
127 MHz, with more realistic component values.

The measured performance of the system is summarized in
Table 1, where the 3 dB bandwidth, 18 MHz centered at 127 MHz.
The total insertion loss of the network is approximately 5.8 dB. The
frequency response is shown in Figure 3, and the SNR and SFDR
performance are shown in Figure 4.

Table 1. Measured Performance of the Circuit

Performance Specifications at −1 dBFS
(FS = 1.75 V p-p), Sample Rate = 205 MSPS

Final Results

Center Frequency 127 MHz
Pass-Band Flatness (118 MHz to 136 MHz) 3 dB
SNRFS at 127 MHz 71.7 dBFS
SFDR at 127 MHz 92 dBc
H2/H3 at 127 MHz 93 dBc/92 dBc
Overall Gain at 127 MHz 5.5 dB
Input Drive at 127 MHz 0.5 dBm (−1 dBFS)

Figure 3. Pass-Band Flatness Performance vs. Frequency

Figure 2. Starting Design for Third-Order, Differential Butterworth Filter with

Z

= 200 Ω, ZL = 200 Ω, FC = 127 MHz, and BW = 20 MHz

S

The internal 2.5 pF capacitance of the ADC was subtracted
from the value of the second shunt capacitor to yield a value of

37.3 pF. In the circuit, this capacitor was located near the ADC
to reduce/absorb the charge kickback.

The values chosen for the final filter passive components (after
adjusting for actual circuit parasitics) are shown in Figure 1.

Figure 4. SNR/SFDR Performance vs. Frequency, Sample Rate = 205 MSPS

Rev. 0 | Page 2 of 5

Circuit Note CN-0279

0.1µF

0.1µF

0.1µF

C

AAF1

C

AAF2

C

AAF2

L

AAF

L

AAF1

L

AAF1

L

AAF

0.1µF

GAIN

C

ADC

XFMR

1:2 Z

INPUT

Z = 50Ω

INTERNAL

INPUT Z

ADC

INTERNAL

INPUT Z

Z

O

/2

Z

O

/2

Z

AAFL

Z

AAFS

Z

AL

AVDD_AMP

DRVDD

AVDD

ANALOG

INPUT

Z = R

I

/2

R

TADC

R

TADC

0.1µF

R

KB

R

KB

R

A

R

I

R

A

R

ADC

C

AAF3

VCM

10823-005

Figure 5. Generalized Differential Amplifier/ADC Interface with Band-Pass Filter

Filter and Interface Design Procedure

In this section, a general approach to the design of the amplifier/
ADC interface with a band-pass filter is presented. To achieve
optimum performance (bandwidth, SNR, and SFDR), there are
certain design constraints placed on the general circuit by the
amplifier and the ADC.

1. The amplifier must see the correct dc load recommended

by the data sheet for optimum performance.

2. The correct amount of series resistance must be used between

the amplifier and the load presented by the filter. This is to
prevent undesired peaking in the pass band.

3. The input to the ADC must be reduced by external parallel

resistors, and the correct series resistance must be used to
isolate the ADC from the filter. This series resistor also
reduces peaking.

The generalized circuit shown in Figure 5 applies to most high
speed differential amplifier/ADC interfaces and was used as a
basis for the band-pass filter. This design approach tends to
minimize the insertion loss of the filter by taking advantage of
the relatively high input impedance of most high speed ADCs
and the relatively low impedance of the driving source (amplifier).

The basic design process is as follows:

1. Set the external ADC termination resistors, R

the parallel combination of R

TAD C

and R

ADC

, so that

TAD C

is between

200 Ω and 400 Ω.

2. Select R

based on experience and/or the ADC data sheet

KB

recommendations, typically between 5 Ω and 36 Ω.

3. Calculate the filter load impedance using

Z

= 2R

AAFL

4. Select the amplifier external series resistor, R

less than 10 Ω if the amplifier differential output impedance
is 100 Ω to 200 Ω. Make R
output impedance of the amplifier is 12 Ω or less.

5. Select Z

is optimum for the particular differential amplifier chosen
using the following equation:

Z

= 2RA + Z

AL

|| (R

ADC

+ 2RKB)

between 5 Ω and 36 Ω if the

A

. Make RA

A

TADC

so that the total load seen by the amplifier, ZAL,

AAFL

AAFL

6. Calculate the filter source resistance by

7. Using a filter design program or tables design the filter

After running these preliminary calculations, the circuit must
be given a quick review for the following items.

1. The value of C

2. The ratio of Z

3. The value of C

4. The inductor, L

5. The value of C

In some cases, the filter design program can provide more than
one unique solution, especially with higher order filters. The
solution that uses the most reasonable set of component values
should always be chosen. Also, choose a configuration that ends
in a shunt capacitor so that it can be combined with the ADC
input capacitance.

Rev. 0 | Page 3 of 5

Z

= ZO + 2RA

AAFS

using the source and load impedances, Z

AAFS

and Z

AAFL

, type
of filter, bandwidth, and order. Use a bandwidth that is about
10% higher than the desired bandwidth of the application
pass band to ensure flatness in the frequency span.

must be at least 10 pF so that it is several

AAF3

times larger than C
the filter to variations in C

AAFL

. This minimizes the sensitivity of

ADC

.

ADC

to Z

must not be more than about 7 so

AAFS

that the filter is within the limits of most filter tables and
design programs.

must be at least 5 pF to minimize sensitivity

AAF1

to parasitic capacitance and component variations.

, must be a reasonable value of at least

AAF

several nH.

AFF2

and L

must be reasonable values.

AAF1

Sometimes circuit simulators can make these values too
low or too high. To make these values more reasonable,
simply ratio these values with better standard value
components that maintain the same resonant frequency.

CN-0279 Circuit Note

Circuit Optimization Techniques and Trade-Offs

The parameters in this interface circuit are very interactive;
therefore, it is almost impossible to optimize the circuit for all
key specifications (bandwidth, bandwidth flatness, SNR, SFDR,
and gain). However, the peaking, which often occurs in the
bandwidth response, can be minimized by varying R

The value of R

also affects SNR performance. Larger values,

A

and RKB.

A

while reducing the bandwidth peaking, tend to slightly increase
the SNR because of the higher signal level required to drive the
ADC full scale.

Select the R

series resistor on the ADC inputs to minimize

KB

distortion caused by any residual charge injection from the
internal sampling capacitor within the ADC. Increasing this
resistor also tends to reduce bandwidth peaking.

Howe v er, increasing R

increases signal attenuation, and the

KB

amplifier must drive a larger signal to fill the ADC input range.

For optimizing center frequency, pass-band characteristics, the
series capacitor, C

Normally, the ADC input termination resistor, R

, can be varied by a small amount.

AAF2

, is selected

TAD C

to make the net ADC input impedance between 200 Ω and 400 Ω,
which is typical of most amplifier characteristic load values. Using
too high or too low a value can have an adverse effect on the
linearity of the amplifier.

Balancing these trade-offs can be somewhat difficult. In this
design, each parameter was given equal weight; therefore, the
values chosen are representative of the interface performance
for all the design characteristics. In some designs, different values
can be chosen to optimize SFDR, SNR, or input drive level,
depending on system requirements.

The SFDR performance in this design is determined by two
factors: the amplifier and ADC interface component values, as
shown in Figure 1.

Note that the signal in this design is ac-coupled with the 0.1 µF
capacitors to block the common-mode voltages between the
amplifier, its termination resistors, and the ADC inputs. Refer to
the AD9642 data sheet for further details regarding common­mode voltages.

Rev. 0 | Page 4 of 5

Passive Component and PC Board Parasitic Considerations

The performance of this or any high speed circuit is highly
dependent on proper printed circuit board (PCB) layout. This
includes, but is not limited to, power supply bypassing, controlled
impedance lines (where required), component placement, signal
routing, and power and ground planes. See Tut o r ia l MT-031 and
Tutor i a l MT-101 for more detailed information regarding PCB
layout for high speed ADCs and amplifiers. In addition, see the

CN-0227 and the CN-0238.

Use low parasitic surface-mount capacitors, inductors, and resistors
for the passive components in the filter. The inductors chosen
are from the Coilcraft 0603CS series. The surface-mount capacitors
used in the filter are 5%, C0G, 0402 type for stability and accuracy.

See the CN-0279 Design Support Package

for the complete

documentation on the system.

COMMON VARIATIONS

The AD9643 is a dual version of the AD9642.

For lower power and bandwidth, the ADA4950-1 and/or

ADL5561/ADL5562 can also be used. These devices are pin

compatible with the other singles previously listed.

CIRCUIT EVALUATION AND TEST

This circuit uses a modified AD9642-250EBZ circuit board and
the HSC-ADC-E VA LCZ FPGA-based data capture board. The
two boards have mating high speed connectors, allowing for the
quick setup and evaluation of the performance of the circuit. The
modified AD9642-250EBZ board contains the circuit evaluated
as described in this note, and the HSC-ADC-EVA L CZ data
capture board is used in conjunction with VisualAnalog® evaluation
software, as well as the SPI Controller software to properly control
the ADC and capture the data. See User Guide UG-386 for the
schematics, BOM, and layout for the AD9642-250EBZ board.
The readme.txt file in the CN-0279 Design Support Package
describes the modifications made to the standard AD9642-250EBZ
board. Application Note AN-835 contains complete details on
how to set up the hardware and software to run the tests described
in this circuit note.

Circuit Note CN-0279

(Continued from first page) Circuits from the L ab circuits are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you

reserves the right to change any Circuits from the Lab circuits at any time without notic e but is under no obligation to do so.

registered trademarks are the property of their respective owners.

LEARN MORE

CN-0279 Design Support Package:
http://www.analog.com/CN0279-DesignSupport

UG-386 User Guide, Evaluating the AD9642/AD9634/AD6672

Analog-to-Digital Converters

Arrants, Alex, Brad Brannon and Rob Reede r, AN-835

Application Note, Understanding High Speed ADC Testing
and Evaluation, Analog Devices.

Ardizzoni, John. A Practical Guide to High-Speed Printed-

Circuit-Board Layout, Analog Dialogue 39-09, September 2005.

MT-031 Tutorial, Grounding Data Converters and Solving the

Mystery of “AGND” and “DGND”, Analog Devices.

MT-101 Tutorial, Decoupling Techniques, Analog Devices.

Quite Universal Circuit Simulator

Nuhertz Technologies, Filter Free Filter Design Program

Reeder, Rob, Achieve CM Convergence between Amps and ADCs,

Electronic Design, July 2010.

Reeder, Rob, Mine These High-Speed ADC Layout Nuggets For

Design Gold, Electronic Design, September 15, 2011.

Rarely Asked Questions: Considerations of High-Speed

Converter PCB Design, Part 1: Power and Ground Planes,
November 2010.

Rarely Asked Questions: Considerations of High-Speed

Converter PCB Design, Part 2: Using Power and Ground
Planes to Your Advantage, February 2011.

Rarely Asked Questions: Considerations of High-Speed Converter

PCB Design, Part 3: The E-Pad Low Down, June 2011.

Data Sheets and Evaluation Boards

AD9642 Data Sheet

ADL5565 Data Sheet

Circuit Evaluation Board (AD9642-250EBZ)

Standard Data Capture Platform (HSC-ADC-EVALCZ)

REVISION HISTORY

7/12—Revision 0: Initial Version

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©2012 Analog Devices, Inc. All rights reserved. Trademarks and

CN10823-0-7/12(0)

Rev. 0 | Page 5 of 5