Datasheet CN-0238 Datasheet (ANALOG DEVICES)

Page 1

Circuit Note

CN-0238

Devices Connected/Referenced

Circuits from the Lab™ reference circuits are engineered and tested for quick and easy system integration to help solve today’s

AD9434

analog, mixed-signal, and RF design challenges. For more information and/or support, visit w ww.analog.com/CN0238.

ADA4960-1

12-Bit, 500 MSPS 1.8 V Analog-to-Digital Converter

5 GHz, Ultralow Distortion RF/IF Differential Amplifier

High Performance, 12-Bit, 500 MSPS Wideband Receiver with Antialiasing Filter

EVALUATION AND DESIGN SUPPORT

Design and Integration Files

Schematics, Layout Files, Bill of Materials

CIRCUIT FUNCTION AND BENEFITS

The circuit shown in Figure 1 is a wideband receiver front end based on the ADA4960-1 ultralow noise differential amplifier driver and the AD9434 12-bit, 500 MSPS analog-to-digital

converter (ADC). The third-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and ADC. The total insertion loss due to the filter network, transformer, and other resistive components is only 1.2 dB.

The overall circuit has a bandwidth of 290 MHz with a pass-band flatness of 1 dB. The SNR and SFDR measured with a 140 MHz analog input are 64.1 dBFS and 70.4 dBc, respectively.

1.1dB LOSS

ANALOG

INPUT

+5.4dBm FS

AT 10MHz

INPUT

Z = 50

OVERALL GAIN = 2. 3dB

0.8dB LO SS 0.3dB LOSS

18pF

5

22nH

62

3.3pF

62

22nH

0.1µF

18pF

33870101

5

511

5

FS = 1.5V p-p DIFF

+1.8V

1.3pF1k

0.1dB LO SS

XFMR

1:1 Z

ECT1-1-13M

25

0.1µF

140

0.1µF

= 10k

3.4dB GAI N

+5V

VIP

IIP

IIN

VIN

–

0.1µF

75

ADA4960-1

G = 3.4dB

75

0.1µF

Figure 1. 12-Bit, 500 MSPS Wideband Receiver Front End (Simplified Schematic: All Connections and Decoupling Not Shown)

Gains, Losses, and Signal Levels Measured Values at 10 MHz

AD9434

ADC

INTERNAL

INPUT Z

10146-001

Rev. A

Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page)

Page 2

CN-0238 Circuit Note

CIRCUIT DESCRIPTION

The circuit accepts a single-ended input and converts it to differential using a wide bandwidth (3 GHz) M/A-COM ECT1-1-13M 1:1 transformer. The 5 GHz ADA4960-1 differential amplifier has a differential input impedance of 10 kΩ. Gain can be adjusted from 0 dB to 18 dB with the selection of the external gain-setting resistor, RG. The output impedance is 150 Ω differential.

The ADA4960-1 is an ideal driver for the AD9434, and the fully differential architecture through the low-pass filter and into the ADC provides good high frequency common-mode rejection, as well as minimizes second-order distortion products. The

ADA4960-1 provides a gain of 0 dB to 18 dB, depending on the

external gain resistor. In the circuit, a gain of 3.4 dB was used to compensate for the insertion loss of the filter network (1.1 dB) and the transformer (0.1 dB), providing an overall signal gain of

2.3 dB. An input signal of approximately 5.4 dBm produces a full-scale 1.5 V p-p differential signal at the ADC input.

The antialiasing filter is a third-order Butterworth filter designed with a standard filter design program. A Butterworth filter was chosen because of its flat response within the pass band. A third order filter yields an ac noise bandwidth ratio of 1.05 and can be designed with the aid of several free filter programs such as Nuhertz Technologies Filter Free or the Quite Universal Circuit Simulator (Qucs) Free Simulation.

In order to achieve best performance, the ADA4960-1 should be loaded with a net differential load of 100 Ω. The 5 Ω series resistors isolate the filter capacitance from the amplifier output, and the 62 Ω resistors in parallel with the downstream impedance yield a net load impedance of 101 Ω when added to the 10 Ω series resistance.

The 5 Ω resistors in series with the ADC inputs isolate internal switching transients from the filter and the amplifier. The 511 Ω resistor in parallel with the ADC serves to reduce the input impedance of the ADC for more predictable performance.

The third-order Butterworth filter was designed with a source impedance of 70 Ω, a load impedance of 338 Ω, and a 3 dB bandwidth of 360 MHz. The calculated values from the program are shown in Figure 2.

35.0

Figure 2. Design for Third-Order Differential Butterworth Filter with

22.04n

3.379pF 10.01pF

22.04nH

= 70 Ω, ZL = 338 Ω, FC = 360 MHz

338

10146-002

The values chosen for the filter’s passive components were the closest standard values to those generated by the program.

The internal 1.3 pF capacitance of the ADC was subtracted from the value of the second shunt capacitor (10.01 pF) to yield a value of 8.71 pF. In the circuit, this capacitor was realized using two 18 pF capacitors connected to ground as shown in Figure 1. This provides the same filtering effect, as well as offering some ac common-mode rejection.

The measured performance of the system is summarized in Tab le 1 , where the 3 dB bandwidth is 290 MHz. The total insertion loss of the network is approximately 1.1 dB. The bandwidth response is shown in Figure 3; the SNR and SFDR performance are shown in Figure 4.

Table 1. Measured Performance of the Circuit

Performance Specs at 1.5 V p-p FS Final Results

Cutoff Frequency (−3 dB) 290 MHz Pass-Band Flatness (6 MHz to 200 MHz) 1 dB SNRFS at 140 MHz 64.1 dBFS SFDR at 140 MHz 70.4 dBc H2/H3 at 140 MHz 85.0 dBc/70.4 dBc Overall Gain at 10 MHz 2.3 dB Input Drive at 10 MHz 5.4 dBm

–2

–4

–6

–8

–10

–12

AMPLITUDE (dBFS)

–14

–16

–18

–20

1M 10M 100M 1G

ANALOG INPUT F REQUENCY (Hz)

Figure 3. Pass-Band Flatness Performance vs. Frequency

3dB AT 290MHz

10146-003

Rev. A | Page 2 of 6

Page 3

Circuit Note CN-0238

SNRFS (dBFS), SFDR (dBc)

0 50 100 150 200 250 300

SFDR (dBc)

SNRFS (dBFS)

ANALOG INPUT FREQUENCY (MHz)

Figure 4. SNR/SFDR Performance vs. Frequency

10146-004

Filter and Interface Design Procedure

To achieve optimum performance (bandwidth, SNR, and SFDR), there are certain design constraints placed on the general circuit by the amplifier and the ADC:

1. The amplifier should see the correct dc load recommended

by the data sheet for optimum performance.

2. The correct amount of series resistance must be used

between the amplifier and the load presented by the filter. This is to prevent undesired peaking in the pass band.

3. The input to the ADC should be reduced by an external

parallel resistor, and the correct series resistance should be used to isolate the ADC from the filter. This series resistor also reduces peaking.

The generalized circuit shown in Figure 5 applies to most high speed differential amplifier/ADC interfaces and will be used as a basis for the discussion. This design approach tends to minimize the insertion loss of the filter by taking advantage of the relatively high input impedance of most high speed ADCs and the relatively low impedance of the driving source (amplifier).

FILTER

AAF2

AAFL

0.1µF

TADC

ADC

= R

AAFL

= 2RA + (Z

= 2R

AAFS

TADC

AAFL

TAMP

ADC

INTERNAL

INPUT Z

 (R

+ 2RKB)

ADC

 2R

TAMP

 (ZO+ 2RA)

)

10146-005

ANALOG

INPUT

Z = 50

Z = 2R

 R

XFMR

1:1 Z

ECT1-1-13M

AAFS

AAF

AAF1

AAF

0.1µF

ZO/2

GAIN

0.1µF

TAMP

0.1µF

Figure 5. Generalized Differential Amplifier/ADC Interface with Low-Pass Filter

Rev. A | Page 3 of 6

Page 4

CN-0238 Circuit Note

The basic design process is as follows:

1. Select the external ADC termination resistor R

the parallel combination of R

TAD C

and R

is between 200 Ω

ADC

TAD C

so that

and 400 Ω.

2. Select R

based on experience and/or the ADC data sheet

recommendations, typically between 5 Ω and 36 Ω.

3. Calculate the filter load impedance using:

= R

|| (R

AAFL

TADC

4. Select the amplifier external series resistor R

+ 2RKB)

ADC

. Make RA less

than 10 Ω if the amplifier differential output impedance is 100 Ω to 200 Ω. Make R

between 5 Ω and 36 Ω if the

output impedance of the amplifier is 12 Ω or less.

5. Select R

so that the total load seen by the amplifier, ZAL,

TAM P

is optimum for the particular differential amplifier chosen using the equation:

= 2RA + (Z

AAFL

|| 2R

TAMP

)

6. Calculate the filter source resistance:

AAFS

= 2R

|| (ZO + 2RA)

TAMP

7. Using a filter design program or tables, design the filter

using the source and load impedances, Z

AAFS

and Z

AAFL

, type of filter, bandwidth, and order. Use a bandwidth that is about 40% higher than one-half the sampling rate to ensure flatness in the frequency span between dc and fs/2.

8. The internal ADC capacitance, C

, should be subtracted

ADC

from the final shunt capacitor value generated by the program. The program will give the value C

SHUNT2

for the differential shunt capacitor. The final common-mode shunt capacitance is

AAF2

= 2(C

SHUNT2

− C

ADC

)

After running these preliminary calculations, the circuit should be given a quick review for the following items.

1. The value of C

several times larger than C sensitivity of the filter to variations in C

2. The ratio of Z

should be at least 10 pF so that it is

AAF2

. This minimizes the

ADC

AAFL

to Z

should not be more than about

AAFS

7 so that the filter is within the limits of most filter tables and design programs.

3. The value of C

should be at least 5 pF to minimize

AAF1

sensitivity to parasitic capacitance and component variations.

4. The inductor, L

, should be a reasonable value of at

AAF

least several nH.

In some cases, the filter design program may provide more than one unique solution, especially with higher order filters. The solution that uses the most reasonable set of component values should always be chosen. Also, choose a configuration that ends in a shunt capacitor so that it can be combined with the ADC input capacitance.

Circuit Optimization Techniques and Trade-Offs

The parameters in this interface circuit are very interactive; therefore, it is almost impossible to optimize the circuit for all key specifications (bandwidth, bandwidth flatness, SNR, SFDR, and gain). However, the peaking, which often occurs in the bandwidth response, can be minimized by varying R

and RKB.

The pass-band peaking is reduced as the value of the output series resistance, R

, is increased. However, as the value of this

resistance increases, there is more signal attenuation, and the amplifier must drive a larger signal to fill the ADC’s full-scale input range.

The value of R

also affects SNR performance. Larger values,

while reducing the bandwidth peaking, tend to slightly increase the SNR because of the higher signal level required to drive the ADC full scale.

Select the R

series resistor on the ADC inputs to minimize

distortion caused by any residual charge injection from the internal sampling capacitor within the ADC. Increasing this resistor also tends to reduce bandwidth peaking.

However, increasing R

increases signal attenuation, and the

amplifier must drive a larger signal to fill the ADC input range.

Another method for optimizing the pass-band flatness is to vary the filter shunt capacitor, C

Normally, the ADC input termination resistor, R

, by a small amount.

AAF2

, is selected

TAD C

to make the net ADC input impedance between 200 Ω and 400 Ω. Making it lower reduces the effect of the ADC input capacitance and may stabilize the filter design; however, it increases the insertion loss of the circuit. Increasing the value also reduces peaking.

Balancing these trade-offs can be somewhat difficult. In this design, each parameter was given equal weight; therefore, the values chosen are representative of the interface performance for all the design characteristics. In some designs, different values may be chosen to optimize SFDR, SNR, or input drive level, depending on system requirements.

Note that the signal in this design is ac coupled with the 0.1 μF capacitors to block the common-mode voltages between the amplifier, its termination resistors, and the ADC inputs. Refer to the AD9434 data sheet for further details regarding common-mode voltages.

Rev. A | Page 4 of 6

Page 5

Circuit Note CN-0238

Passive Component and PC Board Parasitic Considerations

The performance of this or any high speed circuit is highly dependent on proper PCB layout. This includes, but is not limited to, power supply bypassing, controlled impedance lines (where required), component placement, signal routing, and power and ground planes. See Tu to r ia l MT-031 and Tu t or i a l

MT-101 for more detailed information regarding PCB layout

for high speed ADCs and amplifiers.

Low parasitic surface-mount capacitors, inductors, and resistors should be used for the passive components in the filter. The inductors chosen are from the Coilcraft 0603CS series. The surfacemount capacitors used in the filter are 5%, C0G, 0402-type for stability and accuracy.

See the CN-0238 Design Support Package for complete documentation on the system.

COMMON VARIATIONS

For applications that require less bandwidth, better spurious performance, and lower power, the ADA4927-1/ADA4927-2 or ADA4938-1/ADA4938-2 can be used. The ADA4927-1 has a bandwidth of 2.3 GHz and only uses 20 mA of current, while the ADA4938-1 has a bandwidth of 1.0 GHz and uses 37 mA of current.

For applications that require less resolution, the 8-bit, 500 MSPS

AD9484 is pin compatible with the AD9434. The AD9484 has an

SNR of 47 dBFS at 250 MHz analog input frequencies.

For applications that require a lower sampling rate, the 12-bit, 170 MSPS/210 MSPS/250 MSPS AD9230 is a pin-compatible ADC with approximately the same dynamic performance as the

AD9434.

Also, the 12-bit, 500 MSPS AD6641 can be considered for those applications that require digital predistortion (DPD) observation. This product has an on-chip 16k × 12-bit FIFO.

CIRCUIT EVALUATION AND TEST

This circuit uses a modified AD9434-500EBZ circuit board and the HSC-ADC-EVALCZ FPGA-based data capture board. The two boards have mating high speed connectors, allowing for the quick setup and evaluation of the circuit’s performance. The modified AD9434-500EBZ board contains the circuit evaluated as described in this note, and the HSC-ADC-EVALCZ data capture board is used in conjunction with Visual Analog evaluation software, as well as the SPI controller software to properly control the ADC and capture the data. See User Guide

UG-290 for the schematics, BOM, and layout for the AD9434-500EBZ board. The readme.txt file in the CN-0238 Design Support Package describes the modifications made to

the standard AD9434-500EBZ board. Application Note AN-835 contains complete details on how to set up the hardware and software to run the tests described in this circuit note.

LEARN MORE

CN-0238 Design Support Package:

www.analog.com/CN0238-DesignSupport

UG-290, Evaluating the AD9434 and AD9484 Analog-to-Digital

Converters. Analog Devices.

Arrants, Alex, Brad Brannon and Rob Reeder, AN-835

Application Note, Understanding High Speed ADC Testing and Evaluation. Analog Devices.

Ardizzoni, John. “A Practical Guide to High-Speed Printed-

Circuit-Board Layout.” Analog Dialogue 39-09, September

2005.

MT-031 Tutorial, Grounding Data Converters and Solving the

Mystery of “AGND” and “DGND”, Analog Devices.

MT-101 Tutorial, Decoupling Techniques, Analog Devices.

Quite Universal Circuit Simulator

Nuhertz Technologies, Filter Free Filter Design Program

Reeder, Rob, Achieve CM Convergence between Amps and ADCs,

Electronic Design, July 2010.

Reeder, Rob, Mine These High-Speed ADC Layout Nuggets For

Design Gold, Electronic Design, September 15, 2011.

Rarely Asked Questions: Considerations of High-Speed

Converter PCB Design, Part 1: Power and Ground Planes, November 2010.

Rarely Asked Questions: Considerations of High-Speed

Converter PCB Design, Part 2: Using Power and Ground Planes to Your Advantage, February 2011.

Rarely Asked Questions: Considerations of High-Speed

Converter PCB Design, Part 3: The E-Pad Low Down, June

2011.

Data Sheets and Evaluation Boards

AD9434 Data Sheet

ADA4960-1 Data Sheet

Circuit Evaluation Board (AD9434-500EBZ)

Standard Data Capture Platform (HSC-ADC-EVALCZ)

Rev. A | Page 5 of 6

Page 6

CN-0238 Circuit Note

REVISION HISTORY

2/12—Rev. 0 to Rev. A

Changes to Figure 1.......................................................................... 1

12/11—Revision 0: Initial Version

(Continued from first page) Circuits fro m the Lab circuits are intended only for use with Analog Devices products an d are the intellectual property of Analog Devices or its licensors. While you may use the Circuits from the Lab circuits in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of the Circuits from the Lab circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the Lab circuits are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for thei r use, nor for any infringements of patents or other rights of third parties that may result f rom their use. Analog Devices reserves the right to change any Circuits from the Lab circuits at any time without notice but is under no obligation to do so.

Rev. A | Page 6 of 6

Datasheet CN-0238 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

EVALUATION AND DESIGN SUPPORT

CIRCUIT FUNCTION AND BENEFITS

CIRCUIT DESCRIPTION

Filter and Interface Design Procedure

Circuit Optimization Techniques and Trade-Offs

Passive Component and PC Board Parasitic Considerations

COMMON VARIATIONS

CIRCUIT EVALUATION AND TEST

LEARN MORE

Data Sheets and Evaluation Boards

REVISION HISTORY