Datasheet CMX602BE4, CMX602BD4 Datasheet (MX COM Inc)

COMMUNICATION ICs

DATA BULLETIN

CMX602B

Calling Line Identifier

plus Call Waiting (Type II)

2000 MX-COM, Inc. www.mxcom.com tel: [phone] 744 5050 fax: [phone] Doc. # 20480204.002

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks an service marks are held by their respective companies.

PRELIMINARY INFORMATION

Features Applications

•

Automatic CAS Dual Tone Detector
High Sensitivity, Low Falsing
Automatic CAS Duration Checking

• 1µ

A max. 'Zero-Power' Ring or Line

Polarity Reversal Detector

•

V23/Bell202 FSK Demodulator
with Data Retiming facility

• µµ

C Interrupt / Wake-up output to

minimize system operating power

•

Low Power Operation 0.5mA at 2.7V

DD

•

Caller ID/Caller ID on Call Waiting

Telephones
Adjunct Boxes

•

Bellcore, ETSI, British Telecom, and
Mercury Systems

•

Computer Telephone Integration

•

Call Logging Systems

•

Voice Mail Equipment

XTAL XTAL

-

+

Bandpass

Filter

FSK

Demod

Level

Detector

Tone Alert

Detector

Data

Retiming

Mode

Control

Logic

RXD
RXCLK

IN-

IN+

AMPOUT

Power

Supply

Circuits

Xtal Osc and

Clock Dividers

DET

RD

RT

V

DD

V

BIAS

V

SS

ZP

MODE

Input Signal
Amplifier

IRQ

The CMX602B is a low power CMOS device used for the reception of physical layer signals in Bellcore's
Calling Identity Delivery (CID) and Calling Identity on Call Waiting (CIDCW) systems, British Telecom Calling
Line Identification Service (CLIP), the Cable Communications Association's Caller Display Services (CDS),
and similar evolving services.

This device includes a 'zero-power' ring or line polarity reversal detector, a dual-tone (2130Hz plus 2750Hz)
internally timed CPE Alerting Signal (CAS) detector, and a 1200-baud FSK Bell202/V23 compatible
asynchronous data demodulator with data retiming circuitry which removes the need for a UART in the
associated µC.

The CMX602B is suitable for use in systems using Bellcore specifications GR-30-CORE and SR-TSV­002476, British Telecom specifications SIN227 and SIN242, CCA TW/P&E/312, ETSI: ETS 300 659 parts 1
and 2 and ETS 300 778 parts 1 and 2, and Mercury Communications MNR 19.

This device may be used with a 2.7V to 5.5V supply and is available in the following packages:
16-pin TSSOP (CMX602BE4), 16-pin SOIC (CMX602BD4) and a 16-pin PDIP (CMX602BP3).

Calling Line Identifier

plus

Call Waiting (Type II) 2 CMX602B PRELIMINARY INFORMATION

2000 MX-COM, Inc www.mxcom.com Tel: [phone] 744 5050 Fax: [phone] Doc. # 20480204.002

4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA All trademarks and service marks are held by their respective companies.

CONTENTS

Section Page

1. Block Diagram................................................................................................................3

2. Signal List.......................................................................................................................4

3. External Components....................................................................................................5

4. General Description.......................................................................................................6

4.1 Mode Control Logic ..........................................................................................................6

4.2 Input Signal Amplifier........................................................................................................ 6

4.3 Bandpass Filter................................................................................................................. 7

4.4 Level Detector .................................................................................................................. 8

4.5 FSK Demodulator.............................................................................................................8

4.6 FSK Data Retiming...........................................................................................................8

4.7 FSK Data Without Retiming.............................................................................................. 9

4.8 Tone Alert Detector......................................................................................................... 10

4.9 Ring or Line Polarity Reversal Detector.......................................................................... 10

4.10 Xtal Osc and Clock Dividers........................................................................................... 12

5. Application ...................................................................................................................12

5.1 'On-Hook' Operation....................................................................................................... 12

5.1.1 Bellcore System......................................................................................................................12

5.1.2 British Telecom System..........................................................................................................13

5.1.3 Other 'On-Hook' Systems .......................................................................................................13

5.2 'Off-Hook' Operation....................................................................................................... 15

6. Performance Specification..........................................................................................17

6.1 Electrical Performance.................................................................................................... 17

6.1.1 Absolute Maximum Ratings....................................................................................................17

6.1.2 Operating Limits......................................................................................................................17

6.1.3 Operating Characteristics .......................................................................................................18

6.2 Packaging....................................................................................................................... 21

MX-COM, Inc. reserves the right to change specifications at any time and without notice.

Calling Line Identifier

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4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA All trademarks and service marks are held by their respective companies.

1. Block Diagram

XTAL

XTAL

-

+

Bandpass

Filter

FSK

Demod

Level

Detector

Tone Alert

Detector

Data

Retiming

Mode

Control

Logic

RXD

To / From µC

RXCLK

IN-

IN+

AMPOUT

R8

R6

C6

C8

C9

R5

C5

C2

C1

X1

Power

Supply

Circuits

Xtal Osc and

Clock Dividers

DET

RD

RT

V

DD

V

BIAS

V

SS

Ring or Line Polarity

Reversal Detector input

Audio band

input

(components shown

for unbalanced input)

V

DD

3.579545MHz

ZP

MODE

Input Signal

Amplifier

IRQ

Figure 1: Block Diagram

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2. Signal List

Pin No. Signal Type Description

1

XTAL

output Output of the on-chip Xtal oscillator inverter

2 XTAL input Input to the on-chip Xtal oscillator inverter
3 RD

input

(S)

Input to the Ring or Line Polarity Reversal Detector

4 RT

input /
output

Open-drain output and Schmitt trigger input forming part of the Ring or Line
Polarity Reversal detector. An external resistor to V

DD

and a capacitor to

V

SS

should be connected to RT to filter and extend the RD input signal

5 AMPOUT output Output of the on-chip Input Signal Amplifier
6 IN - input Inverting input to the on-chip Input Signal Amplifier
7 IN + input Non-inverting input to the on-chip Input Signal Amplifier
8

V

SS

power Negative supply

9

V

BIAS

output Internally generated bias voltage, held at V

DD

/2 when the device is not in

'Zero-Power' mode. Should be bypassed to V

SS

by a capacitor mounted

close to the device pins.

10 MODE

input

(S)

Input used to select the Tone Alert or FSK Level Detection operating mode.
See Section 4.1

11 ZP

input

(S)

High level on this input selects 'Zero-Power' mode, a low level input enables
the V

BIAS

supply, the Input signal amplifier, the Bandpass Filter , and either

the FSK or the Tone alert circuits depending on the MODE input

12

IRQ

output

Open-drain output (active low) that may be used as an Interrupt Request /
Wake-up input to the associated µC. Indicates CAS Dual Tone event of
correct duration when device is in Tone Alert Detect Mode. An external pull­up resistor should be connected between this output and V

DD

.

13 DET output

Logic level output driven by the Ring or Line Polarity Reversal Detector, the
Tone Alert Detector or the FSK Level detect circuits, depending on the
operating mode. When device is in Tone Alert Mode, it may be used as a
near end voice mute control signal. See Section 4.1

14 RXCLK input

Logic level input, which may be used to clock, received data bits out of the
FSK Data Retiming block. When held high disables FSK Data Retiming
block.

15 RXD output

Logic level output carrying either the raw output of the FSK Demodulator or
re-timed 8-bit characters depending on the state of the RXCLK input. See
Section 4.6

16

V

DD

power

Positive supply.

Levels and thresholds within the device are proportional to

this voltage. Should be bypassed to V

SS

by a capacitor mounted close to the

device pins.

Notes: input (S) = Schmitt trigger input

Table 1 : Signal List

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3. External Components

Line

16
15
14
13
12
11
10

9

1
2
3
4
5
6
7
8

XTAL

V

DD

V

SS

V

BIAS

AMPOUT

IN+

IN-

RD
RT

RXD
RXCLK
DET
IRQ
ZP
MODE

X1

R1

R2

R3

R4

R5

R8

R6

R7

R9 R10

R11

D1-D4

C3

C2

C1

C4

C5

C6

C7

C8

C9

V

DD

V

DD

To/From µC

Line

Protection

Network

A

B

CMX602B

XTAL

Note:

It is recommended that the printed circuit board provide a ground plane in the CMX602B area to

provide a low impedance ground connection to the V

SS

pin and to the bypass capacitors C8 and C9.

Figure 2 : Recommended External Components for Bellcore and/or British Telecom Application

R1

470kΩ

±

1%

R11

100kΩ

±

20%

R2 Note 1

±

1%

C1, C2 18pF

±

20%

R3, R4 C3, C4

0.1µF

±

20%

R5, R6

470kΩ

±

1%

C5

0.33µF

±

20%

R7 C6, C7 680pF

±

20%

R8 Note 2, 3

470kΩ @ 3.3V
680kΩ @ 5.0V

±

1%

C8,C9

0.1µF

±

20%

R9 Note 2

240kΩ @ 3.3V
200kΩ @ 5.0V

±

1%

X1 Note 4 3.579545MHz

±

0.1%

R10

160kΩ

±

1%

D1 - D4 1N4004

Table 2: Recommended External Components

Recommended External Component Notes:

1. See Section 4.8

2. See Section 4.2

3. The recommended values of R8 were selected for applications in both Bellcore and British Telecom
Systems. Optimum Bellcore-only operation may be achieved by reducing the value of R8 e.g. to 656kΩ
@ 5.0V.

4. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at
least 40% of V

DD

, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain

crystal oscillator design assistance, consult your crystal manufacturer.

5. It is recommended that the printed circuit board be laid out with a ground plane in the CMX602B area to
provide a low impedance ground connection to the V

SS

pin and to decoupling capacitors C8 and C9.

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4. General Description

4.1 Mode Control Logic

The CMX602B's operating mode and the source of the DET and

IRQ

outputs are determined by the logic

levels applied to the MODE and ZP input pins.

ZP MODE Mode DET output from

IRQ output from

0 0 Tone Alert Detect Tone Alert Signal Detection

Valid 'off-hook' CAS Duration.
Ring or Line Polarity Reversal Detector

0 1 FSK Receive FSK Level Detector

FSK Data Retiming (if enabled). Ring or
Line Polarity Reversal Detector.

1 0 Zero-Power

Ring or Line Polarity
Reversal Detector

Ring or Line Polarity Reversal Detector.

1 1 Zero-Power

Ring or Line Polarity
Reversal Detector

None

In the 'Zero-Power' modes, power is removed from all of the internal circuitry except for the Ring or Line
Polarity Reversal Detector and the DET and

IRQ

outputs.

4.2 Input Signal Amplifier

The Input Signal Amplifier is used to convert the balanced FSK and Tone Alert signals received over the
telephone line to an unbalanced signal of the correct amplitude for the FSK receiver and Tone Alert Detector
circuits.

-

+

V

SS

V

BIAS

AMPOUT

IN+

IN-

R8R6

R7

R9 R10

C6

C7

C9

A
B

Input Signal Amplifier

Figure 3: Input Signal Amplifier, balanced input configuration

The design equations for this circuit are:

Differential Voltage Gain

V

V

= R9 =

R8 R10

(R8 - R10)

R6 = R7 = 470k R10 = 160k

AMPOUT

(B-A)

RR8

6

×

ΩΩ

The target differential voltage gain depends on the expected A and B input signal levels and the CMX602B's
internal overload and threshold levels, which are proportional to the supply voltage.

The CMX602B has been designed to meet the applicable specifications when R8 = 430kΩ at V

DD

= 3.0V

nominal, rising to 680kΩ at V

DD

= 5.0V (see note) and R9 = 240kΩ at V

DD

= 3.0V dropping to 200kΩ at

V

DD

= 5.0V as indicated in Section 3 and as shown in Figure 5. Reference Notes found in Section 3.

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The Input Signal Amplifier may also be used to allow the CMX602B to operate from an unbalanced signal
source as shown in Figure 4. In this unbalanced signal configuration, the values of R6 and R8 are the same
as used for the balanced input configuration.

-

+

V

SS

V

BIAS

AMPOUT

IN+

IN-

R8R6

C6

C9

A

Input Signal Amplifier

Figure 4: Input Signal Amplifier, unbalanced input configuration

0

100

200

300

400

500

600

700

800

900

1000

3 3.5 4 4.5 5

Nominal V

DD

R8 and R9 : k

Ω

R8

R9

Figure 5: Input Signal Amplifier, Optimum Values of R8 and R9 vs. V

DD

4.3 Bandpass Filter

The Bandpass Filter is used to attenuate out of band noise and interfering signals from reaching the FSK
Demodulator, Tone Alert Detector and Level Detector circuits. The characteristics of this filter differ between
FSK and Tone Alert modes. Switched Capacitor filter stages clocked at 57.7kHz provide primary filtering. If
the input signal is band limited to below 28.85kHz then external anti-aliasing filtering is not required.

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4.4 Level Detector

The Level Detector block operates by measuring the level of the signal at the output of the Bandpass Filter. It
then compares it against a threshold, which depends on whether FSK Receive or Tone Alert Detect mode has
been selected.

In Tone Alert Detect mode the output of the Level Detector block provides an input to the Tone Alert Signal
Detector.

In FSK Receive mode the CMX602B DET output will be set high when the level has exceeded the threshold
for a sufficient duration. Amplitude and time hysteresis are used to reduce chattering of the DET output in
marginal conditions.

Note: In FSK Receive mode, this circuit may also respond to non-FSK signals such as speech.

DET

Line Signal

MODE, ZP

FSK Receiver mode

FSK signal

t

DFON

t

DFOFF

See Section 6.1 for definitions of t

DFON

and t

DFOFF

Figure 6: FSK Level Detector Operation

4.5 FSK Demodulator

The FSK Demodulator block converts the 1200 baud FSK input signal to a digital data stream which is output
via the RXD pin as long as the Data Retiming function is not enabled (Holding RXCLK continuously high).
The RXD output does not depend on the state of the FSK Level Detector output.

Note: In the absence of a valid FSK signal, the demodulator may falsely interpret speech or other extraneous

signals as data.

4.6 FSK Data Retiming

The Data Retiming block extracts the 8 data bits of each character from the received asynchronous data
stream and presents them to the µC under the control of strobe pulses applied to the RXCLK input. The
timing of these pulses is not critical, and they may easily be generated by a simple software loop. This facility
removes the need for a UART in the µC without incurring an excessive software overhead.

The block operates on a character by character basis by first looking for the mark to space transition which
signals the beginning of the start bit. Using this transition as a timing reference, the block samples the output
of the FSK Demodulator in the middle of each of the following 8 received data bits and stores the results in an
internal 8-bit shift register.

When the eighth data bit has been clocked into the internal shift register, the CMX602B examines the RXCLK
input. If RXCLK input is low, then the

IRQ

output will be pulled low, thereby sending the first of the stored

data bits to the RXD output pin. Upon detecting that the

IRQ

output has gone low, the µC should pulse the
RXCLK pin high 8 times. The high to low transition at the end of the first 7 of these pulses will be used by the
CMX602B to shift the next data bit from the shift register onto the RXD output. At the end of the eighth pulse,
the FSK Demodulator output will be reconnected to the RXD output pin. The

IRQ

output will be cleared the

first time the RXCLK input goes high.
Thus to use the Data Retiming function, the RXCLK input should be kept low until the

IRQ

output goes low; if

the Data Retiming function is not required the RXCLK input should continuously be kept high.
The only restrictions on the timing of the RXCLK waveform are those shown in Figure 7 and the need to

complete the transfer of all eight bits into the µC within 8.3ms (to empty the buffer before the next character is
received and put into the buffer).

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START

STOP1

1

2

345678

8

Output of FSK Demod:

RXCLK input:

RXD output:

Received Character 'n'

Retimed data bits from

received character 'n'

Data Bit 1 Data Bit 2

t

D

RXCLK

RXD

IRQ output:

IRQ

t

D

t

CLO

t

CHI

t

D

t

D

= Internal CMX602B delay (max 1µS); t

CLO

= RXCLK low time (min 1µS); t

CHI

= RXCLK high time (min 1µS)

Figure 7: FSK Operation with Data Retiming

Note: If enabled, the Data Retiming block will interpret the FSK Channel Seizure signal (a sequence of

alternating mark and space bits) as valid received characters, with values of 55 (hex). Similarly it may
interpret speech or other signals as random characters.

4.7 FSK Data Without Retiming

If the Data Retiming facility is not required, the RXCLK input to the CMX602B should continuously be kept
high. The asynchronous data from the FSK Demodulator is then connected directly to the RXD output pin
and the

IRQ

output will not be activated by the FSK signal. This case is illustrated in Figure 8.

START

START

STOP

STOP

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

FSK Demod output:

RXD output:

Received Character 'n'

Figure 8: FSK Operation without Data Retiming (RXCLK always high)

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4.8 Tone Alert Detector

The Tone Alert Detector block is enabled when the CMX602B is set to Tone Alert Detector operating mode. It
then monitors the received signal for the presence of simultaneous 2130Hz and 2750Hz tones of sufficient
level and duration.

Two digital bandpass filters, centered around 2130Hz and 2750Hz, are used within the block to provide
additional rejection of interfering signals.

The CMX602B DET output will be set high while Tone Alert signal is detected.
When DET goes low at the end of the Tone Alert signal, the

IR Q

output will be pulled low, only if DET was

high for a period of time falling within the CAS qualifying time (t

QCAS

) limits (See Section 6.1).

IRQ

will

remain low until the CMX602B is switched out of Tone Detect mode. This

IRQ

falling transition indicates a

valid CAS dual-tone has occurred.
Note: The t

QCAS

timing has been optimized for the detection of 75 to 85ms CPE Alert Signals (CAS) used in

off-hook applications. The longer (88ms to 110ms) Tone Alert signal employed by British Telecom for on­hook applications will not necessarily cause

IRQ

to go low.

DET

Line Signal

IRQ will only be pulled low if
DET output was high for t

QCAS

t

DTON

t

DTOFF

MODE, ZP

Tone Alert Detect mode Other mode

IRQ

Tone Alert signal

See Section 6.1 for definitions of t

DTON

, t

DTOFF

and t

QCAS

Figure 9: Tone Alert Detector Operation

4.9 Ring or Line Polarity Reversal Detector

These circuits are used to detect the Line Polarity Reversal and Ringing signals associated with the Calling
Line Identification protocol. Figure 10 illustrates their use in a typical application.

Line

IRQ

DET

RD

RT

ZP
MODE

FromTone Alert,
Energy Detector and
Data Retiming blocks

C5

R1

R2

R5

V

DD

R3

R4

C3

C4

Line

Protection

Network

A

B

A

B

Vt

HI

V

SS

Vt

HI

V

SS

Ring Signal

Bridge Rectifier output (X)

RT

IRQ for ZP or [ZP and MODE ]

LO HI LO

DET for ZP

HI

D1-D4

Figure 10: Ring or Line Polarity Reversal Operation

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When no signal is present on the telephone line, RD will be at VSS and RT pulled to VDD by R5 so the output
of the Schmitt trigger 'B' will be low.

The ring signal is usually applied at the subscriber's exchange as an ac voltage. The ring signal is inserted in
series with one of the telephone wires and will pass through either C3 and R3 or C4 and R4 to appear at the
top end of R1 in a rectified and attenuated form.

The signal prior to R1 will be further attenuated by the potential divider formed by R1 and R2 before being
applied to the CMX602B input RD. If the amplitude of the signal appearing at RD is greater than the input
threshold (Vt

HI

) of Schmitt trigger 'A' then the N transistor connected to RT will be turned on, pulling the

voltage at RT to V

SS

by discharging the external capacitor C5. The output of the Schmitt trigger 'B' will then

go high, activating the DET and/or

IRQ

outputs depending on the states of the MODE and ZP inputs.

The minimum amplitude ringing signal that is certain to be detected is:

()

()

0.7 Vt

R1 R2 R3

R2

0.707V

HI

RMS

+

++









Where Vt

HI

is the high-going threshold voltage of the Schmitt trigger A (see Section 6.1).

With R1, R3 and R4 all 470kΩ as indicated in Figure 2, then setting R2 to 68kΩ will guarantee detection of
ringing signals of 40V

RMS

and above for VDD = 2.7 to 5.5V.

A line polarity reversal may be detected using the same circuit but there will be only one pulse at RD. The
British Telecom specification SIN242 indicates that the circuit must detect a +15V to -15V reversal between
the two lines slewing in 30ms. For a linearly changing voltage at the input to C3 (or C4), then the voltage
appearing at the RD pin will be

dV

dt

C3 1 e R2

t

T

−















−

where

()

TC3R1R2R3

=++

and

dV

dt

is the input slew rate.

For dV/dt = 500V/sec (15V in 30ms), R1, R3 and R4 all 470kΩ and C3, C4 both 0.1µF as indicated in Figure
2, then setting R2 to 390kΩ will guarantee detection at V

DD

= 5.5V.

If the time constant of R5 and C5 is large enough then the voltage on RT will remain below the threshold of
the 'B' Schmitt trigger keeping the DET and/or

IRQ

outputs active for the duration of a ring cycle

The time for the voltage on RT to charge from V

SS

towards VDD can be derived from the formula

VV1e

RT DD

t

R5C5

=−















−

As the Schmitt trigger high-going input threshold voltage (Vt

HI

) has a minimum value of 0.56 x VDD, then the
Schmitt trigger 'B' output will remain high for a time of at least 0.821 x R5 x C5 following a pulse at RD.

Using the values provided in Figure 2 (470kΩ and 0.33µF) gives a minimum time of 100ms (independent of
V

DD

), which is adequate for ring frequencies of 10Hz or above.

If necessary, the µC can distinguish between a ring and a reversal by timing the length of the

IRQ

or DET

output.

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4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA All trademarks and service marks are held by their respective companies.

4.10 Xtal Osc and Clock Dividers

A 3.579545MHz clock present at the XTAL pin determines frequency and timing accuracy of the CMX602B.
This may be generated by the on-chip oscillator inverter using the external components C1, C2, and X1 of
Figure 2, or may be supplied from an external source to the XTAL input, in which case C1, C2, and X1 should
not be fitted.

The oscillator is turned off in the 'Zero-Power' modes.
If the clock is provided by an external source which is not always running, then the ZP input must be set high

when the clock is not available. Failure to observe this rule may cause a significant rise in the supply current
drawn by CMX602B as well as generating undefined states of the RXD, DET, and

IRQ

outputs.

5. Application

5.1 'On-Hook' Operation

The systems described in this section operate when the telephone set is not in use (on-hook) to display the
number of a calling party before the call is answered. System specific descriptions are provided as well as a
flowchart for on-hook applications (Figure 13).

5.1.1 Bellcore System

Figure 11 illustrates the line signaling and CMX602B input and output signals for the Bellcore 'On-Hook'
Caller ID system as defined in Bellcore documents GR-30-CORE and SR-TSV-002476 and also in ETS 300
659-1 Section 6.1.1.

As for the British Telecom system, the 'Chan Seize' signal is a '1010…' FSK bit sequence. The Bellcore
specifications do not require AC or DC line terminations while the FSK data is being received, however ETS
300 659-1 allows for the possibility of an AC termination begin applied.

Note: For simplicity of presentation, the Data Retiming function is not used in Figure 11 (RXCLK is kept high).

FIRST

RING

CHAN
SEIZE

MARK MESSAGE

RINGING

 250ms

3400 to 4400 ms

 200ms250ms 150ms

SIGNALING

RD
RT

IRQ

MODE

ZP

DET
RXD

FSK IDLEFSK IDLE FSK DATA

FSK DATA

FSK DATA

Figure 11: Bellcore On-hook System Signals

Calling Line Identifier

plus

Call Waiting (Type II) 13 CMX602B PRELIMINARY INFORMATION

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4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA All trademarks and service marks are held by their respective companies.

5.1.2 British Telecom System

Figure 12 illustrates the line signaling and CMX602B input and output signals for the British Telecom 'On­Hook' Caller ID system as defined in the British Telecom specifications SIN227 and SIN242 part 1. A similar
system is described in ETSI 300 659-1 Section 6.1.2c.

The Tone Alert signal consists of simultaneous 2130Hz and 2750Hz tones. The 'Chan Seize' signal consists
of a '1010..' FSK bit sequence. Not shown are the requirements for AC and DC loads, including a short initial
Current Wetting Pulse, to be applied to the line 20ms after the end of the Tone Alert signal and to be
maintained during reception of the FSK signal.

Note: For simplicity of presentation, the Data Retiming function is not used in Figure 12 (RXCLK is kept high).

[1]

IDLE 1 + IDLE 2 5 sec.

[2]

may go low at end of DET high period, but this is not guaranteed.IRQ

TONE

ALERT

CHAN
SEIZE

MARK MESSAGE

RINGING

Line

reversal

IDLE 1

100ms

4.8 sec





[1]

[2]

88-110ms  200ms80-262ms 45-75ms  2.5 sec

LINE

SIGNALING

RD

RT

IRQ

MODE

ZP

DET

RXD

IDLE 2

45ms

4.8 sec





[1]

FSK IDLEFSK IDLE

FSK DATAFSK DATA

Figure 12: British Telecom System Signals

5.1.3 Other 'On-Hook' Systems

ETS 300 659-1 also allows for systems where the FSK transmission is preceded by a Dual Tone Alert signal
similar to that used by British Telecom but without line reversal (ETS 300 659-1 Section 6.1.2a) or by a
Ringing Pulse alerting Signal (ETS 300 659-1 Section 6.1.2b).

The U.K. CCA (Cable Communications Association) specification TW/P&E/312 precedes the FSK signals by
a 200 to 450ms ring burst. AC and DC line terminations during FSK reception are optional.

Mercury Communications Ltd. Specification MNR 19 allows for either the British Telecom system or that
specified by CCA.

As these are all slight variants on the Bellcore and British Telecom systems, they can also be supported by
the CMX602B.

Calling Line Identifier

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Call Waiting (Type II) 14 CMX602B PRELIMINARY INFORMATION

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Yes

Yes

Yes

Yes

Yes

No

No

No

No

No

START:(BT)

CMX602B in ZP mode

START:(Bellcore)

CMX602B in ZP mode

END

Timeout

expired

Line Reversal

Detected ?

End of

ring signal ?

Ring signal

detected ?

CMX602B DET

output high ?

CMX602B DET

output low?

Set CMX602B to

Tone Alert Detect mode.

Start 5 second timeout.

Apply

Current Wetting Pulse,

AC and DC terminations.

Set CMX602B to

FSK Receive mode.

Restart 5 second timeout.

Set CMX602B to

FSK Receive mode.

Start 5 second timeout.

Wait 15ms

Clear timeout.

Remove any AC and DC

line terminations.

Set CMX602B to

Zero Power mode.

Read FSK Message,

display data if

checksum OK.

Figure 13: Flow Chart for 'On-Hook' Operation of CMX602B

Calling Line Identifier

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5.2 'Off-Hook' Operation

The CIDCW (Calling Identity on Call Waiting) system, as described in this section, operates when the
telephone set is in use (off-hook) to display the number of a waiting caller without interrupting the current call.

Bellcore documents GR-30-CORE and SR-TSV-002476, British Telecom specifications SIN227 and SIN242
part 2 and ETS 300-659-2 all describe similar systems in which a successful CIDCW transaction consists of a
sequence of actions between the near end CPE (Customer Premises Equipment - e.g. a telephone) and the
Central Office as indicated in Figure 14.

CAS

ACK

FSK data

D

CE

B

far voice

near voice

Signals originating
from far end CPE
and Central Office

Signals originating
at near end CPE

far voice

near voice

A

F

A. Normal conversation with both near and far voice present.
B. Central Office mutes far end voice, emits CAS, and becomes silent.
C. CPE recognizes CIDCW initiation and mutes near end voice and keypad.
D. CPE emits DTMF ACK to Central Office to signal its readiness to receive Caller ID data stream.
E. Central Office recognizes ACK and emits FSK Data stream of Caller ID data which is received and

decoded by CPE.

F. CIDCW transaction is complete. CPE unmutes near end voice and Central Office unmutes far end voice

returning to normal conversation with both near and far voice present.

Figure 14 CIDCW Transaction From Near End CPE Perspective

The CAS signal is transmitted by the Central Office to initiate a CIDCW transaction and consists of an 80ms
burst of simultaneous 2130Hz and 2750Hz tones.

CAS detection is very important because a 'missed' signal causes Caller ID information to be lost and a false
signal detection produces a disruptive tone which is heard by the far end caller. Because the CAS signals
must be detected in the presence of conversations, which both mask and masquerade as the tone signals,
this function is difficult to accomplish correctly.

Because the number of false responses (Talk-offs) and missed signals (Talk-downs) are related to the speech
levels at the CMX602B input, the level of near end speech from the local handset is normally greater than that
of far end speech coming from the Central Office. A further improvement in overall performance can be
obtained by taking the CMX602B's audio input from the receive side of the telephone set hybrid where this is
possible.

The internal algorithms used by the CMX602B to drive the DET and

IRQ

outputs in Tone Alert Detect mode
have been optimized for the detection of off-hook CAS signals in the presence of speech when used
according to the following principles:

1. If it is possible to mute the local speech from the microphone rapidly (within 0.5ms) without introducing

noise (i.e. where the CIDCW equipment is built into the telephone set), then this muting should be done
whenever the CMX602B is in Tone Alert Detect mode and the DET output is high. Doing this will
markedly reduce the number of false responses generated by local (near end) speech. Note that the
DET output is not used for any other purpose in an off-hook application when the CMX602B is set to
Tone Alert Detect mode.

2. When the

IRQ

output goes low in Tone Alert Detect mode, this indicates that a CAS has been detected.
The local handset and keypad should then be muted as required by the Bellcore specification and the
CMX602B switched to FSK Receive mode to be ready to receive the FSK data. Doing this will also clear
the

IRQ

output.

3. The CMX602B's DET output should be monitored for a period of 50ms after changing to FSK Receive
mode and before sending the ACK signal. The transaction should be abandoned if the DET output goes
high during this time, which would be the case if a false CAS detect had been caused by far end speech.

Calling Line Identifier

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Call Waiting (Type II) 16 CMX602B PRELIMINARY INFORMATION

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4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA All trademarks and service marks are held by their respective companies.

Yes (See Note 2)

Yes

Yes

No

No (See Note 3)

No

START

CMX602B in Tone Alert

Detect mode

2 second timeout

expired

Notes:

1. If it is possible to mute the speech output
from the local microphone quickly and without
introducing noise, then this should be done
whenever the CMX602B DET output is high.

2. The output will be reset by changing
from Tone Alert Detect to FSK Receive mode.

IRQ

3. When monitoring the CMX602B DET output for
the 50ms period after changing to FSK mode
note that changing between Tone Alert Detect
and FSK Receive modes resets the DET output.
It will then remain low for at least 15ms, after
which if it does go high, it will remain high for at
least 8ms.

IRQ output

low ?

Timer > 50ms ?

CMX602B DET

output high ?

Mute local handset

and keypad.

See Note 1

Send ACK.

Start 2 second timeout.

Set CMX602B to

FSK Receive mode.

Start timer.

Clear timeout.

Remove mute from

handset and keypad.

Set CMX602B to

Tone Alert Detect mode.

Read FSK Message,

display data if

checksum OK.

Figure 15, Flow Chart for 'Off-Hook' Operation of CMX602B

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6. Performance Specification

6.1 Electrical Performance

6.1.1 Absolute Maximum Ratings

Exceeding these maximum ratings can result in damage to the device.

Min. Max. Units

Supply (VDD - VSS)

-0.3 7.0 V

Voltage on any pin to VSS

-0.3

V

DD

+ 0.3

V

Current into or out of VDD and VSS pins

-30 30 mA

Current into or out of any other pin -20 20 mA

D4 / P3 Package

Total Allowable Power Dissipation at T

AMB

= 25°C

800 mW

Derating above 25°C°

13 mW/°C above 25°C

Storage Temperature -55 125 °C
Operating Temperature -40 85 °C

E4 Package

Total Allowable Power Dissipation at T

AMB

= 25°C

300 mW

Derating above 25°C°

5 mW/°C above 25°C

Storage Temperature -55 125 °C
Operating Temperature -40 85 °C

6.1.2 Operating Limits

Correct operation of the device outside these limits is not implied.

Notes Min. Max. Units

Supply (V

DD

- VSS)

1 2.7 5.5 V

Operating Temperature 1 -40 85 °C
Xtal frequency 2 3.575965 3.583125 MHz

Operating Limits Notes:

1. Operating temperature range –10°C to 60°C at V

DD

< 3.0V.

2. A Xtal frequency of 3.579545MHz ±0.1% is required for correct Tone Alert and FSK detection.

Calling Line Identifier

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Call Waiting (Type II) 18 CMX602B PRELIMINARY INFORMATION

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4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA All trademarks and service marks are held by their respective companies.

6.1.3 Operating Characteristics

For the following conditions unless otherwise specified:
V

DD

= 2.7V at T

AMB

= 10°C to 60°C and V

DD

= 3.0V to 5.0V at T

AMB

= -40°C to 85°C

Xtal Frequency = 3.579545MHz ± 0.1%, 0dBV corresponds to 1.0V

RMS

Notes Min. Typ. Max. Units
DC Parameters

IDD (ZP input high) at V

DD

= 5.0V

1,2 0.02 1.0

µ

A

IDD (ZP input low) at V

DD

= 3.0V

1 0.5 1.0 mA

IDD (ZP input low) at V

DD

= 5.0V

1 1.0 2.0 mA

Logic 1 input level
(RXCLK and XTAL inputs)

70%

V

DD

Logic 0 input level
(RXCLK and XTAL inputs)

30%

V

DD

Logic input leakage current
(V

IN

= 0 to VDD) excluding XTAL input

-1.0 1.0

µ

A

Output logic 1 level (l

OH

= 360µA)

VDD - 0.4

V

Output logic 0 level (l

OL

= 360µA)

0.4 V

IRQ

output 'off' state current

(V

OUT

= VDD)

1.0 µA

Schmitt Trigger input thresholds
(Figure 16)

High going (VtHI)

(0.56)(VDD)

(0.56)(VDD) + 0.6

V

Low going (VtLO)

(0.44)(VDD) - 0.6

(0.44)(V

DD

)

V

Tone Alert Detector

'Low' tone nominal frequency 2130 Hz
'High' tone nominal frequency 2750 Hz
Start of Tone Alert signal to DET high time

(t

DTON

Figure 9)

55.0 ms

End of Tone Alert signal to DET and

IRQ

low time (t

DTOFF

Figure 9)

0.5 10.0 ms

DET high time to ensure

IRQ

goes low

(t

QCAS

see Figure 9)

8.0 45.0 ms

To ensure detection:

3

'Low' tone frequency deviation from
nominal

±0.5 %

'High' tone frequency deviation from
nominal

±0.5 %

Tone level of each simultaneously
applied tone

4 -40.0 -2.2 dBV

2750Hz tone level with respect to
2130Hz
tone level

-6.0 6.0 dB

Signal to Noise ratio 5 20.0 dB
Dual Tone Burst Duration for DET output 75 ms

Dual Tone Burst Duration to ensure

IRQ

goes low

75 85 ms

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4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA All trademarks and service marks are held by their respective companies.

Notes Min. Typ. Max. Units

To ensure non-detection:

6

'Low' tone frequency deviation from
nominal

±75 Hz

'High' tone frequency deviation from
nominal

±95 Hz

Level (total) 4 -46.0 dBV
Dual Tone Burst Duration 45.0 ms

FSK Receiver

Transmission rate 1188 1200 1212 Baud
V23 Mark (logic 1) frequency 1280 1300 1320 Hz
V23 Space (logic 0) frequency 2068 2100 2132 Hz
Bell202 Mark (logic 1) frequency 1188 1200 1212 Hz
Bell202 Space (logic 0) frequency 2178 2200 2222 Hz
Valid input level range 4 -40.0 -8.0 dBV
Acceptable twist (mark level with respect

to space level)

V23 -6.0 6.0 dB
Bell202 -10.0 10.0 dB

Acceptable Signal to Noise ratio

V23 5 20.0 dB

Bell202 5 30.0 dB
Level Detector 'on' threshold level 4 -40.0 dBV
Level Detector 'off' to 'on' time (t

DFON

Figure 6)

25.0 ms

Level Detector 'on' to 'off' time
(t

DFOFF

Figure 6)

8.0 ms

Input Signal Amplifier

Input impedance 7 10.0

MΩ

Voltage gain 500 V/V

XTAL Input

'High' pulse width 8 100 ns
'Low' pulse width 8 100 ns

Operating Characteristics Notes:

1. At 25°C, not including any current drawn from the CMX602B pins by external circuitry other than X1, C1,
and C2.

2. RD, MODE, RXCLK inputs at V

SS

, ZP input at VDD. See Figure 17.

3. All conditions must be met to ensure detection.

4. For V

DD

= 3.3V with equal level tones and with the input signal amplifier external components as shown

in Section 3. The internal threshold levels are proportional to V

DD

. For other supply voltages or different

signal level ranges the voltage gain of the input signal amplifier should be adjusted by selecting the
appropriate external components as described in Section 4.2

5. Flat Noise in the 300Hz-3400Hz band for V23 and 200Hz-3200Hz for Bell202.

6. Meeting any of these conditions will ensure non-detection.

7. Open loop, small signal, low frequency measurements.

8. Timing for an external input to the XTAL pin.

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0

0.5

1

1.5

2

2.5

3

3.5

4

3 3.5 4 4.5 5 5.5

V

DD

V

IN

Vt

HI

Vt

LO

Figure 16: Schmitt Trigger typical input voltage thresholds vs. V

DD

0.0001

0.001

0.01

0.1

1

10

-40-30-20-100 1020304050607080
Temperature

µA

Figure 17: Typical 'Zero-Power' I

DD

vs. Temperature (VDD = 5.0V)

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Call Waiting (Type II) 21 CMX602B PRELIMINARY INFORMATION

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6.2 Packaging

Figure 18: 16-pin TSSOP Mechanical Outline:

Order as part no. CMX602BE4

PIN 1

A

B

ALTERNATIVE

PIN

LOCATION

MARKING

X

P

J

Y

C

K

H

E

L

T

W

Z

NOTE: All dimensions in inches (mm.)

Angles are in degrees

PackageTolerances

A
B
C
E
H

TYP.

MAX.MIN.

DIM.

J

P

X

W

T

Y

K
L

0.105 (2.67)0.093 (2.36)

0.419 (10.64)

45°

7°

0° 10°

0.050 (1.27)

0.041 (1.04)

0.413 (10.49)

0.299 (7.59)

0.050 (1.27)

0.016 (0.41)

0.390 (9.90)

0.020 (0.51)0.003 (0.08)

0.009 (0.23) 0.0125 (0.32)

0.013 (0.33) 0.020 (0.51)

0.395 (10.03)

0.286 (7.26)

Z

5°

5°

Figure 19: 16-pin SOIC Mechanical Outline:

Order as part no. CMX602BD4

Calling Line Identifier

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Call Waiting (Type II) 22 CMX602B PRELIMINARY INFORMATION

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4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA All trademarks and service marks are held by their respective companies.

PackageTolerances

NOTE: All dimensions in inches (mm.)

Angles are in degrees

TYP. MAX.MIN.
A
B
C
E

E1

H

DIM.

J

J1

P
Y

T

K

L

0.200 (5.06)

0.262 (6.63)

0.390 (9.91).

7°

0.150 (3.81)

0.810 (20.57)

0.135 (3.43)

0.100 (2.54)

0.121 (3.07)

0.300 (7.62)

0.290 (7.37) 0.325 (8.26)

0.015 (0.38) 0.070 (1.77)

0.008 (0.20) 0.015 (0.38)

0.014 (0.35) 0.023 (0.58)

0.040 (1.02) 0.065 (1.65)

0.056 (1.42) 0.064 (1.63)

0.740 (18.80)

0.240 (6.10)

B

A

PIN 1

E

Y

E1

T

K
H

J1

J

C

P

L

Figure 20: 16-pin PDIP Mechanical Outline:

Order as part no. CMX602BP3