Datasheet CM8870PE, CM8870P, CM8870FI, CM8870F, CM8870CSI Datasheet (California Micro Devices)

CALIFORNIA MICRO DEVICES

CMOS Integrated DTMF Receiver

CM8870/70C

Features

• Full DTMF receiver

• Less than 35mW power consumption

• Industrial temperature range

• Uses quartz crystal or ceramic resonators

• Adjustable acquisition and release times

• 18-pin DIP, 18-pin DIP EIAJ, 18-pin SOIC, 20-pin
PLCC

• CM8870C

— Power down mode

— Inhibit mode

— Buffered OSC3 output (PLCC package only)

• CM8870C is fully compatible with CM8870 for 18-pin
devices by grounding pins 5 and 6

Applications

• PABX

• Central office

• Mobile radio

• Remote control

• Remote data entry

• Call limiting

• Telephone answering systems

• Paging systems

Product Description

The CAMD CM8870/70C provides full DTMF receiver capability by integrating both the bandsplit filter and digital
decoder functions into a single 18-pin DIP, SOIC, or 20-pin PLCC package. The CM8870/70C is manufactured using
state-of-the-art CMOS process technology for low power consumption (35mW, max.) and precise data handling. The
filter section uses a switched capacitor technique for both high and low group filters and dial tone rejection. The
CM8870/70C decoder uses digital counting techniques for the detection and decoding of all 16 DTMF tone pairs into a
4-bit code. This DTMF receiver minimizes external component count by providing an on-chip differential input ampli­fier, clock generator, and a latched three-state interface bus. The on-chip clock generator requires only a low cost TV
crystal or ceramic resonator as an external component.

© 2000 California Micro Devices Corp. All rights reserved.

9/28/2000

215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com

+##'

1

CALIFORNIA MICRO DEVICES

CM8870/70C

Absolute Maximum Ratings: (Note 1)

retemaraPlobmySeulaV

-

V(egatloVylppuSrewoP

)

V

SS

DD

V

DD

niPynanoegatloVcdVV

niPynanotnerruCI

erutarepmeTgnitarepOT

erutarepmeTegarotST

DD

A

S

SGNITARMUMIXAMETULOSBA

xaMV0.6

SS

VotV3.0-

V3.0+

DD

xaMAm01

C°58+otC°04-

C°051+otC°56-

This device contains input protection
against damage due to high static
voltages or electric fields; however,
precautions should be taken to avoid
application of voltages higher than the
maximum rating.

Notes:

1. Exceeding these ratings may cause
permanent damage, functional
operation under these conditions is
not implied.

DC Characteristics: All voltages referenced to VSS, VDD = 5.0V ± 5%, TA = -40°C to +85°C unless otherwise noted.

SCITSIRETCARAHCCD

retemaraPlobmySniMpyTxaMstinUsnoitidnoCtseT

egatloVylppuSgnitarepOV

tnerruCylppuSgnitarepOI

tnerruCylppuSybdnatSI

noitpmusnoCrewoPP

egatloVtupnIleveLwoLV

egatloVtupnIleveLhgiHV

tnerruCegakaeLtupnII

EOTnotnerruC)ecruoS(pUlluPI

)-NI,+NI(,ecnadepmItupnIR

egatloVdlohserhTgnireetSV

egatloVtuptuOleveLwoLV

egatloVtuptuOleveLhgiHV

tnerruC)kniS(woLtuptuOI

tnerruC)ecruoS(hgiHtuptuOI

egatloVtuptuO

ecnatsiseRtuptuOR

V

FER

HIL/LI

V

DD

DD

QDD

O

LI

HI

os

NI

tsT

LO

HO

LO

HO

FER

RO

57.452.5V

0.30.7Am

52

µA

5153WmV;zHM975.3=f

V=DP

DD

DD

5.1V VDDV0.5=

5.3VV

1.0

5.602

µA

µA

VNIV=

SS

V0.5=

DD

V=

DD

V,V0=EOT

DD

801MΩ zHK1@

2.25.2V VDDV0.5=

30.0V V

79.4VV

0.15.2AmV

4.08.0AmV

4.27.2V V

01

ΩΚ

DD

DD

V4.0=

TUO

V6.4=

TUO

DD

V0.5=

)1etoN(

V0.5=

daoLoN,V0.5=

daoLoN,V0.5=

daoLoN,V0.5=

Operating Characteristics: All voltages referenced to VSS, VDD = 5.0V ± 5%, TA = -40°C to +85°C unless otherwise noted.

Gain Setting Amplifier

SCITSIRETCARAHCGNITAREPO

retemaraPlobmySniMpyTxaMstinUsnoitidnoCtseT

tnerruCegakaeLtupnII

ecnatsiseRtupnIR

egatloVtesffOtupnIV

noitcejeRylppuSrewoPRRSP05Bd)21etoN(zHK1

noitcejeRedoMnommoCRRMC04BdIV<V0.3-

niaGegatloVpooLnepOCDA

gniwSegatloVtuptuOV

)SG(daoLeviticapaCmumixaMCL001Fp

)SG(daoLevitsiseRmumixaMR

©2000 California Micro Devices Corp. All rights reserved.

2

215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com

NI

NI

SO

LOV

01MΩ

23Bd

001±AnV

52±Vm

htdiwdnaBniaGytinUpooLnepOcf3.0zHM

O

L

)daoLoN(egnaRedoMnommoCmcV5.2V

0.4V

P-P

05KΩ

P-P

RL≥ VotWK001

V<

SS

NI

N

daoLoN

V<

DD

V0.3<

SS

9/28/2000

CALIFORNIA MICRO DEVICES

CM8870/70C

AC Characteristics: All voltages referenced to VSS, VDD=5.0V ±5%, TA=-40°C to +85°C, f

test circuit (Fig. 1) unless otherwise noted.

SCITSIRETCARAHCCA

retemaraPlobmySniMpyTxaMstinUsetoN

sleveLlangiStupnIdilaV

)langisetisopmocfoenothcae(

tpeccAtsiwTevitisoP 01Bd

tpeccAtsiwTevitageN 01Bd

timiLtpeccAnoitaiveD.qerF zH2±%5.1.moN01,8,5,3,2

timiLtcejeRnoitaiveD.qerF%5.3±.moN5,3,2

ecnareloTenoTdrihT 61-Bd41,31,9,8,5,4,3,2

ecnareloTesioN21-Bd9,8,6,5,4,3,2

ecnareloTenoTlaiD 22+Bd9,8,7,5,4,3,2

emiTnoitceteDtneserPenoTt

emiTnoitceteDtnesbAenoTt

tpeccAnoitaruDenoTniMt

tcejeRnoitaruDenoTxaMt

tpeccAesuaPtigidretnI.niMt

tcejeResuaPtigidretnI.xaMt

)QottS(yaleDnoitagaporPt

)DtSottS(yaleDnoitagaporPt

)DtSotQ(pUteSataDtuptuOt

elbanEt

)QotEOT(yaleDnoitagaporP

elbasiDt

ycneuqerFkcolC/latsyrCf

PD

AD

CER

CER

DI

OD

QP

SPtD

SQtD

ETP

DTP

KLC

)2CSO(tuptuOkcolCeviticapaC

daoL

C

OL

92-1+mBd

5.72968Vm

58 41Sm

5.03 5.8Sm

04Sm

02Sm

04Sm

02

611

961

4.3

05Sn

003Sn

9575.35975.31385.3zHM

03Fp

=3.579545 MHz using

CLK

SMR

µS

µS

µS

µS

R

L

C

L

V=EOT

8,5,4,3,2,1

8,4,3,2

otrefeR

margaiDgnimiT

)elbatsujdAresU(

eranwohssemiT

htiwdeniatbo

)1.giFnitiucric

DD

K01= Ω

Fp05=

Notes:

1. dBm = decibels above or below a reference power

2. Digit sequence consists of all 16 DTMF tones.

3. Tone duration = 40mS. Tone pause = 40 mS.

4. Nominal DTMF frequencies are used.

5. Both tones in the composite signal have

6. Bandwidth limited (0 to 3 KHz) Gaussian Noise.

7. The precise dial tone frequencies are

8. For an error rate of better than 1 in 10,000

© 2000 California Micro Devices Corp. All rights reserved.

9/28/2000

of 1 mW into a 600 ohm load.

an equal amplitude.

(350 Hz and 440 Hz) ±2%.

215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com

9. Referenced to lowest level frequency component

10. Minimum signal acceptance level is measured with

11. Input pins defined as IN+, IN-, and TOE.

12. External voltage source used to bias V

13. This parameter also applies to a third tone injected onto

14. Referenced to Figure 1. Input DTMF tone level

in DTMF signal.

specified maximum frequency deviation.

the power supply.

at -28 dBm.

REF

.

3

CALIFORNIA MICRO DEVICES

CM8870/70C

Explanation of Events

A) Tone bursts detected, tone duration invalid, outputs not

updated.

B) Tone #n detected, tone duration valid, tone decoded

and latched in outputs.

C) End of tone #n detected, tone absent duration valid,

outputs remain latched until next valid tone.
D) Outputs switched to high impedance state.
E) Tone #n + 1 detected, tone duration valid, tone decoded

and latched in outputs (currently high impedance).
F) Acceptable dropout of tone #n + 1, tone absent duration

invalid, outputs remain latched.
G) End of tone #n + 1 detected, tone absent duration valid,

outputs remain latched until next valid tone.

Explanation of Symbols

V

DTMF composite input signal.

IN

ESt Early Steering Output. Indicates detection

of valid tone frequencies.

St/GT Steering input/guard time output. Drives

external RC timing circuit.

Q1-Q4 4-bit decoded tone output.
StD Delayed Steering Output. Indicates that

valid frequencies have been present/absent
for the required guard time, thus constituting
a valid signal.

TOE Tone Output Enable (input). A low level

shifts Q1-Q4 to its high impedance state.

t

REC

Maximum DTMF signal duration not
detected as valid.

t

REC

Minimum DTMF signal duration required
for valid recognition.

t

ID

t

DO

Minimum time between valid DTMF signals.
Maximum allowable drop-out during valid
DTMF signal.

t

DP

Time to detect the presence of valid
DTMF signals.

t

DA

Time to detect the absence of valid

DTMF signals.
t
t

GTP

GTA

Guard time, tone present.

Guard time, tone absent.

©2000 California Micro Devices Corp. All rights reserved.

4

215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com

9/28/2000

CALIFORNIA MICRO DEVICES

Functional Description

The CAMD CM8870/70C DTMF Integrated Receiver provides
the design engineer with not only low power consumption, but
high performance in a small 18-pin DIP, SOIC, or 20-pin PLCC
package configuration. The CM8870/70C’s internal architec­ture consists of a bandsplit filter section which separates the
high and low tones of the received pair, followed by a digital
decode (counting) section which verifies both the frequency
and duration of the received tones before passing the result­ant 4-bit code to the output bus.

Filter Section

Separation of the low-group and high-group tones is achieved
by applying the dual-tone signal to the inputs of two 9
switched capacitor bandpass filters. The bandwidths of these
filters correspond to the bands enclosing the low-group and
high-group tones (See Figure 3). The filter section also
incorporates notches at 350 Hz and 440 Hz which provides
excellent dial tone rejection. Each filter output is followed by a
single order switched capacitor section which smooths the
signals prior to limiting. Signal limiting is performed by high­gain comparators. These comparators are provided with a
hysteresis to prevent detection of unwanted low-level signals
and noise. The outputs of the comparators provide full-rail
logic swings at the frequencies of the incoming tones.

Decoder Section

The CM8870/70C decoder uses a digital counting technique
to determine the frequencies of the limited tones and to verify
that these tones correspond to standard DTMF frequencies.
A complex averaging algorithm is used to protect against tone
simulation by extraneous signals (such as voice) while
providing tolerance to small frequency variations. The
averaging algorithm has been developed to ensure an
optimum combination of immunity to “talk-off” and tolerance to
the presence of interfering signals (third tones) and noise.
When the detector recognizes the simultaneous presence of
two valid tones (known as “signal condition”), it raises the
“Early Steering” flag (ESt). Any subsequent loss of signal
condition will cause ESt to fall.

Steering Circuit

Before the registration of a decoded tone pair, the receiver
checks for a valid signal duration (referred to as “character­recognition-condition”). This check is performed by an
external RC time constant driven by E
causes V
Providing signal condition is maintained (ESt remains high) for
the validation period (t
the steering logic to register the tone pair, thus latching its

(See Figure 4) to rise as the capacitor discharges.

C

), VC reaches the threshold (V

GTP

corresponding 4-bit code (See Figure 2) into the output latch.
At this point, the GT output is activated and drives VC to V
GT continues to drive high as long as ESt remains high,
signaling that a received tone pair has been registered. The
contents of the output latch are made available on the 4-bit
output bus by raising the three-state control input (TOE) to a
logic high. The steering circuit works in reverse to validate the
interdigit pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver will
tolerate signal interruptions (drop outs) too short to be

. A logic high on ESt

St

th

-order

TSt

) of

DD

.

CM8870/70C

considered a valid pause. This capability together with the
capability of selecting the steering time constants externally,
allows the designer to tailor performance to meet a wide
variety of system requirements.

Guard Time Adjustment

In situations which do not require independent selection of
receive and pause, the simple steering circuit of Figure 4 is
applicable. Component values are chosen according to the
following formula:

= tDP + t

t

REC

t

» 0.67 RC

GTP

The value of t
minimum signal duration to be recognized by the receiver. A
value for C of 0.1 uF is recommended for most applications,
leaving R to be selected by the designer. For example, a
suitable value of R for a t
A typical circuit using this steering configuration is shown in
Figure 1. The timing requirements for most telecommunica­tion applications are satisfied with this circuit. Different
steering arrangements may be used to select independently
the guardtimes for tone-present (t
This may be necessary to meet system specifications which
place both accept and reject limits on both tone duration and
interdigit pause.

Guard time adjustment also allows the designer to tailor
system parameters such as talk-off and noise immunity.
Increasing t
the probability that tones simulated by speech will maintain
signal condition for long enough to be registered. On the
other hand, a relatively short t
appropriate for extremely noisy environments where fast
acquisition time and immunity to drop-outs would be require­ments. Design information for guard time adjustment is shown
in Figure 5.

Input Configuration

The input arrangement of the CM8870/70C provides a
differential input operational amplifier as well as a bias source
(V

REF

Provision is made for connection of a feedback resistor to the
op-amp output (GS) for adjustment of gain.

In a single-ended configuration, the input pins are connected
as shown in Figure 1, with the op-amp connected for unity
gain and VREF biasing the input at ½ V
differential configuration, which permits the adjustment of gain
with the feedback resistor R5.

Clock Circuit

The internal clock circuit is completed with the addition of a
standard television color burst crystal or ceramic resonator
having a resonant frequency of 3.579545 MHz. The
CM8870C in a PLCC package has a buffered oscillator output
(OSC3) that can be used to drive clock inputs of other devices
such as a microprocessor or other CM887X’s as shown in
Figure 7. Multiple CM8870/70Cs can be connected as shown
in figure 8 such that only one crystal or resonator is required.

GTP

is a parameter of the device and t

DP

of 40 milliseconds would be 300K.

REC

) and tone absent (t

GTP

improves talk-off performance, since it reduces

REC

with a long tDO would be

REC

) which is used to bias the inputs at mid-rail.

. Figure 6 shows the

DD

REC

is the

GTA

).

© 2000 California Micro Devices Corp. All rights reserved.

9/28/2000

215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com

5

CALIFORNIA MICRO DEVICES

Pin Function Table

emaNnoitpircseD

+NItupnIgnitrevni-noN

-NItupnIgnitrevnI

SGtceleSniaG

V

FER

HNIDdna,C,B,AsyekstneserpersenotfonoitcetedstibihnI

3CSO.tuptuorotallicsodereffublatigiD

DPnwoDrewoP .rotallicsoehtstibihnidnaecivedehtnwodsrewophgihcigoL

1CSOtupnIkcolC

2CSOtuptuOkcolC

V

SS

EOT QstuptuoehtselbanehgihcigoL.)tupni(elbanetuptuoetats-eerhT

Q

1

Q

2

Q

3

Q

4

DtS

tSE

tG/tS

V

DD

CI.noitcennoClanretnIVotdeitebtsuM

.)2.giFeeS(.deviecer

.ylppusrewopevitisoP

CM8870/70C

NOITCNUFNIP

reifilpmalaitnereffiddne-tnorfehtotnoitcennoC

fonoitcennocrofreifilpmalaitnereffiddne-tnorffotuptuootsseccaseviG

.rotsiserkcabdeef

Vyllanimon(tuptuoegatlovecnerefeR

DD

.)VOotdetcennocyllamron(ylppusrewopevitageN

1Q-4

VwolebsllafTG/tSnoegatlovehtnehwwolcigolotsnruteR.detadpusihctal

.

tST

VnahtretaergegatlovA.)lanoitceridib(tuptuoemitdraug/tupnignireetS

tST

)2.giFeeS(.tSnoegatlovehtdnatSEfonoitcnufasietats

SS

)ylnonoitarugifnoc0788rof(

.liar-dimtastupniehtsaibotdesuebyaM.)2/

.rotallicsolanretnisetelpmocsnipesehtneewtebdetcennoclatsyrczHM545975.3

.pu-lluplanretnI.

riapenotdilavtsalehtotgnidnopserrocedocehtsedivorp,EOTybdelbanenehW.stuptuoetats-eerhT

tuptuoehtdnaderetsigerneebsahriapenotdevieceranehwhgihcigolastneserP.tuptuognireetsdeyaleD

elbazingocerastcetedmhtiroglalatigidehtnehwyletaidemmihgihcigolastneserP.tuptuognireetsylraE

.wolcigolaotnruterottSEesuaclliwnoitidnoclangisfossolyratnemomynA.)noitidnoclangis(riapenot

ehtsesuactSadetceted

stidna,tnatsnocemitgnireetslanretxeehtteserotstcatuptuoTGehT.riapenotdetcetedehtretsigerotecived

All resistors are
All capacitors are

Figure 1.

Single Ended Input Configuration

©2000 California Micro Devices Corp. All rights reserved.

6

215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com

±±

±

1%tolerance.

±±

±±

±

5% tolerance.

±±

F

F

WOL

HGIH

YEKWOTQ4Q

Q

3

Q

2

1

79690211H0001

79663312H0010

79677413H0011
077
077
077
258
258
258

149
149

149
796
077
258

149

-

90214H0100
63315H0101
77416H0110
90217H0111
63318H1000
77419H1001
90210H1010
6331·H1011
7741#H1100
3361AH1101
3361BH1110
3361CH1111
3361DH0000

-YNALZZZZ
ecnadepmIhgiH=Z,hgiHcigoL=H,woLcigol=L

Figure 2.

Functional Diode Table

9/28/2000

CALIFORNIA MICRO DEVICES

CM8870/70C

Figure 3. Typical Filter Characteristic

Figure 4. Basic Steering Circuit

Figure 5. Guard Time Adjustment

© 2000 California Micro Devices Corp. All rights reserved.

9/28/2000

215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com

Figure 6. Differential Input Configuration

7

CALIFORNIA MICRO DEVICES

CM8870/70C

OSC1 OSC2 OSC3

OSC1 of other CM887X’s

Clock input of other devices

30pF

Figure 7. CM8870C Crystal Connection

(PLCC Package Only)

Pin Assignments

1

IN+

V

INH

OSC1

OSC2

V

IN-

GS

REF

*

IC

SS

18

2

17

3

16

4

15

5

14

6

13

7

12

CM8870C

8

11

9

10

P — Plastic DIP (18)
F — Plastic SOP

EIAJ (18)

S — SOIC (18)

V

St/GT

ESt

StD

Q4

Q3

Q2

Q1

TOE

IN+

DD

IN-

GS

V

REF

*

IC

**

IC

OSC1

OSC2

V

SS

P — Plastic DIP (18)
F — Plastic SOP

S — SOIC (18)

1

2

3

4

5

6

7

CM8870

8

9

EIAJ (18)

OSC1

3.58 Mhz 30pF 30pF

OSC1 OSC1OSC2 OSC2 OSC2

Figure 8. CM8870/70C Crystal Connection

NC

IN+

IN-

V

St/GT

3

2

1

20

V

DD

18

St/GT

17

ESt

16

StD

15

Q4

14

Q3

13

Q2

12

Q1

11

TOE

10

V

OSC1

4

GS

5

REF

IC

*

IC

CM8870 CM8870C

6

7

8

9

10

SS

V

OSC2

PE — PLCC (20)

19

V

INH

OSC3

OSC1

4

REF

5

6

PD

7

8

ESt

18

StD

17

NC

16

Q4

15

Q3

14

11

12

13

Q1

Q2

TOE

PE — PLCC (20)

GS

3

9

OSC2

DD

IN-

IN+

* — Connect To VSS

DD

IN-

IN+

IN+

IN-

V

St/GT

2

1

20

19

Est

18

StD

17

NC

16

Q4

15

Q3

14

10

11

12

13

SS

Q1

V

Q2

TOE

Ordering Information

Product Identification Number

Package

P — Plastic DIP (18)
F — Plastic SOP EIAJ (18)
PE — PLCC (20)
S — SOIC (18)

Temperature/Processing

None — 0

I — -40

©2000 California Micro Devices Corp. All rights reserved.

8

215 Topaz Street, Milpitas, California 95035 Tel: [phone] Fax: [phone] www.calmicro.com

O

C to +70OC, ±5% P.S. Tol.

O

C to +85OC, ±5% P.S. Tol.

Example:

CM8870

CM8870C

IP

9/28/2000