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CM17699. TIF
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Page 2
CM17699
The CM17699 is plasma Display Panel (PDP) data
driver board implementing 5 data drivers referenced STV7699.
This module addresses 320 column electrodes of
a plasma panel. The monoblock structure of this
module and the output Flexible Printed Circuit
(FPC) realizes a high density package for data
drivers ICs. This module is adapted to standard
definition large size PDPs. The bidirectional feature
of this module allows its implementation on the top
side and/or bottom side of the panel without any
modification in the data bit stream.
1 - CM17699 MAIN FEATURE S
- Equiped with five STV7699 devices - 4 x 16-bit
bidirectional shift register
- Mounted connectors/capacitors
- Configurable for AC/DC power supply
- FPC compatible with narrow pitches of column
electrodes
- Compatible with custom designs.
Output Count320
Output Pitch320mm
Logic Power Supply4.5V to 5.5V
Power Supply Voltage30V to 160V
Power Output Current
Clock Frequency20MHz
DimensionCOB - 92 x 33
±
40mA
FPC - 101.4 x 50
2 - CM17699 CONNECTORS DEFINITION
2.1 - Signal Connector
Input signal connector is a 50 nodes high density
connector defined as follow :
Power supplies come from 2 connectors of 3 nodes
each (V
, VDD, VSS). The use of both connectors
PP
is not necessary as all the supplies are connected
together on the board. The use of both connectors
spread the currents on the PC borad and reduce
the EMI radiations.
Depending on the application, the data module can
be configured either for DC supplies or for AC
supplies of the data drivers by the implementation
of surface mounted devices.
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Page 3
CM17699
3 - CM17699 SCHEMA T IC
Decoupling capacitors must be located as close as possible to the drivers. If the damping and protection
resistor in V
The rigid board is 92mm long by 30mm wide.
The rigid board can be mounted on the mechanical
chassis of the plasma panel or on a heat sinker by
clips and/or screws.
The recommended size of the heat sinker depends
Figure 3
92.0mm
3.3mm
CM17699
on the final application if data drivers are powered
with a DC or an AC supply .
Power supplies (V
copper surface in order to spread the current on the
board and reduce voltage drops and EMI.
The STV7699 is a Plasma Display Panel (PDP) data
driver implemented in ST’s proprietary BCD technology. Using a 4-bit wide cascadable shift register,
it drives 64 high current & high voltage outputs.
By serialy connecting several STV7699, an y horizontal pixel definition can be performed. The 20MHz
shift clock gives an eq uivalent 80MHz shift register.
The STV7699 is supplied with a separated 170V
power output s upply an d a 5V logic supply. A l l command inputs are CMOS compatible.
5/11
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CM17699
6 - STV7699 SPECIFICA T ION S
6.3 - Pad Dimensions
(in µm)
(continued)
The reference is the center of the die (x = 0, y = 0).
LEFT SIDE from top to bottom
STV7699 contains all the logic and the power
circuits necessary to drive the colums of a Plasma
Display Panel (P .D.P.). Data are shifted at each low
to high transition of the (CLK) shift clock. Data are
input in a 4-bit wide data bus to A 1 - A 4 input (case
of forward shift mode ;
F/R = low). After 16 shifts,
the first nibble is available at the serial outputs
B1 - B4. These outputs can be used to cascade
several drivers to perform any horizontal resolution.
CLK, Ai and Bi inputs are Smith trigger inputs to
improve the noise margin.
The
Forward /Reverse (F/R) input is used to select
the direction of the shift register.
The maximum frequency of the shift clock is
20MHz.
All the output data are held and mem orized into the
latch stage when the Latch input (STB) is high.
When it is at low level, data are transferred from
the shift register to the latch and to the output power
stage.
Output state can be forced to high impedance by
pulling low
When
level or high level according to
HIZ input.
BLK is Low , all t he outputs are forced to low
POL signal value.
Output state copy data that was input, with the
same polarity, when
SSLOG
, V
SSSUB
V
BLK, HIZ and POL are High.
and V
are not internally con-
SSP
nected.
V
SSLOG
and V
must be connected as close as
SSSUB
possible to the logical reference ground of the
application.
Table 1 :
Data STB POL BLK HIZ
HLHHHHCopy data
Note 1 :
Power Output Truth Table
Driver
Output
xxxxL
HIZHigh impedance
xxLxHLForced to low
xxHLHHForced to high
xHHHHQn (1) Latched data
LLHHHLCopy data
Qn is the value memorised in the latch stage ; it is the value
of the parallel shift register output stage after n Clock
pulses.
Comments
A data loaded in the shift register is read on the
output power stage without inversion of its polarity .
Table 2 :
Control Table
F/RAiBiComments
LInputOutput Forward shift
HOutputInputReverse shift
7/11
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CM17699
6 - STV7699 SPECIFICA T ION S
(continued)
6.6 - Characteristics
6.6.1 - Absolute Maximum Ratings
SymbolParameterValueUnit
V
V
V
V
I
POUT
I
DOUT
T
T
T
Note :
V
POUT
Logic Supply-0.3, +7V
CC
Logic Input Voltage-0.3, VCC + 0.3V
IN
Logic Output Voltage-0.3, VCC + 0.3V
OUT
Driver Output Voltage-0.3, +170V
Driver Power Supply-0.3, +170V
PP
Driver Output Current (1)
±
60mA
Diode Output Current (1)+40/-50mA
Junction Temperature+150°C
jmax
Operating Temperature-20, +85°C
oper
Storage Temperature-50, +150°C
stg
1. Through all power outputs : with power dissipation lower or equal than P
and junction temperature lower or equal than T
tot
jmax
6.6.2 - Electrical Characteristics
= 5V, VPP = 160V, V
(V
CC
SSP
= 0V, V
SSLOG
= 0V, V
SSSUB
= 0V , T
= 25°C, f
amb
= 20MHz,
CLK
unless otherwise specified)
SymbolParameterTest ConditionsMin.Typ.Max.Unit
SUPPLY
V
I
I
V
I
OUTPUT
OUT1-OUT64
V
POUT H
V
POUTL
V
DOUTH
V
DOUTL
I
OUTHIZ
SHIFT REGISTER OUTPUT (Ai or Bi according to F/R Status)
V
V
INPUT (CLK, STB,
Notes :
Logic Supply Voltage4.555.5V
CC
Logic Supply Current--100
CCH
Logic Supply Currentf
CCL
Power Output Supply Voltage--160V
PP
Power Output Supply Current (steady outputs)--100
PPH
Power Output High LevelI
Power Output Low LevelI
Output Diode High LevelI
Output Diode Low LevelI
= 20MHz-12TBDmA
CLK
= - 10mA, V
POUTH
I
= - 40mA, V
POUTH
= + 10mA
POUTL
I
= + 30mA
POUTL
= + 25mA (2)(3)--3V
DOUTH
= - 25mA (2)(3)---3V
DOUTL
PP
PP
= 65V
= 65V
55
TBD
-
-
60
2
125TBDVV
Output Stage Leakage Current on HIZ State--
Logic Output High LevelIOH = - 0.5mA4--V
OH
Logic Output Low LevelIOL = + 0.5mA-0.10.3V
OL
BLK, HIZ, Ai, Bi)
V
Input High Level0.8 V
IH
V
Input Low Level--0.2 V
IL
I
High Level Input CurrentVIH = V
IH
Low Level Input Current
I
IL
2. Compatible with power dissipation and T
3. See test diagram.
≤ 125°C.
joper
CC
VIL = 0V---1
CC
--1
-
-
±
10
--V
CC
-
.
µ
A
µ
A
V
V
µ
A
V
µ
A
µ
A
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CM17699
6 - STV7699 SPECIFICA T ION S
(continued)
6.6.3 - AC Timings Requirements
(V
= 4.5V to 5.5V, T
CC
= -20 to +85°C, input signals max leading edge & trailing edge (tR, tF) = 10ns)
amb
SymbolParameterMin. Typ. Max. Unit
t
t
WHCLK
t
WLCLK
t
SDAT
t
HDAT
t
DSTB
t
t
t
t
Data Clock Period50--ns
CLK
Duration of clock (CLK) pulse at high level15--ns
Duration of clock (CLK) pulse at low level15--ns
Set-up Time of data input before clock (low to high) transition0--ns
Hold Time of data input after clock (low to high) transition15--ns
Minimum Delay to latch (STB) after clock (low to high) transition20--ns
Latch (STB) Low Level Pulse Duration10--ns
STB
Blanking (BLK) Pulse Duration100--ns
BLK
Polarity (POL) Pulse Duration100--ns
POL
t
High Impedance (HIZ) Pulse Duration100--ns
HIZ
Set-up Time of Forward/Reverse Signal before Clock (low to high) transition100--ns
Logical Data Output Rise Time-TBD30ns
Logical Data Output Fall Time-TBD30ns
Delay of logic data output (high to low transition) after clock (CLK) transition
Delay of logic data output (low to high transition) after clock (CLK) transition
Delay of power output change (high to low transition) after clock (CLK) transition
Delay of power output change (low to high transition) after clock (CLK) transition-Delay of power output change (high to low transition) after Latch (STB) transition
Delay of power output change (low to high transition) after Latch (STB) transition-Delay of power output change (high to low transition) to Blank (BLK) or Polarity
(POL) transition
Delay of power output change (low to high transition) to Blank (BLK) or Polarity
POL) transition
(
Delay of power output change (high to Hi-Z transition) after high impedance (HIZ) (5)
Delay of power output change (low to Hi-Z transition) after high impedance (HIZ) (5)--
PLZ5
Delay of power output change (Hi-Z to high transition) after high impedance (HIZ) (5)
Delay of power output change (Hi-Z to low transition) after high impedance (
PZL5
Power Output Rise Time (6)--150ns
Power Output Fall Time (6)--150ns
6. One output among 64, loading capacitor C
SSP
= 0V , V
SSLOG
= 0V , V
= 50pF, other outputs at low level.
OUT
SSSUB
= 0V , T
= 25°C, V
amb
= 0.2VCC, V
ILMax.
HIZ) (5)--
-
4040TBD
TBD
TBD
TBD
TBD
--TBD
TBD
TBD
TBD
TBD
TBD
IHMin.
= 0.8VCC,
TBDnsns
120
120nsns
110
110nsns
100
100nsns
100
100nsns
100
100nsns
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CM17699
6 - STV7699 SPECIFICA T IONS
Figure 5 :
AC Characteristics Waveform
CLK
SIN
SOUT
STB
F/R
OUTn
POL
OUTn
50%50%50%
t
STB
t
PHL3
90%
10%
t
PLH3
10%
50%
(continued)
t
CLK
t
WHCLK
t
FDAT
90%
t
RDAT
50%
90%
10%
50%50%
t
PLH4
90%
t
WLCLK
t
SDAT
50%50%
t
PLH1
t
SFR
t
POL
t
PHL1
t
DSTB
t
PHL2
t
PLH2
50%
90%
10%
t
HDAT
t
PHL4
10%
"1"
"0"
"1"
"0"
"1"
"0"
"1"
50%
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
10/11
HIZ
OUTn
90%
10%
t
ROUT
90%
10%
t
FOUT
t
HIZ
50%50%
t
PHZ5
90%
10%
t
PLZ5
t
PZH5
90%
t
PZL5
"1"
"0"
"1"
10%
"0"
7699C-06.EPS
Page 11
CM17699
6 - STV7699 SPECIFICA T ION S
6.7 - Input/output Schematics
Figure 6 :
F/R, BLK, POL, HIZ
(Pins 89, 88, 87, 86)
Figure 8 :
(Pins 96 to 99)
(Pins 82 to 85)
F/R, BLK, POL, HIZ
(Pins 41-81)
Ai, Bi
A4 to A1
B1 to B4
V
SSSUB
(Pins 41-81)
(Pins 90 to 93)
V
V
SSSUB
SSLOG
(continued)
V
(Pin 100)
CC
V
SSLOG
(Pins 90 to 93)
(Pin 100)
V
CC
V
SSLOG
(Pins 90 to 93)
Figure 7 :
CLK, STB
CLK, STB
(Pins 95, 94)
V
SSSUB
7699C-07.EPS
Figure 9 :
(Pins 1, 29, 30, 51, 52, 80)
(Pins 6, 15, 24, 35, 40, 46, 57, 66, 75)
7699C-09.EPS
(Pins 41-81)
Power Output
V
PP
V
SSP
V
(Pin 100)
CC
V
SSLOG
(Pins 90 to 93)
OUTi
(Pins 2 to 5, 7 to 14, 16 to 23,
25 to 28, 31 to 34, 36 to 39,
42 to 45, 47 to 50, 53 to 56,
58 to 65, 67 to 74, 76 to 79)
7699C-08.EPS
7699C-10.EPS
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